From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5463C433EF for ; Fri, 15 Apr 2022 08:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343862AbiDOIp1 (ORCPT ); Fri, 15 Apr 2022 04:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1351609AbiDOIpC (ORCPT ); Fri, 15 Apr 2022 04:45:02 -0400 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9EF3BABB5; Fri, 15 Apr 2022 01:42:01 -0700 (PDT) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id E444A240007; Fri, 15 Apr 2022 08:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650012120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YS+pRs7LHr6e9EuekGh2X2vs14X+J67Z7alkSxxSDok=; b=ktD02ECZx7kx3kFU32mZ8y5MqdVj5y9g9zDmajeZLWYT0+97CRn6TOpV9elACOFPk/Df4o d+353r3H7Rh8mjl1F+QSic91f+PVkIVIznkWev7FSlDzX5Wd5jKalkj/EuTfDjQYs7Y0wR +rz9yb+6uMJNke5C0JTXWIvGyZVGPpsfB+AT1YpeJM0KlAeKY8VXLrbkGYpRcfPAZuJA/0 EcBBMBZvxZYzlVgedtWwx3SWlBnabgIowz28CF3S31hy5ZbF+reO8nsmMXoFBSAUPSajev DvdooxFwCagqrMJw3DZAg6uu6BU11TXuBhH5QwqrYo3hbims22/3vq3TJ+iD8g== Date: Fri, 15 Apr 2022 10:40:29 +0200 From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= To: "Russell King (Oracle)" Cc: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Heiner Kallweit , Thomas Petazzoni , Herve Codina , =?UTF-8?B?TWlxdcOobA==?= Raynal , Milan Stevanovic , Jimmy Lalande , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, Laurent Gonzales , Jean-Pierre Geslin , Phil Edworthy Subject: Re: [PATCH net-next 06/12] net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver Message-ID: <20220415104029.5e52080b@fixe.home> In-Reply-To: References: <20220414122250.158113-1-clement.leger@bootlin.com> <20220414122250.158113-7-clement.leger@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le Thu, 14 Apr 2022 14:02:10 +0100, "Russell King (Oracle)" a =C3=A9crit : > On Thu, Apr 14, 2022 at 02:22:44PM +0200, Cl=C3=A9ment L=C3=A9ger wrote: > > Add Renesas RZ/N1 advanced 5 port switch driver. This switch handles 5 > > ports including 1 CPU management port. A MDIO bus is also exposed by > > this switch and allows to communicate with PHYs connected to the ports. > > Each switch port (except for the CPU management ports) are connected to > > the MII converter. > >=20 > > This driver include basic bridging support, more support will be added > > later (vlan, etc). =20 >=20 > This patch looks to me like it needs to be updated... Hi Russell, When you say so, do you expect the VLAN support to be included ? >=20 > > +static void a5psw_phylink_validate(struct dsa_switch *ds, int port, > > + unsigned long *supported, > > + struct phylink_link_state *state) > > +{ > > + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) =3D { 0 }; > > + > > + phylink_set_port_modes(mask); > > + > > + phylink_set(mask, Autoneg); > > + phylink_set(mask, Pause); > > + phylink_set(mask, Asym_Pause); > > + > > + phylink_set(mask, 1000baseT_Full); > > + if (!dsa_is_cpu_port(ds, port)) { > > + phylink_set(mask, 10baseT_Half); > > + phylink_set(mask, 10baseT_Full); > > + phylink_set(mask, 100baseT_Half); > > + phylink_set(mask, 100baseT_Full); > > + } =20 >=20 > If the port supports e.g. RGMII (as it does via the media converter) > then it also supports 1000baseX modes as well - because a PHY attached > to the RGMII port can convert to 1000baseX. >=20 > > + > > + linkmode_and(supported, supported, mask); > > + linkmode_and(state->advertising, state->advertising, mask); > > +} =20 >=20 > This basically means "I support every phy_interface_t mode that has ever > been implemented" which surely is not what you want. I doubt from the > above that you support 10GBASE-KR for example. Hmmm yes indeed, that's not what I meant *at all*. >=20 > Please instead implement the .phylink_get_caps DSA switch interface, and > fill in the config->supported_interfaces for all interface modes that > the port supports (that including the media converter as well) and the > config->mac_capabilities members. >=20 Ok, looks indeed more fitted and easier to understand. --=20 Cl=C3=A9ment L=C3=A9ger, Embedded Linux and Kernel engineer at Bootlin https://bootlin.com