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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v3 27/60] target/arm: Make some more cpreg data static const
Date: Sun, 17 Apr 2022 10:43:53 -0700	[thread overview]
Message-ID: <20220417174426.711829-28-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org>

These particular data structures are not modified at runtime.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index d6c34c7826..94b41c7e88 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7861,7 +7861,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+        static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
               .exported_bits = 0x000f000f00ff0000,
               .fixed_bits    = 0x0000000000000011 },
@@ -8001,7 +8001,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
      */
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_RW, .accessfn = nsacr_access,
@@ -8009,7 +8009,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             };
             define_one_arm_cp_reg(cpu, &nsacr);
         } else {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR",
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL3_RW | PL1_R,
@@ -8020,7 +8020,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
     } else {
         if (arm_feature(env, ARM_FEATURE_V8)) {
-            ARMCPRegInfo nsacr = {
+            static const ARMCPRegInfo nsacr = {
                 .name = "NSACR", .type = ARM_CP_CONST,
                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
                 .access = PL1_R,
@@ -8173,13 +8173,13 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmsav7_dregion << 8
         };
-        ARMCPRegInfo crn0_wi_reginfo = {
+        static const ARMCPRegInfo crn0_wi_reginfo = {
             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
               .exported_bits = 0x00000000ffffffff },
             { .name = "REVIDR_EL1"                },
@@ -8224,7 +8224,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
-        ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
+        static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
             { .name = "MPIDR_EL1",
               .fixed_bits = 0x0000000080000000 },
         };
@@ -8303,7 +8303,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_VBAR)) {
-        ARMCPRegInfo vbar_cp_reginfo[] = {
+        static const ARMCPRegInfo vbar_cp_reginfo[] = {
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
-- 
2.25.1



  parent reply	other threads:[~2022-04-17 18:10 UTC|newest]

Thread overview: 121+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-17 17:43 [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus Richard Henderson
2022-04-17 17:43 ` [PATCH v3 01/60] tcg: Add tcg_constant_ptr Richard Henderson
2022-04-19 10:41   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8 Richard Henderson
2022-04-19 11:10   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8 Richard Henderson
2022-04-19 11:13   ` Alex Bennée
2022-04-19 11:14   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 04/60] target/arm: Update SCTLR bits to ARMv9.2 Richard Henderson
2022-04-19 11:16   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool Richard Henderson
2022-04-19 11:16   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 " Richard Henderson
2022-04-19 11:17   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 07/60] target/arm: Extend store_cpu_offset to take field size Richard Henderson
2022-04-21 16:15   ` Peter Maydell
2022-04-22 13:58   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 08/60] target/arm: Change DisasContext.thumb to bool Richard Henderson
2022-04-21 16:15   ` Peter Maydell
2022-04-22 13:59   ` Alex Bennée
2022-04-22 14:04     ` Peter Maydell
2022-04-22 15:24       ` Richard Henderson
2022-04-17 17:43 ` [PATCH v3 09/60] target/arm: Change CPUArchState.thumb " Richard Henderson
2022-04-21 16:18   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 10/60] target/arm: Remove fpexc32_access Richard Henderson
2022-04-21 16:25   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 11/60] target/arm: Split out set_btype_raw Richard Henderson
2022-04-21 16:27   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 12/60] target/arm: Split out gen_rebuild_hflags Richard Henderson
2022-04-21 18:47   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 13/60] target/arm: Use tcg_constant in translate-a64.c Richard Henderson
2022-04-21 18:49   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 14/60] target/arm: Simplify GEN_SHIFT in translate.c Richard Henderson
2022-04-21 18:56   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 15/60] target/arm: Simplify gen_sar Richard Henderson
2022-04-21 18:57   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 16/60] target/arm: Simplify aa32 DISAS_WFI Richard Henderson
2022-04-21 19:00   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 17/60] target/arm: Use tcg_constant in translate.c Richard Henderson
2022-04-21 19:00   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 18/60] target/arm: Use tcg_constant in translate-m-nocp.c Richard Henderson
2022-04-21 19:03   ` Peter Maydell
2022-04-21 21:37     ` Richard Henderson
2022-04-17 17:43 ` [PATCH v3 19/60] target/arm: Use tcg_constant in translate-neon.c Richard Henderson
2022-04-21 19:06   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 20/60] target/arm: Use smin/smax for do_sat_addsub_32 Richard Henderson
2022-04-21 19:07   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 21/60] target/arm: Use tcg_constant in translate-sve.c Richard Henderson
2022-04-21 19:08   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 22/60] target/arm: Use tcg_constant in translate-vfp.c Richard Henderson
2022-04-21 19:10   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 23/60] target/arm: Use tcg_constant_i32 in translate.h Richard Henderson
2022-04-21 19:11   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 24/60] target/arm: Split out cpregs.h Richard Henderson
2022-04-21 19:14   ` Peter Maydell
2022-04-22 15:21   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 25/60] target/arm: Reorg CPAccessResult and access_check_cp_reg Richard Henderson
2022-04-22  9:32   ` Peter Maydell
2022-04-22 15:31   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 26/60] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Richard Henderson
2022-04-22  9:37   ` Peter Maydell
2022-04-22 10:39     ` Richard Henderson
2022-04-22 15:36       ` Alex Bennée
2022-05-01  0:10         ` Richard Henderson
2022-04-17 17:43 ` Richard Henderson [this message]
2022-04-22  9:38   ` [PATCH v3 27/60] target/arm: Make some more cpreg data static const Peter Maydell
2022-04-22 15:38   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 28/60] target/arm: Reorg ARMCPRegInfo type field bits Richard Henderson
2022-04-22  9:49   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 29/60] target/arm: Change cpreg access permissions to enum Richard Henderson
2022-04-22  9:52   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 30/60] target/arm: Name CPState type Richard Henderson
2022-04-22  9:53   ` Peter Maydell
2022-04-22 15:51   ` Alex Bennée
2022-04-17 17:43 ` [PATCH v3 31/60] target/arm: Name CPSecureState type Richard Henderson
2022-04-22  9:57   ` Peter Maydell
2022-04-17 17:43 ` [PATCH v3 32/60] target/arm: Update sysreg fields when redirecting for E2H Richard Henderson
2022-04-22 10:39   ` Peter Maydell
2022-05-01  1:03     ` Richard Henderson
2022-04-17 17:43 ` [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly Richard Henderson
2022-04-22 10:46   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 34/60] target/arm: Cleanup add_cpreg_to_hashtable Richard Henderson
2022-04-22 10:48   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 35/60] target/arm: Handle cpreg registration for missing EL Richard Henderson
2022-04-22 10:57   ` Peter Maydell
2022-04-26  9:40     ` Peter Maydell
2022-04-26 15:31     ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 36/60] target/arm: Drop EL3 no EL2 fallbacks Richard Henderson
2022-04-17 17:44 ` [PATCH v3 37/60] target/arm: Merge zcr reginfo Richard Henderson
2022-04-17 17:44 ` [PATCH v3 38/60] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-04-17 17:44 ` [PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-04-17 17:44 ` [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-04-22 11:01   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-04-22 11:02   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 42/60] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-04-17 17:44 ` [PATCH v3 43/60] target/arm: Split out aa32_max_features Richard Henderson
2022-04-22 11:03   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 44/60] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-04-17 17:44 ` [PATCH v3 45/60] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-04-17 17:44 ` [PATCH v3 46/60] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-04-17 17:44 ` [PATCH v3 47/60] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-04-17 17:44 ` [PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-04-17 17:44 ` [PATCH v3 49/60] target/arm: Add minimal RAS registers Richard Henderson
2022-04-17 17:44 ` [PATCH v3 50/60] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-04-17 17:44 ` [PATCH v3 51/60] target/arm: Implement virtual SError exceptions Richard Henderson
2022-04-22 11:06   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 52/60] target/arm: Implement ESB instruction Richard Henderson
2022-04-17 17:44 ` [PATCH v3 53/60] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-04-17 17:44 ` [PATCH v3 54/60] target/arm: Enable FEAT_IESB " Richard Henderson
2022-04-17 17:44 ` [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-04-17 17:44 ` [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 " Richard Henderson
2022-04-29  9:52   ` Damien Hedde
2022-04-29 18:06     ` Richard Henderson
2022-04-17 17:44 ` [PATCH v3 57/60] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-04-17 17:44 ` [PATCH v3 58/60] target/arm: Enable FEAT_DGH " Richard Henderson
2022-04-17 17:44 ` [PATCH v3 59/60] target/arm: Define cortex-a76 Richard Henderson
2022-04-22 11:08   ` Peter Maydell
2022-04-17 17:44 ` [PATCH v3 60/60] target/arm: Define neoverse-n1 Richard Henderson
2022-04-22 11:08   ` Peter Maydell
2022-04-22  9:01 ` [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus Peter Maydell

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