* [PATCH 0/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take audio-related nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add another PATCH for updating clocks and clock-names in the bindings.
Allen-KH Cheng (1):
arm64: dts: mt8192: Add audio-related nodes
Jiaxin Yu (1):
ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 +++++++++++++-
2 files changed, 286 insertions(+), 14 deletions(-)
--
2.18.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take audio-related nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add another PATCH for updating clocks and clock-names in the bindings.
Allen-KH Cheng (1):
arm64: dts: mt8192: Add audio-related nodes
Jiaxin Yu (1):
ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 +++++++++++++-
2 files changed, 286 insertions(+), 14 deletions(-)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take audio-related nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add another PATCH for updating clocks and clock-names in the bindings.
Allen-KH Cheng (1):
arm64: dts: mt8192: Add audio-related nodes
Jiaxin Yu (1):
ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 +++++++++++++-
2 files changed, 286 insertions(+), 14 deletions(-)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
2022-04-19 2:55 ` Allen-KH Cheng
(?)
@ 2022-04-19 2:55 ` Allen-KH Cheng
-1 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu, Allen-KH Cheng
From: Jiaxin Yu <jiaxin.yu@mediatek.com>
Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
1 file changed, 157 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
index 7a25bc9b8060..1b6b22a5732e 100644
--- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
+++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
@@ -39,20 +39,67 @@ properties:
maxItems: 1
clocks:
- items:
- - description: AFE clock
- - description: ADDA DAC clock
- - description: ADDA DAC pre-distortion clock
- - description: audio infra sys clock
- - description: audio infra 26M clock
+ minItems: 56
+ maxItems: 56
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adda6_adc_clk
+ - const: aud_apll22m_clk
+ - const: aud_apll24m_clk
+ - const: aud_apll1_tuner_clk
+ - const: aud_apll2_tuner_clk
+ - const: aud_tdm_clk
+ - const: aud_tml_clk
+ - const: aud_nle
+ - const: aud_dac_hires_clk
+ - const: aud_adc_hires_clk
+ - const: aud_adc_hires_tml
+ - const: aud_adda6_adc_hires_clk
+ - const: aud_3rd_dac_clk
+ - const: aud_3rd_dac_predis_clk
+ - const: aud_3rd_dac_tml
+ - const: aud_3rd_dac_hires_clk
- const: aud_infra_clk
- const: aud_infra_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_audio_int
+ - const: top_mainpll_d4_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d4
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d4
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s3_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_i2s5_m_sel
+ - const: top_i2s6_m_sel
+ - const: top_i2s7_m_sel
+ - const: top_i2s8_m_sel
+ - const: top_i2s9_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div3
+ - const: top_apll12_div4
+ - const: top_apll12_divb
+ - const: top_apll12_div5
+ - const: top_apll12_div6
+ - const: top_apll12_div7
+ - const: top_apll12_div8
+ - const: top_apll12_div9
+ - const: top_mux_audio_h
+ - const: top_clk26m_clk
required:
- compatible
@@ -88,13 +135,115 @@ examples:
clocks = <&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
<&infracfg CLK_INFRA_AUDIO>,
- <&infracfg CLK_INFRA_AUDIO_26M_B>;
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
"aud_infra_clk",
- "aud_infra_26m_clk";
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
};
...
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu, Allen-KH Cheng
From: Jiaxin Yu <jiaxin.yu@mediatek.com>
Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
1 file changed, 157 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
index 7a25bc9b8060..1b6b22a5732e 100644
--- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
+++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
@@ -39,20 +39,67 @@ properties:
maxItems: 1
clocks:
- items:
- - description: AFE clock
- - description: ADDA DAC clock
- - description: ADDA DAC pre-distortion clock
- - description: audio infra sys clock
- - description: audio infra 26M clock
+ minItems: 56
+ maxItems: 56
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adda6_adc_clk
+ - const: aud_apll22m_clk
+ - const: aud_apll24m_clk
+ - const: aud_apll1_tuner_clk
+ - const: aud_apll2_tuner_clk
+ - const: aud_tdm_clk
+ - const: aud_tml_clk
+ - const: aud_nle
+ - const: aud_dac_hires_clk
+ - const: aud_adc_hires_clk
+ - const: aud_adc_hires_tml
+ - const: aud_adda6_adc_hires_clk
+ - const: aud_3rd_dac_clk
+ - const: aud_3rd_dac_predis_clk
+ - const: aud_3rd_dac_tml
+ - const: aud_3rd_dac_hires_clk
- const: aud_infra_clk
- const: aud_infra_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_audio_int
+ - const: top_mainpll_d4_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d4
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d4
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s3_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_i2s5_m_sel
+ - const: top_i2s6_m_sel
+ - const: top_i2s7_m_sel
+ - const: top_i2s8_m_sel
+ - const: top_i2s9_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div3
+ - const: top_apll12_div4
+ - const: top_apll12_divb
+ - const: top_apll12_div5
+ - const: top_apll12_div6
+ - const: top_apll12_div7
+ - const: top_apll12_div8
+ - const: top_apll12_div9
+ - const: top_mux_audio_h
+ - const: top_clk26m_clk
required:
- compatible
@@ -88,13 +135,115 @@ examples:
clocks = <&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
<&infracfg CLK_INFRA_AUDIO>,
- <&infracfg CLK_INFRA_AUDIO_26M_B>;
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
"aud_infra_clk",
- "aud_infra_26m_clk";
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
};
...
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu, Allen-KH Cheng
From: Jiaxin Yu <jiaxin.yu@mediatek.com>
Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
.../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
1 file changed, 157 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
index 7a25bc9b8060..1b6b22a5732e 100644
--- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
+++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
@@ -39,20 +39,67 @@ properties:
maxItems: 1
clocks:
- items:
- - description: AFE clock
- - description: ADDA DAC clock
- - description: ADDA DAC pre-distortion clock
- - description: audio infra sys clock
- - description: audio infra 26M clock
+ minItems: 56
+ maxItems: 56
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
+ - const: aud_adc_clk
+ - const: aud_adda6_adc_clk
+ - const: aud_apll22m_clk
+ - const: aud_apll24m_clk
+ - const: aud_apll1_tuner_clk
+ - const: aud_apll2_tuner_clk
+ - const: aud_tdm_clk
+ - const: aud_tml_clk
+ - const: aud_nle
+ - const: aud_dac_hires_clk
+ - const: aud_adc_hires_clk
+ - const: aud_adc_hires_tml
+ - const: aud_adda6_adc_hires_clk
+ - const: aud_3rd_dac_clk
+ - const: aud_3rd_dac_predis_clk
+ - const: aud_3rd_dac_tml
+ - const: aud_3rd_dac_hires_clk
- const: aud_infra_clk
- const: aud_infra_26m_clk
+ - const: top_mux_audio
+ - const: top_mux_audio_int
+ - const: top_mainpll_d4_d4
+ - const: top_mux_aud_1
+ - const: top_apll1_ck
+ - const: top_mux_aud_2
+ - const: top_apll2_ck
+ - const: top_mux_aud_eng1
+ - const: top_apll1_d4
+ - const: top_mux_aud_eng2
+ - const: top_apll2_d4
+ - const: top_i2s0_m_sel
+ - const: top_i2s1_m_sel
+ - const: top_i2s2_m_sel
+ - const: top_i2s3_m_sel
+ - const: top_i2s4_m_sel
+ - const: top_i2s5_m_sel
+ - const: top_i2s6_m_sel
+ - const: top_i2s7_m_sel
+ - const: top_i2s8_m_sel
+ - const: top_i2s9_m_sel
+ - const: top_apll12_div0
+ - const: top_apll12_div1
+ - const: top_apll12_div2
+ - const: top_apll12_div3
+ - const: top_apll12_div4
+ - const: top_apll12_divb
+ - const: top_apll12_div5
+ - const: top_apll12_div6
+ - const: top_apll12_div7
+ - const: top_apll12_div8
+ - const: top_apll12_div9
+ - const: top_mux_audio_h
+ - const: top_clk26m_clk
required:
- compatible
@@ -88,13 +135,115 @@ examples:
clocks = <&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
<&infracfg CLK_INFRA_AUDIO>,
- <&infracfg CLK_INFRA_AUDIO_26M_B>;
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
"aud_infra_clk",
- "aud_infra_26m_clk";
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
};
...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
2022-04-19 2:55 ` Allen-KH Cheng
(?)
@ 2022-04-19 2:55 ` Allen-KH Cheng
-1 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
- Move audsys node in ascending order.
- Increase the address range's length from 0x1000 to 0x2000.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a6da7b04b9d4..13c87d2a391a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -716,6 +716,135 @@
status = "disabled";
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
pcie: pcie@11230000 {
compatible = "mediatek,mt8192-pcie";
device_type = "pci";
@@ -766,12 +895,6 @@
status = "disabled";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
efuse: efuse@11c10000 {
compatible = "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
- Move audsys node in ascending order.
- Increase the address range's length from 0x1000 to 0x2000.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a6da7b04b9d4..13c87d2a391a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -716,6 +716,135 @@
status = "disabled";
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
pcie: pcie@11230000 {
compatible = "mediatek,mt8192-pcie";
device_type = "pci";
@@ -766,12 +895,6 @@
status = "disabled";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
efuse: efuse@11c10000 {
compatible = "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-19 2:55 ` Allen-KH Cheng
0 siblings, 0 replies; 18+ messages in thread
From: Allen-KH Cheng @ 2022-04-19 2:55 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add audio-related nodes in audsys for mt8192 SoC.
- Move audsys node in ascending order.
- Increase the address range's length from 0x1000 to 0x2000.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a6da7b04b9d4..13c87d2a391a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -716,6 +716,135 @@
status = "disabled";
};
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
pcie: pcie@11230000 {
compatible = "mediatek,mt8192-pcie";
device_type = "pci";
@@ -766,12 +895,6 @@
status = "disabled";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
efuse: efuse@11c10000 {
compatible = "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
2022-04-19 2:55 ` Allen-KH Cheng
(?)
@ 2022-04-22 14:14 ` Matthias Brugger
-1 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:14 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Mark Brown
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
You missed to add Mark to the list. This patch should go through his branch. I
added him now to the thread.
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Regards,
Matthias
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-22 14:14 ` Matthias Brugger
0 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:14 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Mark Brown
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
You missed to add Mark to the list. This patch should go through his branch. I
added him now to the thread.
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Regards,
Matthias
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-22 14:14 ` Matthias Brugger
0 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:14 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring, Mark Brown
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Jiaxin Yu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
You missed to add Mark to the list. This patch should go through his branch. I
added him now to the thread.
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Regards,
Matthias
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
2022-04-19 2:55 ` Allen-KH Cheng
(?)
@ 2022-04-22 14:15 ` Matthias Brugger
-1 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:15 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> - Move audsys node in ascending order.
> - Increase the address range's length from 0x1000 to 0x2000.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Applied, thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a6da7b04b9d4..13c87d2a391a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -716,6 +716,135 @@
> status = "disabled";
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> pcie: pcie@11230000 {
> compatible = "mediatek,mt8192-pcie";
> device_type = "pci";
> @@ -766,12 +895,6 @@
> status = "disabled";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> efuse: efuse@11c10000 {
> compatible = "mediatek,efuse";
> reg = <0 0x11c10000 0 0x1000>;
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-22 14:15 ` Matthias Brugger
0 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:15 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> - Move audsys node in ascending order.
> - Increase the address range's length from 0x1000 to 0x2000.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Applied, thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a6da7b04b9d4..13c87d2a391a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -716,6 +716,135 @@
> status = "disabled";
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> pcie: pcie@11230000 {
> compatible = "mediatek,mt8192-pcie";
> device_type = "pci";
> @@ -766,12 +895,6 @@
> status = "disabled";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> efuse: efuse@11c10000 {
> compatible = "mediatek,efuse";
> reg = <0 0x11c10000 0 0x1000>;
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes
@ 2022-04-22 14:15 ` Matthias Brugger
0 siblings, 0 replies; 18+ messages in thread
From: Matthias Brugger @ 2022-04-22 14:15 UTC (permalink / raw)
To: Allen-KH Cheng, Rob Herring
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On 19/04/2022 04:55, Allen-KH Cheng wrote:
> Add audio-related nodes in audsys for mt8192 SoC.
> - Move audsys node in ascending order.
> - Increase the address range's length from 0x1000 to 0x2000.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Applied, thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a6da7b04b9d4..13c87d2a391a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -716,6 +716,135 @@
> status = "disabled";
> };
>
> + audsys: syscon@11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x2000>;
> + #clock-cells = <1>;
> +
> + afe: mt8192-afe-pcm {
> + compatible = "mediatek,mt8192-audio";
> + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
> + resets = <&watchdog 17>;
> + reset-names = "audiosys";
> + mediatek,apmixedsys = <&apmixedsys>;
> + mediatek,infracfg = <&infracfg>;
> + mediatek,topckgen = <&topckgen>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
> + clocks = <&audsys CLK_AUD_AFE>,
> + <&audsys CLK_AUD_DAC>,
> + <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> + <&infracfg CLK_INFRA_AUDIO>,
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> + clock-names = "aud_afe_clk",
> + "aud_dac_clk",
> + "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> + "aud_infra_clk",
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> + };
> + };
> +
> pcie: pcie@11230000 {
> compatible = "mediatek,mt8192-pcie";
> device_type = "pci";
> @@ -766,12 +895,6 @@
> status = "disabled";
> };
>
> - audsys: clock-controller@11210000 {
> - compatible = "mediatek,mt8192-audsys", "syscon";
> - reg = <0 0x11210000 0 0x1000>;
> - #clock-cells = <1>;
> - };
> -
> efuse: efuse@11c10000 {
> compatible = "mediatek,efuse";
> reg = <0 0x11c10000 0 0x1000>;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
2022-04-19 2:55 ` Allen-KH Cheng
(?)
@ 2022-04-26 20:15 ` Rob Herring
-1 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2022-04-26 20:15 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Chen-Yu Tsai, Ryder Lee, Hui Liu, Jiaxin Yu
On Tue, Apr 19, 2022 at 10:55:56AM +0800, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Not a compatible change breaking the ABI. Please explain why if that's
intentional.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-26 20:15 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2022-04-26 20:15 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Chen-Yu Tsai, Ryder Lee, Hui Liu, Jiaxin Yu
On Tue, Apr 19, 2022 at 10:55:56AM +0800, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Not a compatible change breaking the ABI. Please explain why if that's
intentional.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names
@ 2022-04-26 20:15 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2022-04-26 20:15 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Project_Global_Chrome_Upstream_Group,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
Chen-Yu Tsai, Ryder Lee, Hui Liu, Jiaxin Yu
On Tue, Apr 19, 2022 at 10:55:56AM +0800, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu@mediatek.com>
>
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
Not a compatible change breaking the ABI. Please explain why if that's
intentional.
>
> Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> ---
> .../bindings/sound/mt8192-afe-pcm.yaml | 165 +++++++++++++++++-
> 1 file changed, 157 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
> maxItems: 1
>
> clocks:
> - items:
> - - description: AFE clock
> - - description: ADDA DAC clock
> - - description: ADDA DAC pre-distortion clock
> - - description: audio infra sys clock
> - - description: audio infra 26M clock
> + minItems: 56
> + maxItems: 56
>
> clock-names:
> items:
> - const: aud_afe_clk
> - const: aud_dac_clk
> - const: aud_dac_predis_clk
> + - const: aud_adc_clk
> + - const: aud_adda6_adc_clk
> + - const: aud_apll22m_clk
> + - const: aud_apll24m_clk
> + - const: aud_apll1_tuner_clk
> + - const: aud_apll2_tuner_clk
> + - const: aud_tdm_clk
> + - const: aud_tml_clk
> + - const: aud_nle
> + - const: aud_dac_hires_clk
> + - const: aud_adc_hires_clk
> + - const: aud_adc_hires_tml
> + - const: aud_adda6_adc_hires_clk
> + - const: aud_3rd_dac_clk
> + - const: aud_3rd_dac_predis_clk
> + - const: aud_3rd_dac_tml
> + - const: aud_3rd_dac_hires_clk
> - const: aud_infra_clk
> - const: aud_infra_26m_clk
> + - const: top_mux_audio
> + - const: top_mux_audio_int
> + - const: top_mainpll_d4_d4
> + - const: top_mux_aud_1
> + - const: top_apll1_ck
> + - const: top_mux_aud_2
> + - const: top_apll2_ck
> + - const: top_mux_aud_eng1
> + - const: top_apll1_d4
> + - const: top_mux_aud_eng2
> + - const: top_apll2_d4
> + - const: top_i2s0_m_sel
> + - const: top_i2s1_m_sel
> + - const: top_i2s2_m_sel
> + - const: top_i2s3_m_sel
> + - const: top_i2s4_m_sel
> + - const: top_i2s5_m_sel
> + - const: top_i2s6_m_sel
> + - const: top_i2s7_m_sel
> + - const: top_i2s8_m_sel
> + - const: top_i2s9_m_sel
> + - const: top_apll12_div0
> + - const: top_apll12_div1
> + - const: top_apll12_div2
> + - const: top_apll12_div3
> + - const: top_apll12_div4
> + - const: top_apll12_divb
> + - const: top_apll12_div5
> + - const: top_apll12_div6
> + - const: top_apll12_div7
> + - const: top_apll12_div8
> + - const: top_apll12_div9
> + - const: top_mux_audio_h
> + - const: top_clk26m_clk
>
> required:
> - compatible
> @@ -88,13 +135,115 @@ examples:
> clocks = <&audsys CLK_AUD_AFE>,
> <&audsys CLK_AUD_DAC>,
> <&audsys CLK_AUD_DAC_PREDIS>,
> + <&audsys CLK_AUD_ADC>,
> + <&audsys CLK_AUD_ADDA6_ADC>,
> + <&audsys CLK_AUD_22M>,
> + <&audsys CLK_AUD_24M>,
> + <&audsys CLK_AUD_APLL_TUNER>,
> + <&audsys CLK_AUD_APLL2_TUNER>,
> + <&audsys CLK_AUD_TDM>,
> + <&audsys CLK_AUD_TML>,
> + <&audsys CLK_AUD_NLE>,
> + <&audsys CLK_AUD_DAC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES>,
> + <&audsys CLK_AUD_ADC_HIRES_TML>,
> + <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> + <&audsys CLK_AUD_3RD_DAC>,
> + <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> + <&audsys CLK_AUD_3RD_DAC_TML>,
> + <&audsys CLK_AUD_3RD_DAC_HIRES>,
> <&infracfg CLK_INFRA_AUDIO>,
> - <&infracfg CLK_INFRA_AUDIO_26M_B>;
> + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> + <&topckgen CLK_TOP_AUDIO_SEL>,
> + <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> + <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> + <&topckgen CLK_TOP_AUD_1_SEL>,
> + <&topckgen CLK_TOP_APLL1>,
> + <&topckgen CLK_TOP_AUD_2_SEL>,
> + <&topckgen CLK_TOP_APLL2>,
> + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> + <&topckgen CLK_TOP_APLL1_D4>,
> + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> + <&topckgen CLK_TOP_APLL2_D4>,
> + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> + <&topckgen CLK_TOP_APLL12_DIV0>,
> + <&topckgen CLK_TOP_APLL12_DIV1>,
> + <&topckgen CLK_TOP_APLL12_DIV2>,
> + <&topckgen CLK_TOP_APLL12_DIV3>,
> + <&topckgen CLK_TOP_APLL12_DIV4>,
> + <&topckgen CLK_TOP_APLL12_DIVB>,
> + <&topckgen CLK_TOP_APLL12_DIV5>,
> + <&topckgen CLK_TOP_APLL12_DIV6>,
> + <&topckgen CLK_TOP_APLL12_DIV7>,
> + <&topckgen CLK_TOP_APLL12_DIV8>,
> + <&topckgen CLK_TOP_APLL12_DIV9>,
> + <&topckgen CLK_TOP_AUDIO_H_SEL>,
> + <&clk26m>;
> clock-names = "aud_afe_clk",
> "aud_dac_clk",
> "aud_dac_predis_clk",
> + "aud_adc_clk",
> + "aud_adda6_adc_clk",
> + "aud_apll22m_clk",
> + "aud_apll24m_clk",
> + "aud_apll1_tuner_clk",
> + "aud_apll2_tuner_clk",
> + "aud_tdm_clk",
> + "aud_tml_clk",
> + "aud_nle",
> + "aud_dac_hires_clk",
> + "aud_adc_hires_clk",
> + "aud_adc_hires_tml",
> + "aud_adda6_adc_hires_clk",
> + "aud_3rd_dac_clk",
> + "aud_3rd_dac_predis_clk",
> + "aud_3rd_dac_tml",
> + "aud_3rd_dac_hires_clk",
> "aud_infra_clk",
> - "aud_infra_26m_clk";
> + "aud_infra_26m_clk",
> + "top_mux_audio",
> + "top_mux_audio_int",
> + "top_mainpll_d4_d4",
> + "top_mux_aud_1",
> + "top_apll1_ck",
> + "top_mux_aud_2",
> + "top_apll2_ck",
> + "top_mux_aud_eng1",
> + "top_apll1_d4",
> + "top_mux_aud_eng2",
> + "top_apll2_d4",
> + "top_i2s0_m_sel",
> + "top_i2s1_m_sel",
> + "top_i2s2_m_sel",
> + "top_i2s3_m_sel",
> + "top_i2s4_m_sel",
> + "top_i2s5_m_sel",
> + "top_i2s6_m_sel",
> + "top_i2s7_m_sel",
> + "top_i2s8_m_sel",
> + "top_i2s9_m_sel",
> + "top_apll12_div0",
> + "top_apll12_div1",
> + "top_apll12_div2",
> + "top_apll12_div3",
> + "top_apll12_div4",
> + "top_apll12_divb",
> + "top_apll12_div5",
> + "top_apll12_div6",
> + "top_apll12_div7",
> + "top_apll12_div8",
> + "top_apll12_div9",
> + "top_mux_audio_h",
> + "top_clk26m_clk";
> };
>
> ...
> --
> 2.18.0
>
>
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^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-04-26 20:16 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-19 2:55 [PATCH 0/2] arm64: dts: mt8192: Add audio-related nodes Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-19 2:55 ` [PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-22 14:14 ` Matthias Brugger
2022-04-22 14:14 ` Matthias Brugger
2022-04-22 14:14 ` Matthias Brugger
2022-04-26 20:15 ` Rob Herring
2022-04-26 20:15 ` Rob Herring
2022-04-26 20:15 ` Rob Herring
2022-04-19 2:55 ` [PATCH 2/2] arm64: dts: mt8192: Add audio-related nodes Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-19 2:55 ` Allen-KH Cheng
2022-04-22 14:15 ` Matthias Brugger
2022-04-22 14:15 ` Matthias Brugger
2022-04-22 14:15 ` Matthias Brugger
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