[PATCH v7 0/2] check feature type for DFL irq parsing

[PATCH v7 0/2] check feature type for DFL irq parsing

[Tianfei Zhang]

This patch set adds an extended usage of Feature ID for DFL 
and based on 5.18-rc2. Previously the feature IDs defined are
unique, no matter which feature type. But currently we want
to extend its usage to have a per-type feature ID space.

Patch 1 adds feature type checking before parse the irq info.
Patch 2 adds link address about the Feature ID table.

v7:
  - Add reviewed-by from Matthew Gerlach and Acked-by from Hao. 
  - Change title and git commit message for patch 2. 
v6:
  - Fix documentation from Hao's comment. 
v5:
  - Fix documentation from Matthew's comment. 
v4:
  - Fix the git commit from Hao's comments.
  - Split documentation into another patch.
v3:
  - Remove "Fixes" in commit log with Hao's comment, this is a
    extension not a bug fix.
v2:
  - add DFL Feature ID Registry in documentation.

Tianfei zhang (2):
  fpga: dfl: check feature type before parse irq info
  Documentation: fpga: dfl: add link address of feature id table

 Documentation/fpga/dfl.rst |  5 +++++
 drivers/fpga/dfl.c         | 38 ++++++++++++++++++++++----------------
 2 files changed, 27 insertions(+), 16 deletions(-)

-- 
2.26.2

[PATCH v7 1/2] fpga: dfl: check feature type before parse irq info

[Tianfei Zhang]

From: Tianfei zhang <tianfei.zhang@intel.com>

Previously the feature IDs defined are unique, no matter
which feature type. But currently we want to extend its
usage to have a per-type feature ID space, so this patch
adds feature type checking as well just before look into
feature ID for different features which have irq info.

Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Wu Hao <hao.wu@intel.com>
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
---
v7:
  - Add Reviewed-by and Acked-by tag.
v4:
  - Fix the git commit from Hao's comments.
  - Split documentation into another patch.
v3:
  - Remove "Fixes" in commit log with Hao's comment, this is a
    extension not a bug fix.
v2:
  - add DFL Feature ID Registry in documentation.
---
 drivers/fpga/dfl.c | 38 ++++++++++++++++++++++----------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 599bb21d86af..6bff39ff21a0 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 {
 	void __iomem *base = binfo->ioaddr + ofst;
 	unsigned int i, ibase, inr = 0;
+	enum dfl_id_type type;
 	int virq;
 	u64 v;
 
+	type = feature_dev_id_type(binfo->feature_dev);
+
 	/*
 	 * Ideally DFL framework should only read info from DFL header, but
 	 * current version DFL only provides mmio resources information for
@@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 	 * code will be added. But in order to be compatible to old version
 	 * DFL, the driver may still fall back to these quirks.
 	 */
-	switch (fid) {
-	case PORT_FEATURE_ID_UINT:
-		v = readq(base + PORT_UINT_CAP);
-		ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
-		inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
-		break;
-	case PORT_FEATURE_ID_ERROR:
-		v = readq(base + PORT_ERROR_CAP);
-		ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
-		inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
-		break;
-	case FME_FEATURE_ID_GLOBAL_ERR:
-		v = readq(base + FME_ERROR_CAP);
-		ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
-		inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
-		break;
+	if (type == PORT_ID) {
+		switch (fid) {
+		case PORT_FEATURE_ID_UINT:
+			v = readq(base + PORT_UINT_CAP);
+			ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
+			inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
+			break;
+		case PORT_FEATURE_ID_ERROR:
+			v = readq(base + PORT_ERROR_CAP);
+			ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
+			inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
+			break;
+		}
+	} else if (type == FME_ID) {
+		if (fid == FME_FEATURE_ID_GLOBAL_ERR) {
+			v = readq(base + FME_ERROR_CAP);
+			ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
+			inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
+		}
 	}
 
 	if (!inr) {
-- 
2.26.2

[PATCH v7 2/2] Documentation: fpga: dfl: add link address of feature id table

[Tianfei Zhang]

From: Tianfei zhang <tianfei.zhang@intel.com>

This patch adds the link address of feature id table in documentation.

Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
---
v7:
  - change the title and git commit message.
  - add Reviewed by from Matthew Gerlach.
v6: fix documentation from Hao's comment.
v5: fix documentation from Matthew's comment.
---
 Documentation/fpga/dfl.rst | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index ef9eec71f6f3..15b670926084 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
 FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
 could be a reference.
 
+Please refer to below link to existing feature id table and guide for new feature
+ids application.
+https://github.com/OPAE/dfl-feature-id
+
+
 Location of DFLs on a PCI Device
 ================================
 The original method for finding a DFL on a PCI device assumed the start of the
-- 
2.26.2

Re: [PATCH v7 1/2] fpga: dfl: check feature type before parse irq info

[Moritz Fischer]

On Mon, Apr 18, 2022 at 11:29:41PM -0400, Tianfei Zhang wrote:
> From: Tianfei zhang <tianfei.zhang@intel.com>
> 
> Previously the feature IDs defined are unique, no matter
> which feature type. But currently we want to extend its
> usage to have a per-type feature ID space, so this patch
> adds feature type checking as well just before look into
> feature ID for different features which have irq info.
> 
> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Acked-by: Wu Hao <hao.wu@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> ---
> v7:
>   - Add Reviewed-by and Acked-by tag.
> v4:
>   - Fix the git commit from Hao's comments.
>   - Split documentation into another patch.
> v3:
>   - Remove "Fixes" in commit log with Hao's comment, this is a
>     extension not a bug fix.
> v2:
>   - add DFL Feature ID Registry in documentation.
> ---
>  drivers/fpga/dfl.c | 38 ++++++++++++++++++++++----------------
>  1 file changed, 22 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index 599bb21d86af..6bff39ff21a0 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
>  {
>  	void __iomem *base = binfo->ioaddr + ofst;
>  	unsigned int i, ibase, inr = 0;
> +	enum dfl_id_type type;
>  	int virq;
>  	u64 v;
>  
> +	type = feature_dev_id_type(binfo->feature_dev);
> +
>  	/*
>  	 * Ideally DFL framework should only read info from DFL header, but
>  	 * current version DFL only provides mmio resources information for
> @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
>  	 * code will be added. But in order to be compatible to old version
>  	 * DFL, the driver may still fall back to these quirks.
>  	 */
> -	switch (fid) {
> -	case PORT_FEATURE_ID_UINT:
> -		v = readq(base + PORT_UINT_CAP);
> -		ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> -		inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> -		break;
> -	case PORT_FEATURE_ID_ERROR:
> -		v = readq(base + PORT_ERROR_CAP);
> -		ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> -		inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> -		break;
> -	case FME_FEATURE_ID_GLOBAL_ERR:
> -		v = readq(base + FME_ERROR_CAP);
> -		ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> -		inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> -		break;
> +	if (type == PORT_ID) {
> +		switch (fid) {
> +		case PORT_FEATURE_ID_UINT:
> +			v = readq(base + PORT_UINT_CAP);
> +			ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> +			inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> +			break;
> +		case PORT_FEATURE_ID_ERROR:
> +			v = readq(base + PORT_ERROR_CAP);
> +			ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> +			inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> +			break;
> +		}
> +	} else if (type == FME_ID) {
> +		if (fid == FME_FEATURE_ID_GLOBAL_ERR) {
> +			v = readq(base + FME_ERROR_CAP);
> +			ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> +			inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> +		}
>  	}
>  
>  	if (!inr) {
> -- 
> 2.26.2
> 

Re: [PATCH v7 2/2] Documentation: fpga: dfl: add link address of feature id table

[Moritz Fischer]

On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> From: Tianfei zhang <tianfei.zhang@intel.com>
> 
> This patch adds the link address of feature id table in documentation.
> 
> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v7:
>   - change the title and git commit message.
>   - add Reviewed by from Matthew Gerlach.
> v6: fix documentation from Hao's comment.
> v5: fix documentation from Matthew's comment.
> ---
>  Documentation/fpga/dfl.rst | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> index ef9eec71f6f3..15b670926084 100644
> --- a/Documentation/fpga/dfl.rst
> +++ b/Documentation/fpga/dfl.rst
> @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
>  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
>  could be a reference.
>  
> +Please refer to below link to existing feature id table and guide for new feature
> +ids application.
> +https://github.com/OPAE/dfl-feature-id
> +
> +
>  Location of DFLs on a PCI Device
>  ================================
>  The original method for finding a DFL on a PCI device assumed the start of the
> -- 
> 2.26.2
> 

Re: [PATCH v7 2/2] Documentation: fpga: dfl: add link address of feature id table

[Xu Yilun]

On Thu, Apr 21, 2022 at 07:47:18AM -0700, Moritz Fischer wrote:
> On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> > From: Tianfei zhang <tianfei.zhang@intel.com>
> > 
> > This patch adds the link address of feature id table in documentation.
> > 
> > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> Acked-by: Moritz Fischer <mdf@kernel.org>

Acked-by: Xu Yilun <yilun.xu@intel.com>

> > ---
> > v7:
> >   - change the title and git commit message.
> >   - add Reviewed by from Matthew Gerlach.
> > v6: fix documentation from Hao's comment.
> > v5: fix documentation from Matthew's comment.
> > ---
> >  Documentation/fpga/dfl.rst | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> > index ef9eec71f6f3..15b670926084 100644
> > --- a/Documentation/fpga/dfl.rst
> > +++ b/Documentation/fpga/dfl.rst
> > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id.
> >  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
> >  could be a reference.
> >  
> > +Please refer to below link to existing feature id table and guide for new feature
> > +ids application.
> > +https://github.com/OPAE/dfl-feature-id
> > +
> > +
> >  Location of DFLs on a PCI Device
> >  ================================
> >  The original method for finding a DFL on a PCI device assumed the start of the
> > -- 
> > 2.26.2
> > 

Re: [PATCH v7 1/2] fpga: dfl: check feature type before parse irq info

[Xu Yilun]

On Thu, Apr 21, 2022 at 07:46:21AM -0700, Moritz Fischer wrote:
> On Mon, Apr 18, 2022 at 11:29:41PM -0400, Tianfei Zhang wrote:
> > From: Tianfei zhang <tianfei.zhang@intel.com>
> > 
> > Previously the feature IDs defined are unique, no matter
> > which feature type. But currently we want to extend its
> > usage to have a per-type feature ID space, so this patch
> > adds feature type checking as well just before look into
> > feature ID for different features which have irq info.
> > 
> > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > Acked-by: Wu Hao <hao.wu@intel.com>
> Acked-by: Moritz Fischer <mdf@kernel.org>

Acked-by: Xu Yilun <yilun.xu@intel.com>

> > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> > ---
> > v7:
> >   - Add Reviewed-by and Acked-by tag.
> > v4:
> >   - Fix the git commit from Hao's comments.
> >   - Split documentation into another patch.
> > v3:
> >   - Remove "Fixes" in commit log with Hao's comment, this is a
> >     extension not a bug fix.
> > v2:
> >   - add DFL Feature ID Registry in documentation.
> > ---
> >  drivers/fpga/dfl.c | 38 ++++++++++++++++++++++----------------
> >  1 file changed, 22 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> > index 599bb21d86af..6bff39ff21a0 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
> >  {
> >  	void __iomem *base = binfo->ioaddr + ofst;
> >  	unsigned int i, ibase, inr = 0;
> > +	enum dfl_id_type type;
> >  	int virq;
> >  	u64 v;
> >  
> > +	type = feature_dev_id_type(binfo->feature_dev);
> > +
> >  	/*
> >  	 * Ideally DFL framework should only read info from DFL header, but
> >  	 * current version DFL only provides mmio resources information for
> > @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
> >  	 * code will be added. But in order to be compatible to old version
> >  	 * DFL, the driver may still fall back to these quirks.
> >  	 */
> > -	switch (fid) {
> > -	case PORT_FEATURE_ID_UINT:
> > -		v = readq(base + PORT_UINT_CAP);
> > -		ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> > -		inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> > -		break;
> > -	case PORT_FEATURE_ID_ERROR:
> > -		v = readq(base + PORT_ERROR_CAP);
> > -		ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> > -		inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> > -		break;
> > -	case FME_FEATURE_ID_GLOBAL_ERR:
> > -		v = readq(base + FME_ERROR_CAP);
> > -		ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> > -		inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> > -		break;
> > +	if (type == PORT_ID) {
> > +		switch (fid) {
> > +		case PORT_FEATURE_ID_UINT:
> > +			v = readq(base + PORT_UINT_CAP);
> > +			ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
> > +			inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
> > +			break;
> > +		case PORT_FEATURE_ID_ERROR:
> > +			v = readq(base + PORT_ERROR_CAP);
> > +			ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
> > +			inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
> > +			break;
> > +		}
> > +	} else if (type == FME_ID) {
> > +		if (fid == FME_FEATURE_ID_GLOBAL_ERR) {
> > +			v = readq(base + FME_ERROR_CAP);
> > +			ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
> > +			inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
> > +		}
> >  	}
> >  
> >  	if (!inr) {
> > -- 
> > 2.26.2
> > 

RE: [PATCH v7 2/2] Documentation: fpga: dfl: add link address of feature id table

[Wu, Hao]

> -----Original Message-----
> From: Xu, Yilun <yilun.xu@intel.com>
> Sent: Monday, April 25, 2022 3:23 PM
> To: Moritz Fischer <mdf@kernel.org>
> Cc: Zhang, Tianfei <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com>;
> trix@redhat.com; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.org;
> corbet@lwn.net; Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Subject: Re: [PATCH v7 2/2] Documentation: fpga: dfl: add link address of
> feature id table
> 
> On Thu, Apr 21, 2022 at 07:47:18AM -0700, Moritz Fischer wrote:
> > On Mon, Apr 18, 2022 at 11:29:42PM -0400, Tianfei Zhang wrote:
> > > From: Tianfei zhang <tianfei.zhang@intel.com>
> > >
> > > This patch adds the link address of feature id table in documentation.
> > >
> > > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com>
> > Acked-by: Moritz Fischer <mdf@kernel.org>
> 
> Acked-by: Xu Yilun <yilun.xu@intel.com>
> 

Acked-by: Wu Hao <hao.wu@intel.com>

> > > ---
> > > v7:
> > >   - change the title and git commit message.
> > >   - add Reviewed by from Matthew Gerlach.
> > > v6: fix documentation from Hao's comment.
> > > v5: fix documentation from Matthew's comment.
> > > ---
> > >  Documentation/fpga/dfl.rst | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
> > > index ef9eec71f6f3..15b670926084 100644
> > > --- a/Documentation/fpga/dfl.rst
> > > +++ b/Documentation/fpga/dfl.rst
> > > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature
> driver with matched feature id.
> > >  FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-
> pr.c)
> > >  could be a reference.
> > >
> > > +Please refer to below link to existing feature id table and guide for new
> feature
> > > +ids application.
> > > +https://github.com/OPAE/dfl-feature-id
> > > +
> > > +
> > >  Location of DFLs on a PCI Device
> > >  ================================
> > >  The original method for finding a DFL on a PCI device assumed the start of
> the
> > > --
> > > 2.26.2
> > >