From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5053EC433EF for ; Tue, 19 Apr 2022 07:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349167AbiDSHGu (ORCPT ); Tue, 19 Apr 2022 03:06:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237092AbiDSHGq (ORCPT ); Tue, 19 Apr 2022 03:06:46 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E29E62AC6C; Tue, 19 Apr 2022 00:04:04 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73fM2025664; Tue, 19 Apr 2022 02:03:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351821; bh=GE9Plw/ZKj9bf211DOprV0mgq6L7hEDBT4cWIq5E0yo=; h=From:To:CC:Subject:Date; b=InXJW5fgW56RZTOTSJOaNefKs8N4t9eaDYTxjKpyQDRbZDmUJY+5qFprIY8HGzJy2 a9SI59m3xiw4ImJBwTMXF77AR9088y+WS+aGceTSJPcN8zb1NYanEMZE8La3s1hY41 XJIU5CRPOxgHvELgIssaOuh50ThCEXbIXxcuFLHg= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73fcX120926 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:41 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73euZ005625; Tue, 19 Apr 2022 02:03:40 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 0/2] Update register & interrupt info in am65x DSS Date: Tue, 19 Apr 2022 12:33:00 +0530 Message-ID: <20220419070302.16502-1-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Display SubSystem IP on the ti's am65x soc has an additional register space "common1" and services a maximum of 2 interrupts. The first patch in the series adds the required updates to the yaml file. The second patch then reflects the yaml updates in the DSS DT node of am65x soc. Aradhya Bhatia (2): dt-bindings: display: ti,am65x-dss: Add missing register & interrupt arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.35.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81F3EC433EF for ; Tue, 19 Apr 2022 07:31:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=qYWbrOdzRQA6GTbjH/Em6HZSxDRTKSYpKk+n1+xul+c=; b=VJODEXkndmUZ1S wWHjD3f0jygyMWi/Bl48tU1/ZpqrNVfsHehCBAt3z6aJvT9bXI3fI2u2LbClOpGeDUksdMU3dy7dZ ohX1RuUkwczxwxkj9b2T3rf2YA+GveDGr2b8aCQSDMJ+bxqPMEIY0ghY9dXCYWMtjkOPQjylaBTAJ RFdrDWeSH2K7TQ7//iUTTJ91m5bR1likN+F+WxfmMABTHqJAVXdAYLF0svLSxq3rauvTHkFwYcKva jcGGoKiLJqai096wiuGnWm+SIvZ2Pr7EliBVtUm/PDko3TYUkFa6qaTij3OegWGHU3mGrRKITU+Gd BwgDKn57pRM7MisZwu1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngiJr-0020Sa-K2; Tue, 19 Apr 2022 07:30:40 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nghu6-001q83-QH for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 07:04:04 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73fM2025664; Tue, 19 Apr 2022 02:03:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351821; bh=GE9Plw/ZKj9bf211DOprV0mgq6L7hEDBT4cWIq5E0yo=; h=From:To:CC:Subject:Date; b=InXJW5fgW56RZTOTSJOaNefKs8N4t9eaDYTxjKpyQDRbZDmUJY+5qFprIY8HGzJy2 a9SI59m3xiw4ImJBwTMXF77AR9088y+WS+aGceTSJPcN8zb1NYanEMZE8La3s1hY41 XJIU5CRPOxgHvELgIssaOuh50ThCEXbIXxcuFLHg= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73fcX120926 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:41 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73euZ005625; Tue, 19 Apr 2022 02:03:40 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 0/2] Update register & interrupt info in am65x DSS Date: Tue, 19 Apr 2022 12:33:00 +0530 Message-ID: <20220419070302.16502-1-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_000402_920969_0102C8D9 X-CRM114-Status: UNSURE ( 8.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Display SubSystem IP on the ti's am65x soc has an additional register space "common1" and services a maximum of 2 interrupts. The first patch in the series adds the required updates to the yaml file. The second patch then reflects the yaml updates in the DSS DT node of am65x soc. Aradhya Bhatia (2): dt-bindings: display: ti,am65x-dss: Add missing register & interrupt arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.35.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB9EDC433FE for ; Tue, 19 Apr 2022 07:49:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F079210E2D3; Tue, 19 Apr 2022 07:49:01 +0000 (UTC) X-Greylist: delayed 2704 seconds by postgrey-1.36 at gabe; Tue, 19 Apr 2022 07:49:00 UTC Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B8C310E2D3 for ; Tue, 19 Apr 2022 07:49:00 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73fM2025664; Tue, 19 Apr 2022 02:03:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351821; bh=GE9Plw/ZKj9bf211DOprV0mgq6L7hEDBT4cWIq5E0yo=; h=From:To:CC:Subject:Date; b=InXJW5fgW56RZTOTSJOaNefKs8N4t9eaDYTxjKpyQDRbZDmUJY+5qFprIY8HGzJy2 a9SI59m3xiw4ImJBwTMXF77AR9088y+WS+aGceTSJPcN8zb1NYanEMZE8La3s1hY41 XJIU5CRPOxgHvELgIssaOuh50ThCEXbIXxcuFLHg= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73fcX120926 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:41 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:40 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73euZ005625; Tue, 19 Apr 2022 02:03:40 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon Subject: [PATCH 0/2] Update register & interrupt info in am65x DSS Date: Tue, 19 Apr 2022 12:33:00 +0530 Message-ID: <20220419070302.16502-1-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Devicetree , Aradhya Bhatia , Linux Kernel , DRI Development , Nikhil Devshatwar , Linux ARM Kernel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The Display SubSystem IP on the ti's am65x soc has an additional register space "common1" and services a maximum of 2 interrupts. The first patch in the series adds the required updates to the yaml file. The second patch then reflects the yaml updates in the DSS DT node of am65x soc. Aradhya Bhatia (2): dt-bindings: display: ti,am65x-dss: Add missing register & interrupt arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 2 files changed, 11 insertions(+), 5 deletions(-) -- 2.35.3