From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74652C433EF for ; Tue, 19 Apr 2022 07:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349177AbiDSHGy (ORCPT ); Tue, 19 Apr 2022 03:06:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239397AbiDSHGq (ORCPT ); Tue, 19 Apr 2022 03:06:46 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08E582AE00; Tue, 19 Apr 2022 00:04:04 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73ich090970; Tue, 19 Apr 2022 02:03:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351824; bh=rQb5x+seCA/gRyaHh8ycHp7w1ZagLiW2Ocbe4cn0WE8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FNu3cIpmQP2T3j6CKBtdoi23GtPDA+QFvlWI5fDl7zWaCEITM4XZG4r/kERHKh21h aEB3jwf9YRd5GVnGck4eOgO8sNYk/IVp/Lasx3m+dk5iDOq2ZvstCciXTs+Wo0nfqa 8Ja3MWfPnb5xEejkmUJqcZ8OfNDhg4wLBUJsTWgs= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73iUC031438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:44 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:43 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:43 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73hAJ105340; Tue, 19 Apr 2022 02:03:43 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Date: Tue, 19 Apr 2022 12:33:02 +0530 Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com> References: <20220419070302.16502-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The DSS IP on the ti-am65x soc supports an additional register space named "common1". Further, it services a maximum of 2 interrupts. Add the missing register space "common1" and the additional interrupt in the dss DT node . Signed-off-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e749343acced..1bafa3a98e71 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -830,13 +830,14 @@ csi2_0: port@0 { dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a01000 0x0 0x1000>, /* common1 */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ <0x0 0x04a06000 0x0 0x1000>, /* vid */ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ - reg-names = "common", "vidl1", "vid", + reg-names = "common", "common1", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -856,7 +857,8 @@ dss: dss@4a00000 { assigned-clocks = <&k3_clks 67 2>; assigned-clock-parents = <&k3_clks 67 5>; - interrupts = ; + interrupts = , + ; dma-coherent; -- 2.35.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDA10C433EF for ; Tue, 19 Apr 2022 07:11:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39DD710EECE; Tue, 19 Apr 2022 07:11:40 +0000 (UTC) X-Greylist: delayed 463 seconds by postgrey-1.36 at gabe; Tue, 19 Apr 2022 07:11:38 UTC Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by gabe.freedesktop.org (Postfix) with ESMTPS id F017A10EECE for ; Tue, 19 Apr 2022 07:11:38 +0000 (UTC) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 23J73ich090970; Tue, 19 Apr 2022 02:03:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1650351824; bh=rQb5x+seCA/gRyaHh8ycHp7w1ZagLiW2Ocbe4cn0WE8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FNu3cIpmQP2T3j6CKBtdoi23GtPDA+QFvlWI5fDl7zWaCEITM4XZG4r/kERHKh21h aEB3jwf9YRd5GVnGck4eOgO8sNYk/IVp/Lasx3m+dk5iDOq2ZvstCciXTs+Wo0nfqa 8Ja3MWfPnb5xEejkmUJqcZ8OfNDhg4wLBUJsTWgs= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 23J73iUC031438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 19 Apr 2022 02:03:44 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 19 Apr 2022 02:03:43 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 19 Apr 2022 02:03:43 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 23J73hAJ105340; Tue, 19 Apr 2022 02:03:43 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Date: Tue, 19 Apr 2022 12:33:02 +0530 Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com> References: <20220419070302.16502-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Devicetree , Aradhya Bhatia , Linux Kernel , DRI Development , Nikhil Devshatwar , Linux ARM Kernel Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The DSS IP on the ti-am65x soc supports an additional register space named "common1". Further, it services a maximum of 2 interrupts. Add the missing register space "common1" and the additional interrupt in the dss DT node . Signed-off-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e749343acced..1bafa3a98e71 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -830,13 +830,14 @@ csi2_0: port@0 { dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a01000 0x0 0x1000>, /* common1 */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ <0x0 0x04a06000 0x0 0x1000>, /* vid */ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ - reg-names = "common", "vidl1", "vid", + reg-names = "common", "common1", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -856,7 +857,8 @@ dss: dss@4a00000 { assigned-clocks = <&k3_clks 67 2>; assigned-clock-parents = <&k3_clks 67 5>; - interrupts = ; + interrupts = , + ; dma-coherent; -- 2.35.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BB77C433EF for ; Tue, 19 Apr 2022 07:32:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=F3UujL+3OrFgdFYyUpigepsgLQvizTGgPt11tRIlS2w=; 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Tue, 19 Apr 2022 02:03:43 -0500 From: Aradhya Bhatia To: Jyri Sarha , Tomi Valkeinen , Vignesh Raghavendra , Nishanth Menon CC: DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Date: Tue, 19 Apr 2022 12:33:02 +0530 Message-ID: <20220419070302.16502-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220419070302.16502-1-a-bhatia1@ti.com> References: <20220419070302.16502-1-a-bhatia1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_000402_994927_2F3ECA31 X-CRM114-Status: GOOD ( 10.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The DSS IP on the ti-am65x soc supports an additional register space named "common1". Further, it services a maximum of 2 interrupts. Add the missing register space "common1" and the additional interrupt in the dss DT node . Signed-off-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index e749343acced..1bafa3a98e71 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -830,13 +830,14 @@ csi2_0: port@0 { dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a01000 0x0 0x1000>, /* common1 */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ <0x0 0x04a06000 0x0 0x1000>, /* vid */ <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ - reg-names = "common", "vidl1", "vid", + reg-names = "common", "common1", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; @@ -856,7 +857,8 @@ dss: dss@4a00000 { assigned-clocks = <&k3_clks 67 2>; assigned-clock-parents = <&k3_clks 67 5>; - interrupts = ; + interrupts = , + ; dma-coherent; -- 2.35.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel