From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C4FAC433F5 for ; Tue, 19 Apr 2022 10:45:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=uLzcC3XLf5by4P45wZVrO6FxF6cj8PRLAMiTWUm8c64=; b=eF1cuz/gAz5ysW gDHv60SP0eWWCwEn98R6ocE3Smf0jJn1rb3d47MTiy+6lVBZJAUrSODmjyUUfqskWZcfWoclebo1F jep9KK6aGODdKeZqUrvkLnksYZXuj6rivOkjGfCF+5CgsFTR+yIEXSVG28LEk5CpAueoLEecOyC35 fqZzdph4xHjnH9uuZeXfcaAvqkvFOGapIknN18OE37dfK2A8GEhNW2yY3cIgM46XynM/NaA9CrCdc xyxR3iZJYh5jj8q/0B4hWGuHpSzJSpaZf11EYbvg9I5juI+LNRt+d+6pyxWSY44dv/k3WEjCe080C mceZhonIPeHr3X/SdvgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nglLE-002rXV-3V; Tue, 19 Apr 2022 10:44:16 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nglLA-002rUd-96 for linux-arm-kernel@lists.infradead.org; Tue, 19 Apr 2022 10:44:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B0D3A6123E; Tue, 19 Apr 2022 10:44:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F89DC385A5; Tue, 19 Apr 2022 10:44:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650365048; bh=goiYYQXMrTnsSKumUMFAGYlju9olFXyMUjWGA5iONw0=; h=From:To:Cc:Subject:Date:From; b=fcZVaeG2Rto0/PJLRsHZ8TcPeCEMDvZxzsOuYaUmVWc4s7Y8xQSkh7+J3UesN8+n7 4htnoW7+y9zjlhyI7PVe/N2Iz439UOEr6YXM1bcn4NTd6NLDuB6YbvJPKzT1lPYv8h ufBMNQRg/YiWvWmba6AB9XbHx4T1UJIT9UoQS1qghYPPr4flWFq5hgtC60Mh11He95 QpTa13DjESfwjT07QFqhOHRaTaSOUP8zv04uWFXsl1V0rNHybsQzN7pvkSCgA5r2hU 1Dttu1MgPaj13yHqc4/ztA2dOYdTn5KhspUWYfmxZ0ZmEMfbUVWbBXLWIK+bhBCRfP 0Z+4E3By1uw2Q== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v4 0/8] arm64: Automatic system register definition generation Date: Tue, 19 Apr 2022 11:43:21 +0100 Message-Id: <20220419104329.188489-1-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5634; h=from:subject; bh=goiYYQXMrTnsSKumUMFAGYlju9olFXyMUjWGA5iONw0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiXpJKBwkKTG2CayPLnHzNIJpEfSxe1G4cKck6z9E5 6o4RcjeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYl6SSgAKCRAk1otyXVSH0HSEB/ 9MAEafrENzoMN4SOhJ2g9UcN/1IgGjnaE0dBdFUTxAnRWZKh2EeOOu41RmVVn3+8K2yBgHh1+OSs1J 0N2XsXS4mtNPEpXGj3i/KQbX6R1KuuzIe7z3PmPylzXuyiBIo423spYt2l0nGE0iE2GLcexXHmVWdT f/V4JtF/B/a8gKIWXfFGHnnuhp/mV4gBYYB038BrIRl/VBnaBPWSgL3gT5MfaBZVsEAINJmGXEWCzg wvJsysx85dmykKpOwYU9jVFtwcpyT5rMgueBR6DufP3vGkpWcIfmTMmhyDJRGM08WNrEtQf1lx1SGb UMejd9KMJov4VyhLogVpk9qiCTyyIp X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_034412_439996_C9BD6B5D X-CRM114-Status: GOOD ( 24.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The arm64 kernel requires some metadata for each system register it may need to access. Currently we have: * A SYS_ definition which sorresponds to a sys_reg() macro. This is used both to look up a sysreg by encoding (e.g. in KVM), and also to generate code to access a sysreg where the assembler is unaware of the specific sysreg encoding. Where assemblers support the S3__C_C_ syntax for system registers, we could use this rather than manually assembling the instructions. However, we don't have consistent definitions for these and we currently still need to handle toolchains that lack this feature. * A set of __SHIFT and __MASK definitions, which can be used to extract fields from the register, or to construct a register from a set of fields. These do not follow the convention used by , and the masks are not shifted into place, preventing their use in FIELD_PREP() and FIELD_GET(). We require the SHIFT definitions for inline assembly (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and unshifted MASK is tedious and error-prone and life is much easier when they can be relied up to exist when writing code. * A set of __ definitions for each enumerated value a field may hold. These are used when identifying the presence of features. Atop of this, other code has to build up metadata at runtime (e.g. the sets of RES0/RES1 bits in a register). This patch series introduces a script which describes registers and the fields within them in a format that is easy to cross reference with the architecture reference manual and uses them to generate the constants we use in a standard format: | #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | #define SYS_ID_AA64ISAR0_EL1_Op0 3 | #define SYS_ID_AA64ISAR0_EL1_Op1 0 | #define SYS_ID_AA64ISAR0_EL1_CRn 0 | #define SYS_ID_AA64ISAR0_EL1_CRm 6 | #define SYS_ID_AA64ISAR0_EL1_Op2 0 | #define ID_AA64ISAR0_EL1_RNDR ARM64_SYSREG_BITMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_MASK ARM64_SYSREG_BITMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 | #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 | #define ID_AA64ISAR0_EL1_RNDR_NI ULL(0b0000) | #define ID_AA64ISAR0_EL1_RNDR_IMP ULL(0b0001) This should be particularly useful for the ID registers where we will be able to specify just the register and field for more of the bitfield information, simplifying ARM64_FTR_BITS() and providing helpers for use in struct arm64_cpu_capabilities or for hwcaps. At the moment this is only intended to express metadata from the architecture, and does not handle policy imposed by the kernel, such as values exposed to userspace or VMs. In future this could be extended to express such information. This could also be extended to cover more information such as the FTR_SIGNED/FTR_UNSIGNED distinction. There is also currently no support for registers which change layout at runtime, for example based on virtualisation settings - these could be manually handled for the time being, or the script extended. At the present time (especially given how near we are to the merge window) this is as much about getting feedback on the general approach and how to move forward if we want to move forward. Rather than attempting to convert every register at once the current series converts a few sample registers to provide some concrete examples but allow for easier updating during review of the file format and the script. Handling a register at a time should also make review less taxing so it seems like a sensible approach in general. The generation script was originally written by Mark Rutland and subsequently improved and integrated into the kernel build by me. v4: - Rebase onto v5.18-rc3. v3: - Rebase onto v5.18-rc1. v2: - Fix issue with building bounds.s in an O= build by renaming the generated header. Mark Brown (7): arm64/mte: Move shift from definition of TCF0 enumeration values arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI arm64/sysreg: Enable automatic generation of system register definitions arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 arm64/sysreg: Generate definitions for TTBRn_EL1 arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Rutland (1): arm64: Add sysreg header generation scripting arch/arm64/include/asm/Kbuild | 1 + arch/arm64/include/asm/archrandom.h | 2 +- arch/arm64/include/asm/sysreg.h | 61 +---- arch/arm64/kernel/cpufeature.c | 70 +++--- arch/arm64/kernel/mte.c | 6 +- .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 +-- arch/arm64/tools/Makefile | 8 +- arch/arm64/tools/gen-sysreg.awk | 213 ++++++++++++++++++ arch/arm64/tools/sysreg | 183 +++++++++++++++ 9 files changed, 466 insertions(+), 106 deletions(-) create mode 100755 arch/arm64/tools/gen-sysreg.awk create mode 100644 arch/arm64/tools/sysreg base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel