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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Luca Salabrino <luca.scalabrino@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v14 12/39] arm64/sme: Implement support for TPIDR2
Date: Tue, 19 Apr 2022 12:22:20 +0100	[thread overview]
Message-ID: <20220419112247.711548-13-broonie@kernel.org> (raw)
In-Reply-To: <20220419112247.711548-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 5ddfae233ea5..14a8f3d93add 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -778,6 +778,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 7a57cbff8a03..849e97d418a8 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -169,6 +169,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 39f44fcb9b99..231f2d85b65e 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1098,6 +1098,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 7fa97df55e3a..e20571f19718 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	Mark Brown <broonie@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org,
	Alan Hayward <alan.hayward@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	Luca Salabrino <luca.scalabrino@arm.com>
Subject: [PATCH v14 12/39] arm64/sme: Implement support for TPIDR2
Date: Tue, 19 Apr 2022 12:22:20 +0100	[thread overview]
Message-ID: <20220419112247.711548-13-broonie@kernel.org> (raw)
In-Reply-To: <20220419112247.711548-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 5ddfae233ea5..14a8f3d93add 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -778,6 +778,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 7a57cbff8a03..849e97d418a8 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -169,6 +169,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 39f44fcb9b99..231f2d85b65e 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1098,6 +1098,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 7fa97df55e3a..e20571f19718 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
	Luis Machado <luis.machado@arm.com>,
	Salil Akerkar <Salil.Akerkar@arm.com>,
	Basant Kumar Dwivedi <Basant.KumarDwivedi@arm.com>,
	Szabolcs Nagy <szabolcs.nagy@arm.com>,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Luca Salabrino <luca.scalabrino@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v14 12/39] arm64/sme: Implement support for TPIDR2
Date: Tue, 19 Apr 2022 12:22:20 +0100	[thread overview]
Message-ID: <20220419112247.711548-13-broonie@kernel.org> (raw)
In-Reply-To: <20220419112247.711548-1-broonie@kernel.org>

The Scalable Matrix Extension introduces support for a new thread specific
data register TPIDR2 intended for use by libc. The kernel must save the
value of TPIDR2 on context switch and should ensure that all new threads
start off with a default value of 0. Add a field to the thread_struct to
store TPIDR2 and context switch it with the other thread specific data.

In case there are future extensions which also use TPIDR2 we introduce
system_supports_tpidr2() and use that rather than system_supports_sme()
for TPIDR2 handling.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/include/asm/cpufeature.h |  5 +++++
 arch/arm64/include/asm/processor.h  |  1 +
 arch/arm64/kernel/fpsimd.c          |  4 ++++
 arch/arm64/kernel/process.c         | 14 ++++++++++++--
 4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 5ddfae233ea5..14a8f3d93add 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -778,6 +778,11 @@ static __always_inline bool system_supports_fa64(void)
 		cpus_have_const_cap(ARM64_SME_FA64);
 }
 
+static __always_inline bool system_supports_tpidr2(void)
+{
+	return system_supports_sme();
+}
+
 static __always_inline bool system_supports_cnp(void)
 {
 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index 7a57cbff8a03..849e97d418a8 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -169,6 +169,7 @@ struct thread_struct {
 	u64			mte_ctrl;
 #endif
 	u64			sctlr_user;
+	u64			tpidr2_el0;
 };
 
 static inline unsigned int thread_get_vl(struct thread_struct *thread,
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 39f44fcb9b99..231f2d85b65e 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1098,6 +1098,10 @@ void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
 	/* Allow SME in kernel */
 	write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
 	isb();
+
+	/* Allow EL0 to access TPIDR2 */
+	write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
+	isb();
 }
 
 /*
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 7fa97df55e3a..e20571f19718 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -250,6 +250,8 @@ void show_regs(struct pt_regs *regs)
 static void tls_thread_flush(void)
 {
 	write_sysreg(0, tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(0, SYS_TPIDR2_EL0);
 
 	if (is_compat_task()) {
 		current->thread.uw.tp_value = 0;
@@ -343,6 +345,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 		 * out-of-sync with the saved value.
 		 */
 		*task_user_tls(p) = read_sysreg(tpidr_el0);
+		if (system_supports_tpidr2())
+			p->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 
 		if (stack_start) {
 			if (is_compat_thread(task_thread_info(p)))
@@ -353,10 +357,12 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 
 		/*
 		 * If a TLS pointer was passed to clone, use it for the new
-		 * thread.
+		 * thread.  We also reset TPIDR2 if it's in use.
 		 */
-		if (clone_flags & CLONE_SETTLS)
+		if (clone_flags & CLONE_SETTLS) {
 			p->thread.uw.tp_value = tls;
+			p->thread.tpidr2_el0 = 0;
+		}
 	} else {
 		/*
 		 * A kthread has no context to ERET to, so ensure any buggy
@@ -387,6 +393,8 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start,
 void tls_preserve_current_state(void)
 {
 	*task_user_tls(current) = read_sysreg(tpidr_el0);
+	if (system_supports_tpidr2() && !is_compat_task())
+		current->thread.tpidr2_el0 = read_sysreg_s(SYS_TPIDR2_EL0);
 }
 
 static void tls_thread_switch(struct task_struct *next)
@@ -399,6 +407,8 @@ static void tls_thread_switch(struct task_struct *next)
 		write_sysreg(0, tpidrro_el0);
 
 	write_sysreg(*task_user_tls(next), tpidr_el0);
+	if (system_supports_tpidr2())
+		write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0);
 }
 
 /*
-- 
2.30.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2022-04-19 11:24 UTC|newest]

Thread overview: 177+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-19 11:22 [PATCH v14 00/39] arm64/sme: Initial support for the Scalable Matrix Extension Mark Brown
2022-04-19 11:22 ` Mark Brown
2022-04-19 11:22 ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 01/39] kselftest/arm64: Fix comment for ptrace_sve_get_fpsimd_data() Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 02/39] kselftest/arm64: Remove assumption that tasks start FPSIMD only Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 03/39] kselftest/arm64: Validate setting via FPSIMD and read via SVE regsets Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 04/39] arm64/sme: Provide ABI documentation for SME Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-28  9:19   ` Catalin Marinas
2022-04-28  9:19     ` Catalin Marinas
2022-04-28  9:19     ` Catalin Marinas
2022-05-03  8:13     ` Szabolcs Nagy
2022-05-03  8:13       ` Szabolcs Nagy
2022-05-03  8:13       ` Szabolcs Nagy
2022-04-19 11:22 ` [PATCH v14 05/39] arm64/sme: System register and exception syndrome definitions Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 06/39] arm64/sme: Manually encode SME instructions Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 07/39] arm64/sme: Early CPU setup for SME Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 08/39] arm64/sme: Basic enumeration support Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 09/39] arm64/sme: Identify supported SME vector lengths at boot Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 10/39] arm64/sme: Implement sysctl to set the default vector length Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 11/39] arm64/sme: Implement vector length configuration prctl()s Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` Mark Brown [this message]
2022-04-19 11:22   ` [PATCH v14 12/39] arm64/sme: Implement support for TPIDR2 Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 13/39] arm64/sme: Implement SVCR context switching Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 14/39] arm64/sme: Implement streaming SVE " Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 15/39] arm64/sme: Implement ZA " Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 16/39] arm64/sme: Implement traps and syscall handling for SME Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-22 16:28   ` Catalin Marinas
2022-04-22 16:28     ` Catalin Marinas
2022-04-22 16:28     ` Catalin Marinas
2022-12-07 14:00   ` Zenghui Yu
2022-12-07 14:00     ` Zenghui Yu
2022-12-07 14:00     ` Zenghui Yu
2022-12-07 14:16     ` Mark Brown
2022-12-07 14:16       ` Mark Brown
2022-12-07 14:16       ` Mark Brown
2022-12-08  2:15       ` Zenghui Yu
2022-12-08  2:15         ` Zenghui Yu
2022-12-08  2:15         ` Zenghui Yu
2022-04-19 11:22 ` [PATCH v14 17/39] arm64/sme: Disable ZA and streaming mode when handling signals Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 18/39] arm64/sme: Implement streaming SVE signal handling Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 19/39] arm64/sme: Implement ZA " Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 20/39] arm64/sme: Implement ptrace support for streaming mode SVE registers Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 21/39] arm64/sme: Add ptrace support for ZA Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 22/39] arm64/sme: Disable streaming mode and ZA when flushing CPU state Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 23/39] arm64/sme: Save and restore streaming mode over EFI runtime calls Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 24/39] KVM: arm64: Hide SME system registers from guests Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 25/39] KVM: arm64: Trap SME usage in guest Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 26/39] KVM: arm64: Handle SME host state when running guests Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 27/39] arm64/sme: Provide Kconfig for SME Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
     [not found]   ` <CGME20220426221433eucas1p253f6350eacf87d8cac2c05adc903656e@eucas1p2.samsung.com>
2022-04-26 22:14     ` Marek Szyprowski
2022-04-26 22:14       ` Marek Szyprowski
2022-04-26 22:14       ` Marek Szyprowski
2022-04-27 12:55       ` Mark Brown
2022-04-27 12:55         ` Mark Brown
2022-04-27 12:55         ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 28/39] kselftest/arm64: Add manual encodings for SME instructions Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 29/39] kselftest/arm64: sme: Add SME support to vlset Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 30/39] kselftest/arm64: Add tests for TPIDR2 Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 31/39] kselftest/arm64: Extend vector configuration API tests to cover SME Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 32/39] kselftest/arm64: sme: Provide streaming mode SVE stress test Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 33/39] kselftest/arm64: signal: Handle ZA signal context in core code Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 34/39] kselftest/arm64: Add stress test for SME ZA context switching Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 35/39] kselftest/arm64: signal: Add SME signal handling tests Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 36/39] kselftest/arm64: Add streaming SVE to SVE ptrace tests Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 37/39] kselftest/arm64: Add coverage for the ZA ptrace interface Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 38/39] kselftest/arm64: Add SME support to syscall ABI test Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22 ` [PATCH v14 39/39] selftests/arm64: Add a testcase for handling of ZA on clone() Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-19 11:22   ` Mark Brown
2022-04-22 17:10 ` [PATCH v14 00/39] arm64/sme: Initial support for the Scalable Matrix Extension Marc Zyngier
2022-04-22 17:10   ` Marc Zyngier
2022-04-22 17:10   ` Marc Zyngier
2022-04-22 18:35   ` Catalin Marinas
2022-04-22 18:35     ` Catalin Marinas
2022-04-22 18:35     ` Catalin Marinas
2022-04-22 18:26 ` (subset) " Catalin Marinas
2022-04-22 18:26   ` Catalin Marinas
2022-04-22 18:26   ` Catalin Marinas
2022-04-27 17:08 ` Qian Cai
2022-04-27 17:08   ` Qian Cai
2022-04-27 17:08   ` Qian Cai
2022-04-27 17:14   ` Mark Brown
2022-04-27 17:14     ` Mark Brown
2022-04-27 17:14     ` Mark Brown
2022-04-27 21:08     ` Qian Cai
2022-04-27 21:08       ` Qian Cai
2022-04-27 21:08       ` Qian Cai
2022-04-27 22:13       ` Mark Brown
2022-04-27 22:13         ` Mark Brown
2022-04-27 22:13         ` Mark Brown
2022-05-03 22:23 ` Qian Cai
2022-05-03 22:23   ` Qian Cai
2022-05-03 22:23   ` Qian Cai
2022-05-03 23:52   ` Mark Brown
2022-05-03 23:52     ` Mark Brown
2022-05-03 23:52     ` Mark Brown
2022-05-04  5:25     ` Naresh Kamboju
2022-05-04  5:25       ` Naresh Kamboju
2022-05-04  5:25       ` Naresh Kamboju
2022-05-04  7:49     ` Naresh Kamboju
2022-05-04  7:49       ` Naresh Kamboju
2022-05-04  7:49       ` Naresh Kamboju

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