[PATCH 00/15] treewide: Initial support for R-Car V4H

[PATCH 00/15] treewide: Initial support for R-Car V4H

[Yoshihiro Shimoda]

This patch series adds initial support for the Renesas R-Car V4H
(r8a779g0) SoC.

Yoshihiro Shimoda (15):
  dt-bindings: arm: renesas: Document R-Car V4H SoC DT bindings
  dt-bindings: arm: renesas: Document Renesas White Hawk boards
  dt-bindings: reset: renesas,rst: Document r8a779g0 reset module
  dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings
  dt-bindings: power: Add r8a779g0 SYSC power domain definitions
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0
  dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions
  dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings
  soc: renesas: r8a779g0-sysc: Add r8a779g0 support
  soc: renesas: Identify R-Car V4H
  soc: renesas: rcar-rst: Add support for R-Car V4H
  clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4
  clk: renesas: cpg-mssr: Add support for R-Car V4H
  arm64: dts: renesas: Add Renesas R8A779G0 SoC support
  arm64: dts: renesas: Add Renesas White Hawk boards support

 .../devicetree/bindings/arm/renesas.yaml      |  12 +
 .../bindings/clock/renesas,cpg-mssr.yaml      |   1 +
 .../bindings/power/renesas,rcar-sysc.yaml     |   1 +
 .../bindings/reset/renesas,rst.yaml           |   1 +
 .../bindings/serial/renesas,hscif.yaml        |   6 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../dts/renesas/r8a779g0-white-hawk-cpu.dtsi  |  45 ++++
 .../boot/dts/renesas/r8a779g0-white-hawk.dts  |  22 ++
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi     | 122 ++++++++++
 drivers/clk/renesas/Kconfig                   |   5 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r8a779f0-cpg-mssr.c       |  18 +-
 drivers/clk/renesas/r8a779g0-cpg-mssr.c       | 215 ++++++++++++++++++
 drivers/clk/renesas/rcar-gen4-cpg.c           |   5 +
 drivers/clk/renesas/rcar-gen4-cpg.h           |   3 +
 drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h        |   1 +
 drivers/soc/renesas/Kconfig                   |  11 +
 drivers/soc/renesas/Makefile                  |   1 +
 drivers/soc/renesas/r8a779g0-sysc.c           |  62 +++++
 drivers/soc/renesas/rcar-gen4-sysc.c          |   3 +
 drivers/soc/renesas/rcar-gen4-sysc.h          |   1 +
 drivers/soc/renesas/rcar-rst.c                |   1 +
 drivers/soc/renesas/renesas-soc.c             |   8 +
 include/dt-bindings/clock/r8a779g0-cpg-mssr.h |  87 +++++++
 include/dt-bindings/power/r8a779g0-sysc.h     |  45 ++++
 26 files changed, 676 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi
 create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c
 create mode 100644 drivers/soc/renesas/r8a779g0-sysc.c
 create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h

-- 
2.25.1

[PATCH 01/15] dt-bindings: arm: renesas: Document R-Car V4H SoC DT bindings

[Yoshihiro Shimoda]

Add device tree bindings documentation for Renesas R-Car V4H
(r8a779f0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index f61807103867..bbb7c63ce2a8 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -327,6 +327,10 @@ properties:
           - const: renesas,spider-cpu
           - const: renesas,r8a779f0
 
+      - description: R-Car V4H (R8A779G0)
+        items:
+          - const: renesas,r8a779g0
+
       - description: R-Car H3e (R8A779M0)
         items:
           - enum:
-- 
2.25.1

[PATCH 02/15] dt-bindings: arm: renesas: Document Renesas White Hawk boards

[Yoshihiro Shimoda]

Add device tree bindings documentation for Renesas R-Car V4H
White Hawk CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index bbb7c63ce2a8..5408b154d05e 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -329,6 +329,14 @@ properties:
 
       - description: R-Car V4H (R8A779G0)
         items:
+          - enum:
+              - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
+          - const: renesas,r8a779g0
+
+      - items:
+          - enum:
+              - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
+          - const: renesas,white-hawk-cpu
           - const: renesas,r8a779g0
 
       - description: R-Car H3e (R8A779M0)
-- 
2.25.1

[PATCH 03/15] dt-bindings: reset: renesas,rst: Document r8a779g0 reset module

[Yoshihiro Shimoda]

Document bindings for the R-Car V4H (R8A779G0) reset module.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
index bbe313bf1796..0d1b89e2fe9c 100644
--- a/Documentation/devicetree/bindings/reset/renesas,rst.yaml
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
@@ -49,6 +49,7 @@ properties:
       - renesas,r8a77995-rst      # R-Car D3
       - renesas,r8a779a0-rst      # R-Car V3U
       - renesas,r8a779f0-rst      # R-Car S4-8
+      - renesas,r8a779g0-rst      # R-Car V4H
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH 04/15] dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings

[Yoshihiro Shimoda]

Document bindings for the R-Car V4H (aka R8A779G0) SYSC block.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
index 76c417990f12..8d56bedd3390 100644
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
@@ -44,6 +44,7 @@ properties:
       - renesas,r8a77995-sysc # R-Car D3
       - renesas,r8a779a0-sysc # R-Car V3U
       - renesas,r8a779f0-sysc # R-Car S4-8
+      - renesas,r8a779g0-sysc # R-Car V4H
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH 05/15] dt-bindings: power: Add r8a779g0 SYSC power domain definitions

[Yoshihiro Shimoda]

Add power domain indices for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 include/dt-bindings/power/r8a779g0-sysc.h | 45 +++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a779g0-sysc.h

diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
new file mode 100644
index 000000000000..da79c4b39556
--- /dev/null
+++ b/include/dt-bindings/power/r8a779g0-sysc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779G0_PD_A1E0D0C0		0
+#define R8A779G0_PD_A1E0D0C1		1
+#define R8A779G0_PD_A1E0D1C0		2
+#define R8A779G0_PD_A1E0D1C1		3
+#define R8A779G0_PD_A2E0D0		16
+#define R8A779G0_PD_A2E0D1		17
+#define R8A779G0_PD_A3E0		20
+#define R8A779G0_PD_A33DGA		24
+#define R8A779G0_PD_A23DGB		25
+#define R8A779G0_PD_A1DSP0		33
+#define R8A779G0_PD_A2IMP01		34
+#define R8A779G0_PD_A2PSC		35
+#define R8A779G0_PD_A2CV0		36
+#define R8A779G0_PD_A2CV1		37
+#define R8A779G0_PD_A1CNN0		41
+#define R8A779G0_PD_A2CN0		42
+#define R8A779G0_PD_A3IR		43
+#define R8A779G0_PD_A1DSP1		45
+#define R8A779G0_PD_A2IMP23		46
+#define R8A779G0_PD_A2DMA		47
+#define R8A779G0_PD_A2CV2		48
+#define R8A779G0_PD_A2CV3		49
+#define R8A779G0_PD_A1DSP2		53
+#define R8A779G0_PD_A1DSP3		54
+#define R8A779G0_PD_A3VIP0		56
+#define R8A779G0_PD_A3VIP1		57
+#define R8A779G0_PD_A3VIP2		58
+#define R8A779G0_PD_A3ISP0		60
+#define R8A779G0_PD_A3ISP1		61
+
+/* Always-on power area */
+#define R8A779G0_PD_ALWAYS_ON		64
+
+#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
-- 
2.25.1

[PATCH 06/15] dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0

[Yoshihiro Shimoda]

Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse
Generator.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
index e0b86214f0f5..e57bc40d307a 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
@@ -49,6 +49,7 @@ properties:
       - renesas,r8a77995-cpg-mssr # R-Car D3
       - renesas,r8a779a0-cpg-mssr # R-Car V3U
       - renesas,r8a779f0-cpg-mssr # R-Car S4-8
+      - renesas,r8a779g0-cpg-mssr # R-Car V4H
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car V4H (R8A779G0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h

diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
new file mode 100644
index 000000000000..07a94cf45581
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779g0 CPG Core Clocks */
+
+#define R8A779G0_CLK_ZX			0
+#define R8A779G0_CLK_ZS			1
+#define R8A779G0_CLK_ZT			2
+#define R8A779G0_CLK_ZTR		3
+#define R8A779G0_CLK_S0D2		4
+#define R8A779G0_CLK_S0D3		5
+#define R8A779G0_CLK_S0D4		6
+#define R8A779G0_CLK_S0D1_VIO		7
+#define R8A779G0_CLK_S0D2_VIO		8
+#define R8A779G0_CLK_S0D4_VIO		9
+#define R8A779G0_CLK_S0D8_VIO		10
+#define R8A779G0_CLK_S0D1_VC		11
+#define R8A779G0_CLK_S0D2_VC		12
+#define R8A779G0_CLK_S0D4_VC		13
+#define R8A779G0_CLK_S0D2_MM		14
+#define R8A779G0_CLK_S0D4_MM		15
+#define R8A779G0_CLK_S0D2_U3DG		16
+#define R8A779G0_CLK_S0D4_U3DG		17
+#define R8A779G0_CLK_S0D2_RT		18
+#define R8A779G0_CLK_S0D3_RT		19
+#define R8A779G0_CLK_S0D4_RT		20
+#define R8A779G0_CLK_S0D6_RT		21
+#define R8A779G0_CLK_S0D24_RT		22
+#define R8A779G0_CLK_S0D2_PER		23
+#define R8A779G0_CLK_S0D3_PER		24
+#define R8A779G0_CLK_S0D6_PER		25
+#define R8A779G0_CLK_S0D12_PER		26
+#define R8A779G0_CLK_S0D24_PER		27
+#define R8A779G0_CLK_S0D1_HSC		28
+#define R8A779G0_CLK_S0D2_HSC		29
+#define R8A779G0_CLK_S0D4_HSC		30
+#define R8A779G0_CLK_S0D2_CC		31
+#define R8A779G0_CLK_SVD1_IR		32
+#define R8A779G0_CLK_SVD2_IR		33
+#define R8A779G0_CLK_SVD1_VIP		34
+#define R8A779G0_CLK_SVD2_VIP		35
+#define R8A779G0_CLK_CL			36
+#define R8A779G0_CLK_CL16M		37
+#define R8A779G0_CLK_CL16M_MM		38
+#define R8A779G0_CLK_CL16M_RT		39
+#define R8A779G0_CLK_CL16M_PER		40
+#define R8A779G0_CLK_CL16M_HSC		41
+#define R8A779G0_CLK_Z0			42
+#define R8A779G0_CLK_ZB3		43
+#define R8A779G0_CLK_ZB3D2		44
+#define R8A779G0_CLK_ZB3D4		45
+#define R8A779G0_CLK_ZG			46
+#define R8A779G0_CLK_SD0H		47
+#define R8A779G0_CLK_SD0		48
+#define R8A779G0_CLK_RPC		49
+#define R8A779G0_CLK_RPCD2		50
+#define R8A779G0_CLK_MSO		51
+#define R8A779G0_CLK_CANFD		52
+#define R8A779G0_CLK_CSI		53
+#define R8A779G0_CLK_FRAY		54
+#define R8A779G0_CLK_IPC		55
+#define R8A779G0_CLK_SASYNCRT		56
+#define R8A779G0_CLK_SASYNCPERD1	57
+#define R8A779G0_CLK_SASYNCPERD2	58
+#define R8A779G0_CLK_SASYNCPERD4	59
+#define R8A779G0_CLK_VIOBUSD2		60
+#define R8A779G0_CLK_VCBUSD2		61
+#define R8A779G0_CLK_IMPA1		62
+#define R8A779G0_CLK_DSIEXT		63
+#define R8A779G0_CLK_DSIREF		64
+#define R8A779G0_CLK_ADGH		65
+#define R8A779G0_CLK_OSC		66
+#define R8A779G0_CLK_ZR0		67
+#define R8A779G0_CLK_ZR1		68
+#define R8A779G0_CLK_ZR2		69
+#define R8A779G0_CLK_IMPAD4		70
+#define R8A779G0_CLK_CPEX		71
+#define R8A779G0_CLK_CBFUSA		72
+#define R8A779G0_CLK_R			73
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
-- 
2.25.1

[PATCH 08/15] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings

[Yoshihiro Shimoda]

R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
so document the SoC specific bindings.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
index ee9804cd49bb..c151c90714f5 100644
--- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
@@ -55,6 +55,12 @@ properties:
           - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
           - const: renesas,hscif           # generic HSCIF compatible UART
 
+      - items:
+          - enum:
+              - renesas,hscif-r8a779g0     # R-Car V4H
+          - const: renesas,rcar-gen4-hscif # R-Car Gen4
+          - const: renesas,hscif           # generic HSCIF compatible UART
+
   reg:
     maxItems: 1
 
-- 
2.25.1

[PATCH 09/15] soc: renesas: r8a779g0-sysc: Add r8a779g0 support

[Yoshihiro Shimoda]

Add support for R-Car V4H (R8A779G0) SoC power areas and register
access.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/Kconfig          |  4 ++
 drivers/soc/renesas/Makefile         |  1 +
 drivers/soc/renesas/r8a779g0-sysc.c  | 62 ++++++++++++++++++++++++++++
 drivers/soc/renesas/rcar-gen4-sysc.c |  3 ++
 drivers/soc/renesas/rcar-gen4-sysc.h |  1 +
 5 files changed, 71 insertions(+)
 create mode 100644 drivers/soc/renesas/r8a779g0-sysc.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 63477f05fbaf..422c8da82fad 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -369,6 +369,10 @@ config SYSC_R8A779F0
 	bool "System Controller support for R-Car S4-8" if COMPILE_TEST
 	select SYSC_RCAR_GEN4
 
+config SYSC_R8A779G0
+	bool "System Controller support for R-Car V4H" if COMPILE_TEST
+	select SYSC_RCAR_GEN4
+
 config SYSC_R8A7792
 	bool "System Controller support for R-Car V2H" if COMPILE_TEST
 	select SYSC_RCAR
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index deeb41f84f01..535868c9c7e4 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SYSC_R8A77990)	+= r8a77990-sysc.o
 obj-$(CONFIG_SYSC_R8A77995)	+= r8a77995-sysc.o
 obj-$(CONFIG_SYSC_R8A779A0)	+= r8a779a0-sysc.o
 obj-$(CONFIG_SYSC_R8A779F0)	+= r8a779f0-sysc.o
+obj-$(CONFIG_SYSC_R8A779G0)	+= r8a779g0-sysc.o
 ifdef CONFIG_SMP
 obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
diff --git a/drivers/soc/renesas/r8a779g0-sysc.c b/drivers/soc/renesas/r8a779g0-sysc.c
new file mode 100644
index 000000000000..a452709f066d
--- /dev/null
+++ b/drivers/soc/renesas/r8a779g0-sysc.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas R-Car V4H System Controller
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <linux/bits.h>
+#include <linux/clk/renesas.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/of_address.h>
+#include <linux/pm_domain.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <dt-bindings/power/r8a779g0-sysc.h>
+
+#include "rcar-gen4-sysc.h"
+
+static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
+	{ "always-on",	R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+	{ "a3e0",	R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
+	{ "a2e0d0",	R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
+	{ "a2e0d1",	R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
+	{ "a1e0d0c0",	R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
+	{ "a1e0d0c1",	R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
+	{ "a1e0d1c0",	R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
+	{ "a1e0d1c1",	R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
+	{ "a33dga",	R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
+	{ "a23dgb",	R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
+	{ "a3vip0",	R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
+	{ "a3vip1",	R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
+	{ "a3vip2",	R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
+	{ "a3isp0",	R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
+	{ "a3isp1",	R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
+	{ "a3ir",	R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
+	{ "a2cn0",	R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
+	{ "a1cnn0",	R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
+	{ "a1dsp0",	R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
+	{ "a1dsp1",	R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
+	{ "a1dsp2",	R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
+	{ "a1dsp3",	R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
+	{ "a2imp01",	R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
+	{ "a2imp23",	R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
+	{ "a2psc",	R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
+	{ "a2dma",	R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
+	{ "a2cv0",	R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
+	{ "a2cv1",	R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
+	{ "a2cv2",	R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
+	{ "a2cv3",	R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
+};
+
+const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
+	.areas = r8a779g0_areas,
+	.num_areas = ARRAY_SIZE(r8a779g0_areas),
+};
diff --git a/drivers/soc/renesas/rcar-gen4-sysc.c b/drivers/soc/renesas/rcar-gen4-sysc.c
index 831162a57f9a..9e5e6e077abc 100644
--- a/drivers/soc/renesas/rcar-gen4-sysc.c
+++ b/drivers/soc/renesas/rcar-gen4-sysc.c
@@ -281,6 +281,9 @@ static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = {
 #endif
 #ifdef CONFIG_SYSC_R8A779F0
 	{ .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info },
+#endif
+#ifdef CONFIG_SYSC_R8A779G0
+	{ .compatible = "renesas,r8a779g0-sysc", .data = &r8a779g0_sysc_info },
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/soc/renesas/rcar-gen4-sysc.h b/drivers/soc/renesas/rcar-gen4-sysc.h
index 0e0bd102b1f9..fe2d98254754 100644
--- a/drivers/soc/renesas/rcar-gen4-sysc.h
+++ b/drivers/soc/renesas/rcar-gen4-sysc.h
@@ -39,5 +39,6 @@ struct rcar_gen4_sysc_info {
 
 extern const struct rcar_gen4_sysc_info r8a779a0_sysc_info;
 extern const struct rcar_gen4_sysc_info r8a779f0_sysc_info;
+extern const struct rcar_gen4_sysc_info r8a779g0_sysc_info;
 
 #endif /* __SOC_RENESAS_RCAR_GEN4_SYSC_H__ */
-- 
2.25.1

[PATCH 10/15] soc: renesas: Identify R-Car V4H

[Yoshihiro Shimoda]

Add support for identifying the R-Car V4H (R8A779G0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/Kconfig       | 7 +++++++
 drivers/soc/renesas/renesas-soc.c | 8 ++++++++
 2 files changed, 15 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 422c8da82fad..e94ea3d6dcb0 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -247,6 +247,13 @@ config ARCH_R8A779F0
 	help
 	  This enables support for the Renesas R-Car S4-8 SoC.
 
+config ARCH_R8A779G0
+	bool "ARM64 Platform support for R-Car V4H"
+	select ARCH_RCAR_GEN3
+	select SYSC_R8A779G0
+	help
+	  This enables support for the Renesas R-Car V4H SoC.
+
 config ARCH_R8A77980
 	bool "ARM64 Platform support for R-Car V3H"
 	select ARCH_RCAR_GEN3
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 30192a099d38..5b995952a747 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -241,6 +241,11 @@ static const struct renesas_soc soc_rcar_s4 __initconst __maybe_unused = {
 	.id	= 0x5a,
 };
 
+static const struct renesas_soc soc_rcar_v4h __initconst __maybe_unused = {
+	.family	= &fam_rcar_gen4,
+	.id	= 0x5c,
+};
+
 static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = {
 	.family	= &fam_shmobile,
 	.id	= 0x37,
@@ -349,6 +354,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
 #ifdef CONFIG_ARCH_R8A779F0
 	{ .compatible = "renesas,r8a779f0",	.data = &soc_rcar_s4 },
 #endif
+#ifdef CONFIG_ARCH_R8A779G0
+	{ .compatible = "renesas,r8a779g0",	.data = &soc_rcar_v4h },
+#endif
 #if defined(CONFIG_ARCH_R9A07G043)
 	{ .compatible = "renesas,r9a07g043",	.data = &soc_rz_g2ul },
 #endif
-- 
2.25.1

[PATCH 11/15] soc: renesas: rcar-rst: Add support for R-Car V4H

[Yoshihiro Shimoda]

Add support for R-Car V4H (R8A779G0) to the R-Car RST driver.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/soc/renesas/rcar-rst.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 4d293eb2d8f3..e1c7e91f5a86 100644
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -103,6 +103,7 @@ static const struct of_device_id rcar_rst_matches[] __initconst = {
 	/* R-Car Gen4 */
 	{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
 	{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
+	{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
 	{ /* sentinel */ }
 };
 
-- 
2.25.1

[PATCH 12/15] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4

[Yoshihiro Shimoda]

R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +++++++++---------
 drivers/clk/renesas/rcar-gen4-cpg.c     |  5 +++++
 drivers/clk/renesas/rcar-gen4-cpg.h     |  3 +++
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 08e8d95ce5e7..be9dcc00d3ab 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -142,23 +142,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
  * CPG Clock Data
  */
 /*
- *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL5	PLL6	OSC
+ *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC
  * 14 13 (MHz)
  * ----------------------------------------------------------------
- * 0  0	 16    / 1	x200	x150	x200	x200	x134	/15
- * 0  1	 20    / 1	x160	x120	x160	x160	x106	/19
+ * 0  0	 16    / 1	x200	x150	x200	n/a	x200	x134	/15
+ * 0  1	 20    / 1	x160	x120	x160	n/a	x160	x106	/19
  * 1  0	 Prohibited setting
- * 1  1	 40    / 2	x160	x120	x160	x160	x106	/38
+ * 1  1	 40    / 2	x160	x120	x160	n/a	x160	x106	/38
  */
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
 					 (((md) & BIT(13)) >> 13))
 
 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
-	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */
-	{ 1,		200,	1,	150,	1,	200,	1,	200,	1,	134,	1,	15,	},
-	{ 1,		160,	1,	120,	1,	160,	1,	160,	1,	106,	1,	19,	},
-	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},
-	{ 2,		160,	1,	120,	1,	160,	1,	160,	1,	106,	1,	38,	},
+	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */
+	{ 1,		200,	1,	150,	1,	200,	1,	0,	0,	200,	1,	134,	1,	15,	},
+	{ 1,		160,	1,	120,	1,	160,	1,	0,	0,	160,	1,	106,	1,	19,	},
+	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},
+	{ 2,		160,	1,	120,	1,	160,	1,	0,	0,	160,	1,	106,	1,	38,	},
 };
 
 static int __init r8a779f0_cpg_mssr_init(struct device *dev)
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 54ebf4b3c128..c7ed43d6aa67 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -215,6 +215,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
 		div = cpg_pll_config->pll3_div;
 		break;
 
+	case CLK_TYPE_GEN4_PLL4:
+		mult = cpg_pll_config->pll4_mult;
+		div = cpg_pll_config->pll4_div;
+		break;
+
 	case CLK_TYPE_GEN4_PLL5:
 		mult = cpg_pll_config->pll5_mult;
 		div = cpg_pll_config->pll5_div;
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index afc8c024d538..0b15dcfdca7b 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -16,6 +16,7 @@ enum rcar_gen4_clk_types {
 	CLK_TYPE_GEN4_PLL2X_3X,	/* r8a779a0 only */
 	CLK_TYPE_GEN4_PLL3,
 	CLK_TYPE_GEN4_PLL5,
+	CLK_TYPE_GEN4_PLL4,
 	CLK_TYPE_GEN4_PLL6,
 	CLK_TYPE_GEN4_SDSRC,
 	CLK_TYPE_GEN4_SDH,
@@ -56,6 +57,8 @@ struct rcar_gen4_cpg_pll_config {
 	u8 pll2_div;
 	u8 pll3_mult;
 	u8 pll3_div;
+	u8 pll4_mult;
+	u8 pll4_div;
 	u8 pll5_mult;
 	u8 pll5_div;
 	u8 pll6_mult;
-- 
2.25.1

[PATCH 13/15] clk: renesas: cpg-mssr: Add support for R-Car V4H

[Yoshihiro Shimoda]

Initial CPG support for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/clk/renesas/Kconfig             |   5 +
 drivers/clk/renesas/Makefile            |   1 +
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 215 ++++++++++++++++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c  |   6 +
 drivers/clk/renesas/renesas-cpg-mssr.h  |   1 +
 5 files changed, 228 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a779g0-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index a95ed8f310da..7e9b9a5bb5b7 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -32,6 +32,7 @@ config CLK_RENESAS
 	select CLK_R8A77995 if ARCH_R8A77995
 	select CLK_R8A779A0 if ARCH_R8A779A0
 	select CLK_R8A779F0 if ARCH_R8A779F0
+	select CLK_R8A779G0 if ARCH_R8A779G0
 	select CLK_R9A06G032 if ARCH_R9A06G032
 	select CLK_R9A07G043 if ARCH_R9A07G043
 	select CLK_R9A07G044 if ARCH_R9A07G044
@@ -158,6 +159,10 @@ config CLK_R8A779F0
 	bool "R-Car S4-8 clock support" if COMPILE_TEST
 	select CLK_RCAR_GEN4_CPG
 
+config CLK_R8A779G0
+	bool "R-Car V4H clock support" if COMPILE_TEST
+	select CLK_RCAR_GEN4_CPG
+
 config CLK_R9A06G032
 	bool "RZ/N1D clock support" if COMPILE_TEST
 
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index ca3a9bbcf27a..b83062af090c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779A0)		+= r8a779a0-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A779F0)		+= r8a779f0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779G0)		+= r8a779g0-cpg-mssr.o
 obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o
 obj-$(CONFIG_CLK_R9A07G043)		+= r9a07g043-cpg.o
 obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
new file mode 100644
index 000000000000..eaa89bbfd006
--- /dev/null
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on r8a779g0-cpg-mssr.c
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen4-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R8A779G0_CLK_R,
+
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_EXTALR,
+
+	/* Internal Core Clocks */
+	CLK_MAIN,
+	CLK_PLL1,
+	CLK_PLL2,
+	CLK_PLL3,
+	CLK_PLL4,
+	CLK_PLL5,
+	CLK_PLL6,
+	CLK_PLL1_DIV2,
+	CLK_PLL2_DIV2,
+	CLK_PLL3_DIV2,
+	CLK_PLL4_DIV2,
+	CLK_PLL5_DIV2,
+	CLK_PLL5_DIV4,
+	CLK_PLL6_DIV2,
+	CLK_S0,
+	CLK_S0_VIO,
+	CLK_S0_VC,
+	CLK_S0_HSC,
+	CLK_SV_VIP,
+	CLK_SV_IR,
+	CLK_SDSRC,
+	CLK_RPCSRC,
+	CLK_VIOBUS,
+	CLK_VCBUS,
+	CLK_OCO,
+
+	/* Module Clocks */
+	MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal",	CLK_EXTAL),
+	DEF_INPUT("extalr",	CLK_EXTALR),
+
+	/* Internal Core Clocks */
+	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+	DEF_BASE(".pll2", CLK_PLL2,	CLK_TYPE_GEN4_PLL2, CLK_MAIN),
+	DEF_BASE(".pll3", CLK_PLL3,	CLK_TYPE_GEN4_PLL3, CLK_MAIN),
+	DEF_BASE(".pll4", CLK_PLL4,	CLK_TYPE_GEN4_PLL4, CLK_MAIN),
+	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),
+	DEF_BASE(".pll6", CLK_PLL6,	CLK_TYPE_GEN4_PLL6, CLK_MAIN),
+
+	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
+	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),
+	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),
+	DEF_FIXED(".pll4_div2",	CLK_PLL4_DIV2,	CLK_PLL4,	2, 1),
+	DEF_FIXED(".pll5_div2",	CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),
+	DEF_FIXED(".pll5_div4",	CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),
+	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),
+	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),
+	DEF_FIXED(".s0_vio",	CLK_S0_VIO,	CLK_PLL1_DIV2,	2, 1),
+	DEF_FIXED(".s0_vc",	CLK_S0_VC,	CLK_PLL1_DIV2,	2, 1),
+	DEF_FIXED(".s0_hsc",	CLK_S0_HSC,	CLK_PLL1_DIV2,	2, 1),
+	DEF_FIXED(".sv_vip",	CLK_SV_VIP,	CLK_PLL1_DIV2,	2, 1),
+	DEF_FIXED(".sv_ir",	CLK_SV_IR,	CLK_PLL1_DIV2,	2, 1),
+	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
+	DEF_RATE(".oco",	CLK_OCO,	32768),
+
+	DEF_BASE(".rpcsrc",	CLK_RPCSRC,		CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+	DEF_BASE(".rpc",	R8A779G0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+	DEF_BASE("rpcd2",	R8A779G0_CLK_RPCD2,	CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
+	DEF_FIXED(".vio",	CLK_VIOBUS,	CLK_PLL5_DIV2,	3, 1),
+	DEF_FIXED(".vc",	CLK_VCBUS,	CLK_PLL5_DIV2,	3, 1),
+
+	/* Core Clock Outputs */
+	DEF_FIXED("s0d2",	R8A779G0_CLK_S0D2,	CLK_S0,		2, 1),
+	DEF_FIXED("s0d3",	R8A779G0_CLK_S0D3,	CLK_S0,		3, 1),
+	DEF_FIXED("s0d4",	R8A779G0_CLK_S0D4,	CLK_S0,		4, 1),
+	DEF_FIXED("cl16m",	R8A779G0_CLK_CL16M,	CLK_S0,		48, 1),
+	DEF_FIXED("s0d1_vio",	R8A779G0_CLK_S0D1_VIO,	CLK_S0_VIO,	1, 1),
+	DEF_FIXED("s0d2_vio",	R8A779G0_CLK_S0D2_VIO,	CLK_S0_VIO,	2, 1),
+	DEF_FIXED("s0d4_vio",	R8A779G0_CLK_S0D4_VIO,	CLK_S0_VIO,	4, 1),
+	DEF_FIXED("s0d8_vio",	R8A779G0_CLK_S0D8_VIO,	CLK_S0_VIO,	8, 1),
+	DEF_FIXED("s0d1_vc",	R8A779G0_CLK_S0D1_VC,	CLK_S0_VC,	1, 1),
+	DEF_FIXED("s0d2_vc",	R8A779G0_CLK_S0D2_VC,	CLK_S0_VC,	2, 1),
+	DEF_FIXED("s0d4_vc",	R8A779G0_CLK_S0D4_VC,	CLK_S0_VC,	4, 1),
+	DEF_FIXED("s0d2_mm",	R8A779G0_CLK_S0D2_MM,	CLK_S0,		2, 1),
+	DEF_FIXED("s0d4_mm",	R8A779G0_CLK_S0D4_MM,	CLK_S0,		4, 1),
+	DEF_FIXED("cl16m_mm",	R8A779G0_CLK_CL16M_MM,	CLK_S0,		48, 1),
+	DEF_FIXED("s0d2_u3dg",	R8A779G0_CLK_S0D2_U3DG,	CLK_S0,		2, 1),
+	DEF_FIXED("s0d4_u3dg",	R8A779G0_CLK_S0D4_U3DG,	CLK_S0,		4, 1),
+	DEF_FIXED("s0d2_rt",	R8A779G0_CLK_S0D2_RT,	CLK_S0,		2, 1),
+	DEF_FIXED("s0d3_rt",	R8A779G0_CLK_S0D3_RT,	CLK_S0,		3, 1),
+	DEF_FIXED("s0d4_rt",	R8A779G0_CLK_S0D4_RT,	CLK_S0,		4, 1),
+	DEF_FIXED("s0d6_rt",	R8A779G0_CLK_S0D6_RT,	CLK_S0,		6, 1),
+	DEF_FIXED("s0d24_rt",	R8A779G0_CLK_S0D24_RT,	CLK_S0,		24, 1),
+	DEF_FIXED("cl16m_rt",	R8A779G0_CLK_CL16M_RT,	CLK_S0,		48, 1),
+	DEF_FIXED("s0d2_per",	R8A779G0_CLK_S0D2_PER,	CLK_S0,		2, 1),
+	DEF_FIXED("s0d3_per",	R8A779G0_CLK_S0D3_PER,	CLK_S0,		3, 1),
+	DEF_FIXED("s0d6_per",	R8A779G0_CLK_S0D6_PER,	CLK_S0,		6, 1),
+	DEF_FIXED("s0d12_per",	R8A779G0_CLK_S0D12_PER,	CLK_S0,		12, 1),
+	DEF_FIXED("s0d24_per",	R8A779G0_CLK_S0D24_PER,	CLK_S0,		24, 1),
+	DEF_FIXED("cl16m_per",	R8A779G0_CLK_CL16M_PER,	CLK_S0,		48, 1),
+	DEF_FIXED("s0d1_hsc",	R8A779G0_CLK_S0D1_HSC,	CLK_S0_HSC,	1, 1),
+	DEF_FIXED("s0d2_hsc",	R8A779G0_CLK_S0D2_HSC,	CLK_S0_HSC,	2, 1),
+	DEF_FIXED("s0d4_hsc",	R8A779G0_CLK_S0D4_HSC,	CLK_S0_HSC,	4, 1),
+	DEF_FIXED("cl16m_hsc",	R8A779G0_CLK_CL16M_HSC,	CLK_S0_HSC,	48, 1),
+	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),
+	DEF_FIXED("svd1_ir",	R8A779G0_CLK_SVD1_IR,	CLK_SV_IR,	1, 1),
+	DEF_FIXED("svd2_ir",	R8A779G0_CLK_SVD2_IR,	CLK_SV_IR,	2, 1),
+	DEF_FIXED("svd1_vip",	R8A779G0_CLK_SVD1_VIP,	CLK_SV_VIP,	1, 1),
+	DEF_FIXED("svd2_vip",	R8A779G0_CLK_SVD2_VIP,	CLK_SV_VIP,	2, 1),
+	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),
+	DEF_FIXED("cbfusa",	R8A779G0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
+	DEF_FIXED("cpex",	R8A779G0_CLK_CPEX,	CLK_EXTAL,	2, 1),
+	DEF_FIXED("viobusd2",	R8A779G0_CLK_VIOBUSD2,	CLK_VIOBUS,	2, 1),
+	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VCBUS,	2, 1),
+
+	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	CLK_SDSRC,	0x870),
+	DEF_DIV6P1("mso",	R8A779G0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
+
+	DEF_GEN4_OSC("osc",	R8A779G0_CLK_OSC,	CLK_EXTAL,	8),
+	DEF_GEN4_MDSEL("r",	R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
+	DEF_MOD("hscif0",	514,	R8A779G0_CLK_S0D3_PER),
+	DEF_MOD("hscif1",	515,	R8A779G0_CLK_S0D3_PER),
+	DEF_MOD("hscif2",	516,	R8A779G0_CLK_S0D3_PER),
+	DEF_MOD("hscif3",	517,	R8A779G0_CLK_S0D3_PER),
+};
+
+/*
+ * CPG Clock Data
+ */
+/*
+ *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC
+ * 14 13 (MHz)
+ * ----------------------------------------------------------------
+ * 0  0	 16.66 / 1	x192	x204	x192	x144	x192	x168	/8
+ * 0  1	 20    / 1	x160	x170	x160	x120	x160	x140	/8
+ * 1  0	 Prohibited setting
+ * 1  1	 33.33 / 2	x192	x204	x192	x144	x192	x168	/8
+ */
+#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
+					 (((md) & BIT(13)) >> 13))
+
+static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
+	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */
+	{ 1,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	8,	},
+	{ 1,		160,	1,	170,	1,	160,	1,	120,	1,	160,	1,	140,	1,	8,	},
+	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},
+	{ 2,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	8,	},
+};
+
+static int __init r8a779g0_cpg_mssr_init(struct device *dev)
+{
+	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
+	u32 cpg_mode;
+	int error;
+
+	error = rcar_rst_read_mode_pins(&cpg_mode);
+	if (error)
+		return error;
+
+	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+	if (!cpg_pll_config->extal_div) {
+		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
+		return -EINVAL;
+	}
+
+	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
+}
+
+const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r8a779g0_core_clks,
+	.num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r8a779g0_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
+	.num_hw_mod_clks = 30 * 32,
+
+	/* Callbacks */
+	.init = r8a779g0_cpg_mssr_init,
+	.cpg_clk_register = rcar_gen4_cpg_clk_register,
+
+	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 5d2c3edbaa14..1a0cdf001b2f 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -853,6 +853,12 @@ static const struct of_device_id cpg_mssr_match[] = {
 		.compatible = "renesas,r8a779f0-cpg-mssr",
 		.data = &r8a779f0_cpg_mssr_info,
 	},
+#endif
+#ifdef CONFIG_CLK_R8A779G0
+	{
+		.compatible = "renesas,r8a779g0-cpg-mssr",
+		.data = &r8a779g0_cpg_mssr_info,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 16810dd4e6ac..1c3c057d17f5 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -179,6 +179,7 @@ extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
 
 void __init cpg_mssr_early_init(struct device_node *np,
 				const struct cpg_mssr_info *info);
-- 
2.25.1

[PATCH 14/15] arm64: dts: renesas: Add Renesas R8A779G0 SoC support

[Yoshihiro Shimoda]

Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
new file mode 100644
index 000000000000..eb5a9ca837c7
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G0) SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a779g0-sysc.h>
+
+/ {
+	compatible = "renesas,r8a779g0";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		a76_0: cpu@0 {
+			compatible = "arm,cortex-a76";
+			reg = <0>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extalr_clk: extalr {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	pmu_a76 {
+		compatible = "arm,cortex-a76-pmu";
+		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	/* External SCIF clock - to be overridden by boards that provide it */
+	scif_clk: scif {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a779g0-cpg-mssr";
+			reg = <0 0xe6150000 0 0x4000>;
+			clocks = <&extal_clk>, <&extalr_clk>;
+			clock-names = "extal", "extalr";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a779g0-rst";
+			reg = <0 0xe6160000 0 0x4000>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a779g0-sysc";
+			reg = <0 0xe6180000 0 0x4000>;
+			#power-domain-cells = <1>;
+		};
+
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a779g0",
+				     "renesas,rcar-gen4-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 96>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 514>,
+				 <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 514>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1000000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1000000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x110000>;
+			interrupts = <GIC_PPI 9
+				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.25.1

[PATCH 15/15] arm64: dts: renesas: Add Renesas White Hawk boards support

[Yoshihiro Shimoda]

Initial support for the Renesas White Hawk CPU and BreakOut boards.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../dts/renesas/r8a779g0-white-hawk-cpu.dtsi  | 45 +++++++++++++++++++
 .../boot/dts/renesas/r8a779g0-white-hawk.dts  | 22 +++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index fa9811251fd7..15309309a2e1 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
 
 dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
 
+dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
+
 dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
new file mode 100644
index 000000000000..6cc6821fa4da
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the White Hawk CPU board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include "r8a779g0.dtsi"
+
+/ {
+	model = "Renesas White Hawk CPU board";
+	compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+
+	memory@480000000 {
+		device_type = "memory";
+		reg = <0x4 0x80000000 0x0 0x80000000>;
+	};
+
+	memory@600000000 {
+		device_type = "memory";
+		reg = <0x6 0x00000000 0x1 0x00000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&hscif0 {
+	status = "okay";
+};
+
+&scif_clk {
+	clock-frequency = <24000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
new file mode 100644
index 000000000000..d4ed8c4035dd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0 or MIT)
+/*
+ * Device Tree Source for the White Hawk CPU and BreakOut boards
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a779g0-white-hawk-cpu.dtsi"
+
+/ {
+	model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
+	compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
+
+	aliases {
+		serial0 = &hscif0;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+	};
+};
-- 
2.25.1

Re: [PATCH 02/15] dt-bindings: arm: renesas: Document Renesas White Hawk boards

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Add device tree bindings documentation for Renesas R-Car V4H
> White Hawk CPU and BreakOut boards.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  Documentation/devicetree/bindings/arm/renesas.yaml | 8 ++++++++
>  1 file changed, 8 insertions(+)

Squash it with your previous patch, please. Documenting just SoC and
immediately later the board compatibles is too big split.


Best regards,
Krzysztof

Re: [PATCH 03/15] dt-bindings: reset: renesas,rst: Document r8a779g0 reset module

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Document bindings for the R-Car V4H (R8A779G0) reset module.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  Documentation/devicetree/bindings/reset/renesas,rst.yaml | 1 +
>  1 file changed, 1 insertion(+)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 04/15] dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Document bindings for the R-Car V4H (aka R8A779G0) SYSC block.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 05/15] dt-bindings: power: Add r8a779g0 SYSC power domain definitions

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Add power domain indices for R-Car V4H (r8a779g0).

Are these values used by renesas,rcar-sysc (r8a779g0) - patch 4? If yes,
maybe just squash it?

In any case:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 06/15] dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse
> Generator.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> R-Car V4H (R8A779G0) SoC.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 87 +++++++++++++++++++
>  1 file changed, 87 insertions(+)
>  create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> 
> diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> new file mode 100644
> index 000000000000..07a94cf45581
> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */

Any reason why not licensing it the same as bindings document
(GPL-2.0-only OR BSD-2-Clause)? The same applies to patch 5.

MIT and BSD-2-clause are almost the same, AFAIR, so let's stick to one
(BSD-2-clause) for consistency?


Best regards,
Krzysztof

Re: [PATCH 08/15] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
> so document the SoC specific bindings.
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 14/15] arm64: dts: renesas: Add Renesas R8A779G0 SoC support

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++++++++++++++
>  1 file changed, 122 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> new file mode 100644
> index 000000000000..eb5a9ca837c7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0 or MIT)
> +/*
> + * Device Tree Source for the R-Car V4H (R8A779G0) SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/r8a779g0-sysc.h>
> +
> +/ {
> +	compatible = "renesas,r8a779g0";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		a76_0: cpu@0 {
> +			compatible = "arm,cortex-a76";
> +			reg = <0>;
> +			device_type = "cpu";
> +			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
> +		};
> +	};
> +
> +	extal_clk: extal {

Generic node names. If you need some differentiating prefix, how about
"extal-clock"?

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	extalr_clk: extalr {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	pmu_a76 {

No underscores in node names.

> +		compatible = "arm,cortex-a76-pmu";
> +		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	/* External SCIF clock - to be overridden by boards that provide it */
> +	scif_clk: scif {

Generic node names, so scif-clock?

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: dts: renesas: Add Renesas White Hawk boards support

[Krzysztof Kozlowski]

On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> Initial support for the Renesas White Hawk CPU and BreakOut boards.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/Makefile          |  2 +
>  .../dts/renesas/r8a779g0-white-hawk-cpu.dtsi  | 45 +++++++++++++++++++
>  .../boot/dts/renesas/r8a779g0-white-hawk.dts  | 22 +++++++++
>  3 files changed, 69 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
>  create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 05/15] dt-bindings: power: Add r8a779g0 SYSC power domain definitions

[Geert Uytterhoeven]

Hi Krzysztof,

On Thu, Apr 21, 2022 at 9:44 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
> On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> > Add power domain indices for R-Car V4H (r8a779g0).
>
> Are these values used by renesas,rcar-sysc (r8a779g0) - patch 4? If yes,
> maybe just squash it?

They are used by driver and DT sources, so we typically keep this as
a separate patch, to be queued on a branch shared by driver and DT.

> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/15] dt-bindings: power: Add r8a779g0 SYSC power domain definitions

[Krzysztof Kozlowski]

On 21/04/2022 10:07, Geert Uytterhoeven wrote:
> Hi Krzysztof,
> 
> On Thu, Apr 21, 2022 at 9:44 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>> On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
>>> Add power domain indices for R-Car V4H (r8a779g0).
>>
>> Are these values used by renesas,rcar-sysc (r8a779g0) - patch 4? If yes,
>> maybe just squash it?
> 
> They are used by driver and DT sources, so we typically keep this as
> a separate patch, to be queued on a branch shared by driver and DT.

True, sounds good.

Best regards,
Krzysztof

Re: [PATCH 01/15] dt-bindings: arm: renesas: Document R-Car V4H SoC DT bindings

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add device tree bindings documentation for Renesas R-Car V4H
> (r8a779f0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/15] dt-bindings: arm: renesas: Document Renesas White Hawk boards

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add device tree bindings documentation for Renesas R-Car V4H
> White Hawk CPU and BreakOut boards.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19, squashed with PATCH 01/15,
as requested by Krzysztof.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 03/15] dt-bindings: reset: renesas,rst: Document r8a779g0 reset module

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Document bindings for the R-Car V4H (R8A779G0) reset module.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/15] dt-bindings: power: renesas,rcar-sysc: Document r8a779g0 SYSC bindings

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Document bindings for the R-Car V4H (aka R8A779G0) SYSC block.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/15] dt-bindings: power: Add r8a779g0 SYSC power domain definitions

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add power domain indices for R-Car V4H (r8a779g0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue for v5.19 a branch shared by driver and DT.


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/15] dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse
> Generator.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 08/15] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
> +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* r8a779g0 CPG Core Clocks */
> +
> +#define R8A779G0_CLK_ZX                        0
> +#define R8A779G0_CLK_ZS                        1
> +#define R8A779G0_CLK_ZT                        2
> +#define R8A779G0_CLK_ZTR               3
> +#define R8A779G0_CLK_S0D2              4
> +#define R8A779G0_CLK_S0D3              5
> +#define R8A779G0_CLK_S0D4              6
> +#define R8A779G0_CLK_S0D1_VIO          7
> +#define R8A779G0_CLK_S0D2_VIO          8
> +#define R8A779G0_CLK_S0D4_VIO          9
> +#define R8A779G0_CLK_S0D8_VIO          10
> +#define R8A779G0_CLK_S0D1_VC           11
> +#define R8A779G0_CLK_S0D2_VC           12
> +#define R8A779G0_CLK_S0D4_VC           13
> +#define R8A779G0_CLK_S0D2_MM           14
> +#define R8A779G0_CLK_S0D4_MM           15
> +#define R8A779G0_CLK_S0D2_U3DG         16
> +#define R8A779G0_CLK_S0D4_U3DG         17
> +#define R8A779G0_CLK_S0D2_RT           18
> +#define R8A779G0_CLK_S0D3_RT           19
> +#define R8A779G0_CLK_S0D4_RT           20
> +#define R8A779G0_CLK_S0D6_RT           21
> +#define R8A779G0_CLK_S0D24_RT          22
> +#define R8A779G0_CLK_S0D2_PER          23
> +#define R8A779G0_CLK_S0D3_PER          24

Missing S0D4_PER?

> +#define R8A779G0_CLK_S0D6_PER          25
> +#define R8A779G0_CLK_S0D12_PER         26
> +#define R8A779G0_CLK_S0D24_PER         27
> +#define R8A779G0_CLK_S0D1_HSC          28
> +#define R8A779G0_CLK_S0D2_HSC          29
> +#define R8A779G0_CLK_S0D4_HSC          30
> +#define R8A779G0_CLK_S0D2_CC           31
> +#define R8A779G0_CLK_SVD1_IR           32
> +#define R8A779G0_CLK_SVD2_IR           33

Missing IMPA0?
Or is it internal-only? Perhaps the same for IMPA1 below?

> +#define R8A779G0_CLK_SVD1_VIP          34
> +#define R8A779G0_CLK_SVD2_VIP          35
> +#define R8A779G0_CLK_CL                        36
> +#define R8A779G0_CLK_CL16M             37
> +#define R8A779G0_CLK_CL16M_MM          38
> +#define R8A779G0_CLK_CL16M_RT          39
> +#define R8A779G0_CLK_CL16M_PER         40
> +#define R8A779G0_CLK_CL16M_HSC         41
> +#define R8A779G0_CLK_Z0                        42
> +#define R8A779G0_CLK_ZB3               43
> +#define R8A779G0_CLK_ZB3D2             44
> +#define R8A779G0_CLK_ZB3D4             45
> +#define R8A779G0_CLK_ZG                        46
> +#define R8A779G0_CLK_SD0H              47
> +#define R8A779G0_CLK_SD0               48
> +#define R8A779G0_CLK_RPC               49
> +#define R8A779G0_CLK_RPCD2             50
> +#define R8A779G0_CLK_MSO               51
> +#define R8A779G0_CLK_CANFD             52
> +#define R8A779G0_CLK_CSI               53
> +#define R8A779G0_CLK_FRAY              54
> +#define R8A779G0_CLK_IPC               55
> +#define R8A779G0_CLK_SASYNCRT          56
> +#define R8A779G0_CLK_SASYNCPERD1       57
> +#define R8A779G0_CLK_SASYNCPERD2       58
> +#define R8A779G0_CLK_SASYNCPERD4       59

Missing VIOBUS? You do have it as an internal core clock.

> +#define R8A779G0_CLK_VIOBUSD2          60

Missing VCBUS? You do have it as an internal core clock.

> +#define R8A779G0_CLK_VCBUSD2           61
> +#define R8A779G0_CLK_IMPA1             62
> +#define R8A779G0_CLK_DSIEXT            63
> +#define R8A779G0_CLK_DSIREF            64
> +#define R8A779G0_CLK_ADGH              65
> +#define R8A779G0_CLK_OSC               66
> +#define R8A779G0_CLK_ZR0               67
> +#define R8A779G0_CLK_ZR1               68
> +#define R8A779G0_CLK_ZR2               69

Missing IMPA?
Figure 8.1.1 (Block Diagram of CPG) indicates it's a direct
input to the IMP block, hence not an internal core clock.

> +#define R8A779G0_CLK_IMPAD4            70
> +#define R8A779G0_CLK_CPEX              71
> +#define R8A779G0_CLK_CBFUSA            72
> +#define R8A779G0_CLK_R                 73
> +
> +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 09/15] soc: renesas: r8a779g0-sysc: Add r8a779g0 support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for R-Car V4H (R8A779G0) SoC power areas and register
> access.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -369,6 +369,10 @@ config SYSC_R8A779F0
>         bool "System Controller support for R-Car S4-8" if COMPILE_TEST
>         select SYSC_RCAR_GEN4
>
> +config SYSC_R8A779G0
> +       bool "System Controller support for R-Car V4H" if COMPILE_TEST
> +       select SYSC_RCAR_GEN4

Please insert below SYSC_R8A779A0, to preserve alphabetical
order (by description).

> +
>  config SYSC_R8A7792
>         bool "System Controller support for R-Car V2H" if COMPILE_TEST
>         select SYSC_RCAR

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 10/15] soc: renesas: Identify R-Car V4H

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for identifying the R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -247,6 +247,13 @@ config ARCH_R8A779F0
>         help
>           This enables support for the Renesas R-Car S4-8 SoC.
>
> +config ARCH_R8A779G0
> +       bool "ARM64 Platform support for R-Car V4H"
> +       select ARCH_RCAR_GEN3
> +       select SYSC_R8A779G0
> +       help
> +         This enables support for the Renesas R-Car V4H SoC.
> +

Please insert below ARCH_R8A779A0, to preserve alphabetical
order (by description).

>  config ARCH_R8A77980
>         bool "ARM64 Platform support for R-Car V3H"
>         select ARCH_RCAR_GEN3

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/15] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4

[Geert Uytterhoeven]

Hi Shimoda-san,

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for your patch!

> ---
>  drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +++++++++---------
>  drivers/clk/renesas/rcar-gen4-cpg.c     |  5 +++++
>  drivers/clk/renesas/rcar-gen4-cpg.h     |  3 +++
>  3 files changed, 17 insertions(+), 9 deletions(-)

You forgot to update drivers/clk/renesas/r8a779a0-cpg-mssr.c.
Hence all clocks derived from PLL5 have a zero rate, causing the
SDHI driver to enter an infinite loop in renesas_sdhi_set_clock()
(clock = 0):

        for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
                clock <<= 1;

Adding the missing PLL4 mul/div columns fixes that.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/15] soc: renesas: rcar-rst: Add support for R-Car V4H

[Geert Uytterhoeven]

On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add support for R-Car V4H (R8A779G0) to the R-Car RST driver.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Hello Krzysztof,

> From: Krzysztof Kozlowski, Sent: Thursday, April 21, 2022 4:49 PM
> 
> On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> > Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> > R-Car V4H (R8A779G0) SoC.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> >  include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 87 +++++++++++++++++++
> >  1 file changed, 87 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> >
> > diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> > new file mode 100644
> > index 000000000000..07a94cf45581
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> > @@ -0,0 +1,87 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
> 
> Any reason why not licensing it the same as bindings document
> (GPL-2.0-only OR BSD-2-Clause)? The same applies to patch 5.
> 
> MIT and BSD-2-clause are almost the same, AFAIR, so let's stick to one
> (BSD-2-clause) for consistency?

Since r8a779g0.dtsi (which uses this) is under (GPL-2.0 or MIT), I use it here.
Also, r8a779g0.dtsi includes dt-bindings/interrupt-controller/arm-gic.h and
the arm-gic.h is under (GPL-2.0 or MIT). So, using it is better, IIUC.
In other words, r8a779g0.dtsi doesn't include any the bindings document
so that there is not needed to use the same license, I think.
# I'm not a lawyer though...

Best regards,
Yoshihiro Shimoda

> 
> Best regards,
> Krzysztof

RE: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Thursday, April 21, 2022 7:19 PM
> 
> Hi Shimoda-san,
> 
> On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> > R-Car V4H (R8A779G0) SoC.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> > @@ -0,0 +1,87 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
> > +/*
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
> > +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* r8a779g0 CPG Core Clocks */
> > +
> > +#define R8A779G0_CLK_ZX                        0
> > +#define R8A779G0_CLK_ZS                        1
> > +#define R8A779G0_CLK_ZT                        2
> > +#define R8A779G0_CLK_ZTR               3
> > +#define R8A779G0_CLK_S0D2              4
> > +#define R8A779G0_CLK_S0D3              5
> > +#define R8A779G0_CLK_S0D4              6
> > +#define R8A779G0_CLK_S0D1_VIO          7
> > +#define R8A779G0_CLK_S0D2_VIO          8
> > +#define R8A779G0_CLK_S0D4_VIO          9
> > +#define R8A779G0_CLK_S0D8_VIO          10
> > +#define R8A779G0_CLK_S0D1_VC           11
> > +#define R8A779G0_CLK_S0D2_VC           12
> > +#define R8A779G0_CLK_S0D4_VC           13
> > +#define R8A779G0_CLK_S0D2_MM           14
> > +#define R8A779G0_CLK_S0D4_MM           15
> > +#define R8A779G0_CLK_S0D2_U3DG         16
> > +#define R8A779G0_CLK_S0D4_U3DG         17
> > +#define R8A779G0_CLK_S0D2_RT           18
> > +#define R8A779G0_CLK_S0D3_RT           19
> > +#define R8A779G0_CLK_S0D4_RT           20
> > +#define R8A779G0_CLK_S0D6_RT           21
> > +#define R8A779G0_CLK_S0D24_RT          22
> > +#define R8A779G0_CLK_S0D2_PER          23
> > +#define R8A779G0_CLK_S0D3_PER          24
> 
> Missing S0D4_PER?

Oops. I'll add it.

> > +#define R8A779G0_CLK_S0D6_PER          25
> > +#define R8A779G0_CLK_S0D12_PER         26
> > +#define R8A779G0_CLK_S0D24_PER         27
> > +#define R8A779G0_CLK_S0D1_HSC          28
> > +#define R8A779G0_CLK_S0D2_HSC          29
> > +#define R8A779G0_CLK_S0D4_HSC          30
> > +#define R8A779G0_CLK_S0D2_CC           31
> > +#define R8A779G0_CLK_SVD1_IR           32
> > +#define R8A779G0_CLK_SVD2_IR           33
> 
> Missing IMPA0?
> Or is it internal-only? Perhaps the same for IMPA1 below?

IIUC, IMPA[01] are internal-only.

> > +#define R8A779G0_CLK_SVD1_VIP          34
> > +#define R8A779G0_CLK_SVD2_VIP          35
> > +#define R8A779G0_CLK_CL                        36
> > +#define R8A779G0_CLK_CL16M             37
> > +#define R8A779G0_CLK_CL16M_MM          38
> > +#define R8A779G0_CLK_CL16M_RT          39
> > +#define R8A779G0_CLK_CL16M_PER         40
> > +#define R8A779G0_CLK_CL16M_HSC         41
> > +#define R8A779G0_CLK_Z0                        42
> > +#define R8A779G0_CLK_ZB3               43
> > +#define R8A779G0_CLK_ZB3D2             44
> > +#define R8A779G0_CLK_ZB3D4             45
> > +#define R8A779G0_CLK_ZG                        46
> > +#define R8A779G0_CLK_SD0H              47
> > +#define R8A779G0_CLK_SD0               48
> > +#define R8A779G0_CLK_RPC               49
> > +#define R8A779G0_CLK_RPCD2             50
> > +#define R8A779G0_CLK_MSO               51
> > +#define R8A779G0_CLK_CANFD             52
> > +#define R8A779G0_CLK_CSI               53
> > +#define R8A779G0_CLK_FRAY              54
> > +#define R8A779G0_CLK_IPC               55
> > +#define R8A779G0_CLK_SASYNCRT          56
> > +#define R8A779G0_CLK_SASYNCPERD1       57
> > +#define R8A779G0_CLK_SASYNCPERD2       58
> > +#define R8A779G0_CLK_SASYNCPERD4       59
> 
> Missing VIOBUS? You do have it as an internal core clock.

Thank you.
I misunderstood that VIOBUS is an internal core clock.
The VIO is internal core clock, but VIOBUS is not an internal core clock.
I'll add VIOBUS here.

> > +#define R8A779G0_CLK_VIOBUSD2          60
> 
> Missing VCBUS? You do have it as an internal core clock.

Correct. I'll add VCBUS here.

> > +#define R8A779G0_CLK_VCBUSD2           61
> > +#define R8A779G0_CLK_IMPA1             62
> > +#define R8A779G0_CLK_DSIEXT            63
> > +#define R8A779G0_CLK_DSIREF            64
> > +#define R8A779G0_CLK_ADGH              65
> > +#define R8A779G0_CLK_OSC               66
> > +#define R8A779G0_CLK_ZR0               67
> > +#define R8A779G0_CLK_ZR1               68
> > +#define R8A779G0_CLK_ZR2               69
> 
> Missing IMPA?
> Figure 8.1.1 (Block Diagram of CPG) indicates it's a direct
> input to the IMP block, hence not an internal core clock.

You're correct. I'll add IMPA here.

Best regards,
Yoshihiro Shimoda

> > +#define R8A779G0_CLK_IMPAD4            70
> > +#define R8A779G0_CLK_CPEX              71
> > +#define R8A779G0_CLK_CBFUSA            72
> > +#define R8A779G0_CLK_R                 73
> > +
> > +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

RE: [PATCH 12/15] clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4

[Yoshihiro Shimoda]

Hi Geert-san,

Thank you for your review!

> From: Geert Uytterhoeven, Sent: Thursday, April 21, 2022 10:48 PM
> 
> Hi Shimoda-san,
> 
> On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for your patch!
> 
> > ---
> >  drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +++++++++---------
> >  drivers/clk/renesas/rcar-gen4-cpg.c     |  5 +++++
> >  drivers/clk/renesas/rcar-gen4-cpg.h     |  3 +++
> >  3 files changed, 17 insertions(+), 9 deletions(-)
> 
> You forgot to update drivers/clk/renesas/r8a779a0-cpg-mssr.c.

I completely forgot it. I'll fix it.

> Hence all clocks derived from PLL5 have a zero rate, causing the
> SDHI driver to enter an infinite loop in renesas_sdhi_set_clock()
> (clock = 0):
> 
>         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
>                 clock <<= 1;
> 
> Adding the missing PLL4 mul/div columns fixes that.

I got it.

> The rest LGTM.

Thank you for your review!

Best regards,
Yoshihiro Shimoda

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Geert Uytterhoeven]

Hi Shimoda-san,

On Fri, Apr 22, 2022 at 7:40 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Thursday, April 21, 2022 7:19 PM
> > On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> > > R-Car V4H (R8A779G0) SoC.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h

> > Missing IMPA0?
> > Or is it internal-only? Perhaps the same for IMPA1 below?
>
> IIUC, IMPA[01] are internal-only.

OK.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Krzysztof Kozlowski]

On 22/04/2022 07:32, Yoshihiro Shimoda wrote:
> Hello Krzysztof,
> 
>> From: Krzysztof Kozlowski, Sent: Thursday, April 21, 2022 4:49 PM
>>
>> On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
>>> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
>>> R-Car V4H (R8A779G0) SoC.
>>>
>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>>> ---
>>>  include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 87 +++++++++++++++++++
>>>  1 file changed, 87 insertions(+)
>>>  create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
>>>
>>> diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
>>> new file mode 100644
>>> index 000000000000..07a94cf45581
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
>>> @@ -0,0 +1,87 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
>>
>> Any reason why not licensing it the same as bindings document
>> (GPL-2.0-only OR BSD-2-Clause)? The same applies to patch 5.
>>
>> MIT and BSD-2-clause are almost the same, AFAIR, so let's stick to one
>> (BSD-2-clause) for consistency?
> 
> Since r8a779g0.dtsi (which uses this) is under (GPL-2.0 or MIT), I use it here.
> Also, r8a779g0.dtsi includes dt-bindings/interrupt-controller/arm-gic.h and
> the arm-gic.h is under (GPL-2.0 or MIT). So, using it is better, IIUC.

This would mean we want to license the bindings the same as we license
the DTS. It's not the case. For the bindings we have the strong
preference - GPL-2.0 or BSD-2-clause. For the DTS - not that much, just
recommendation, I think.

> In other words, r8a779g0.dtsi doesn't include any the bindings document
> so that there is not needed to use the same license, I think.
> # I'm not a lawyer though...

If you would like to follow your recommendation, you should license also
schema as MIT, because your DTS uses it as well (as a derivative work).

Anyway MIT and BSD-2-c are very similar, so there is no much difference
here.


Best regards,
Krzysztof

Re: [PATCH 08/15] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings

[Geert Uytterhoeven]

Hi Shimoda-san,

On Thu, Apr 21, 2022 at 11:45 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
> > so document the SoC specific bindings.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Sorry, I spoke too soon.

"renesas,rcar-gen4-hscif" should be added to the conditional
section making "resets" a required property.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 07/15] dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions

[Yoshihiro Shimoda]

Hello Krzysztof,

> From: Krzysztof Kozlowski, Sent: Friday, April 22, 2022 4:17 PM
> 
> On 22/04/2022 07:32, Yoshihiro Shimoda wrote:
> > Hello Krzysztof,
> >
> >> From: Krzysztof Kozlowski, Sent: Thursday, April 21, 2022 4:49 PM
> >>
> >> On 20/04/2022 10:42, Yoshihiro Shimoda wrote:
> >>> Add all Clock Pulse Generator Core Clock Outputs for the Renesas
> >>> R-Car V4H (R8A779G0) SoC.
> >>>
> >>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >>> ---
> >>>  include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 87 +++++++++++++++++++
> >>>  1 file changed, 87 insertions(+)
> >>>  create mode 100644 include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> >>>
> >>> diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> >>> new file mode 100644
> >>> index 000000000000..07a94cf45581
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
> >>> @@ -0,0 +1,87 @@
> >>> +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
> >>
> >> Any reason why not licensing it the same as bindings document
> >> (GPL-2.0-only OR BSD-2-Clause)? The same applies to patch 5.
> >>
> >> MIT and BSD-2-clause are almost the same, AFAIR, so let's stick to one
> >> (BSD-2-clause) for consistency?
> >
> > Since r8a779g0.dtsi (which uses this) is under (GPL-2.0 or MIT), I use it here.
> > Also, r8a779g0.dtsi includes dt-bindings/interrupt-controller/arm-gic.h and
> > the arm-gic.h is under (GPL-2.0 or MIT). So, using it is better, IIUC.
> 
> This would mean we want to license the bindings the same as we license
> the DTS. It's not the case. For the bindings we have the strong
> preference - GPL-2.0 or BSD-2-clause. For the DTS - not that much, just
> recommendation, I think.

Thank you very much for your comments. Now I understand the files in include/dt-bindings/
are also the bindings.

> > In other words, r8a779g0.dtsi doesn't include any the bindings document
> > so that there is not needed to use the same license, I think.
> > # I'm not a lawyer though...
> 
> If you would like to follow your recommendation, you should license also
> schema as MIT, because your DTS uses it as well (as a derivative work).
> 
> Anyway MIT and BSD-2-c are very similar, so there is no much difference
> here.

I got it. So, I'll change the license from (GPL-2.0 or MIT) to (GPL-2.0-only OR BSD-2-Clause).

Best regards,
Yoshihiro Shimoda

RE: [PATCH 08/15] dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Friday, April 22, 2022 9:36 PM
> 
> Hi Shimoda-san,
> 
> On Thu, Apr 21, 2022 at 11:45 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports,
> > > so document the SoC specific bindings.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Sorry, I spoke too soon.
> 
> "renesas,rcar-gen4-hscif" should be added to the conditional
> section making "resets" a required property.

Thank you for your review! I'll fix it.

Best regards,
Yoshihiro Shimoda