From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C58E1C433EF for ; Thu, 21 Apr 2022 09:53:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232770AbiDUJ4o (ORCPT ); Thu, 21 Apr 2022 05:56:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387938AbiDUJ4e (ORCPT ); Thu, 21 Apr 2022 05:56:34 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CC1327B23; Thu, 21 Apr 2022 02:53:44 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id C65DC1BF20B; Thu, 21 Apr 2022 09:53:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1650534823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=InYlcnp2sDm4ChkUXG4xyc4b9OP+smT4t/tQR4FHwzw=; b=Z7D89EGYq5UaBvNABnqVVz/3P5bnCB5YtczX9uRbsakgOWGLQ1kmKUZ/yBpUaJMzLBmVse fabCk1gwdKMzVXkb5IuG+kBVyhnND5aqWRW9TJeurebg6P6M4D73rdKRGrpbc8ls90bhdD oUG1Cs8k2h8BTADOQcVYMBuPqOIQqG4WbH8ny9AFZmYRx2cjAajxMX4U6hMafNybPpawXz Sg00uaivp1Re5BJQRyE3ixdWVLvrP02gGCwPGrAmy10AMdVdYLHvA+hT5MPsWWZtr1VZba 2Nd1/+6JZbc+R9pf5w8el4xOKQDQ5Xzy/EYoPZkZcqGC5tre8EjFl+CbOl5cgQ== From: Miquel Raynal To: Geert Uytterhoeven , Magnus Damm , Greg Kroah-Hartman , Jiri Slaby Cc: Miquel Raynal , Andy Shevchenko , linux-renesas-soc@vger.kernel.org, linux-serial@vger.kernel.org, Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Ilpo Jarvinen , Phil Edworthy Subject: [PATCH v6 09/12] serial: 8250: dw: Improve RZN1 support Date: Thu, 21 Apr 2022 11:53:20 +0200 Message-Id: <20220421095323.101811-10-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220421095323.101811-1-miquel.raynal@bootlin.com> References: <20220421095323.101811-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Phil Edworthy Renesas RZ/N1 SoC features a slightly modified DW UART. On this SoC, the CPR register value is known but not synthetized in hardware. We hence need to provide a CPR value in the platform data. This version of the controller also relies on acting as flow controller when using DMA, so we need to provide the "is dma flow controller" quirk. Signed-off-by: Phil Edworthy Co-developed-by: Miquel Raynal Signed-off-by: Miquel Raynal Reviewed-by: Andy Shevchenko --- drivers/tty/serial/8250/8250_dw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 90e64c8bd4bf..0cf1a99dc124 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -761,6 +761,8 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { .usr_reg = DW_UART_USR, + .cpr_val = 0x00012f32, + .quirks = DW_UART_QUIRK_IS_DMA_FC, }; static const struct dw8250_platform_data dw8250_starfive_jh7100_data = { -- 2.27.0