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* [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support
@ 2022-04-21  9:53 Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 01/12] serial: 8250: dw: Move definitions to the shared header Miquel Raynal
                   ` (11 more replies)
  0 siblings, 12 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

Hello,

Support for the RZN1 DMA engine allows us adapt a little bit the 8250 DW
UART driver with to bring DMA support for this SoC.

This short series applies on top of the series bringing RZN1 DMA
support, currently on its v11, see [1]. Technically speaking, only the DT
patch needs to be applied after [1]. The other patches can come in at
any moment, because if no "dmas" property is provided in the DT, DMA
support will simply be ignored.

[1] https://lore.kernel.org/dmaengine/20220421085112.78858-1-miquel.raynal@bootlin.com/T/#t

Thanks,
Miquèl

Changes in v6:
* Collected more tags.
* Moved some RZN1 definitions below to respect the increasing order of
  the register offsets.
* Renamed the cpr platdata entry to cpr_val.
* Moved the cpr/cpr_val platdata entry closer to usr_reg.
* Dropped the patch from Emil Renner Berthing adding jh7100 support from
  my tree. Squashed the other patch from this external series with the
  fixes which applied on top of it and were supposed to bring platform
  data support.
* Rebased on top of tty-next.

Changes in v5:
* Collected the various tags.
* Updated the style to fit Andy's requests.
* Moved the usr register offset to pdata as advised by Andy.
* Moved the addition of the property.h header to the right patch.
* Return earlier from the IRQ handler whenever possible.
* Moved the dw8250_readl/writel_ext() helpers to dwlib.h so that they
  could be reused by the patch adding rzn1 support.

Changes in v4:
* Squashed the patch changing the quirks type with the patch introducing
  the pdata structure. This way I don't need to go through the uintptr_t
  step. 
* Added a pdata stub to the DW compatible. This way "if (pdata)" checks
  are no longer needed and we can avoid ternary operators disliked by
  Greg.
* Saved the pdata structure pointer inside the per-device structure to
  avoid calling the same device property heplper over and over again. 
* Changed the style a bit to fit Andy's requirements.

Changes in v3:
* Added Geert's Reviewed-by's.
* Used forward declaration in dwlib.h when relevant.
* Reordered the headers when necessary.
* Added a patch changing the quirks type from unsigned long to unsigned
  int as advised by Andy.
* s/up->port.dev/p->dev/ when relevant.
* Added a debug message in dwlib when no CPR is available.
* Dropped the CPR_DMA_EXTRA bit addition: we assume DMA is there.
* Changed the prefix of certain definitions.

Changes in v2:
* Rebased on top of Emil's patches. Added platform data structures
  instead of raw quirk integers in order to provide a CPR value.
* Added includes in dwlib.h even though it's not particularly useful, it
  may help preventing a build error later on if we ever decide to include
  this file from another location.
* Dropped the call to ->tx_dma and instead implemented a callback that
  can be called from serial8250_tx/rx_dma.
* Used the device API instead of the of API.
* Changed the logic about DMA capabilities to avoid breaking existing
  designs.
* Introduced a new quirk related to the flow-control feature of the
  RZ/N1 version of the UART controller when used with DMA.
* Re-arranged the entire series as advised by Andy and Geert.
* Added several preparation patches to ease the review of various
  functional changes.

Emil Renner Berthing (1):
  serial: 8250: dw: Create a generic platform data structure

Miquel Raynal (8):
  serial: 8250: dw: Move the USR register to pdata
  serial: 8250: dw: Allow to use a fallback CPR value if not synthesized
  serial: 8250: dma: Allow driver operations before starting DMA
    transfers
  serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path
  serial: 8250: dw: Move the IO accessors to 8250_dwlib.h
  ARM: dts: r9a06g032: Fill the UART DMA properties
  bestla: Enable DMA, UART3 and UART4
  bestla: Add support for RZN1 dmamux

Phil Edworthy (3):
  serial: 8250: dw: Move definitions to the shared header
  serial: 8250: dw: Add support for DMA flow controlling devices
  serial: 8250: dw: Improve RZN1 support

 .../boot/dts/r9a06g032-rzn1d400-bestla.dts    |  35 +++++
 arch/arm/boot/dts/r9a06g032.dtsi              |  15 ++
 arch/arm/configs/bestla_defconfig             |   2 +-
 drivers/tty/serial/8250/8250.h                |  18 +++
 drivers/tty/serial/8250/8250_dma.c            |   4 +
 drivers/tty/serial/8250/8250_dw.c             | 139 ++++++++++++++----
 drivers/tty/serial/8250/8250_dwlib.c          |  26 +---
 drivers/tty/serial/8250/8250_dwlib.h          |  48 ++++++
 8 files changed, 236 insertions(+), 51 deletions(-)

-- 
2.27.0


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v6 01/12] serial: 8250: dw: Move definitions to the shared header
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 02/12] serial: 8250: dw: Create a generic platform data structure Miquel Raynal
                   ` (10 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen,
	Phil Edworthy

From: Phil Edworthy <phil.edworthy@renesas.com>

Move the per-device structure and a helper out of the main .c file, into
a shared header as they will both be reused from another .c file.

There is no functional change.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[miquel.raynal@bootlin.com: Extracted from a bigger change]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c    | 21 ---------------------
 drivers/tty/serial/8250/8250_dwlib.h | 26 ++++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 1769808031c5..dcbe54ccd16b 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -37,27 +37,6 @@
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE		BIT(6)
 
-struct dw8250_data {
-	struct dw8250_port_data	data;
-
-	u8			usr_reg;
-	int			msr_mask_on;
-	int			msr_mask_off;
-	struct clk		*clk;
-	struct clk		*pclk;
-	struct notifier_block	clk_notifier;
-	struct work_struct	clk_work;
-	struct reset_control	*rst;
-
-	unsigned int		skip_autocfg:1;
-	unsigned int		uart_16550_compatible:1;
-};
-
-static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
-{
-	return container_of(data, struct dw8250_data, data);
-}
-
 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 {
 	return container_of(nb, struct dw8250_data, clk_notifier);
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 83d528e5cc21..72e7dbcccad0 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -1,10 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Synopsys DesignWare 8250 library header file. */
 
+#include <linux/notifier.h>
 #include <linux/types.h>
+#include <linux/workqueue.h>
 
 #include "8250.h"
 
+struct clk;
+struct reset_control;
+
 struct dw8250_port_data {
 	/* Port properties */
 	int			line;
@@ -16,5 +21,26 @@ struct dw8250_port_data {
 	u8			dlf_size;
 };
 
+struct dw8250_data {
+	struct dw8250_port_data	data;
+
+	u8			usr_reg;
+	int			msr_mask_on;
+	int			msr_mask_off;
+	struct clk		*clk;
+	struct clk		*pclk;
+	struct notifier_block	clk_notifier;
+	struct work_struct	clk_work;
+	struct reset_control	*rst;
+
+	unsigned int		skip_autocfg:1;
+	unsigned int		uart_16550_compatible:1;
+};
+
 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
 void dw8250_setup_port(struct uart_port *p);
+
+static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
+{
+	return container_of(data, struct dw8250_data, data);
+}
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 02/12] serial: 8250: dw: Create a generic platform data structure
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 01/12] serial: 8250: dw: Move definitions to the shared header Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 03/12] serial: 8250: dw: Move the USR register to pdata Miquel Raynal
                   ` (9 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen,
	Emil Renner Berthing

From: Emil Renner Berthing <kernel@esmil.dk>

Use device tree match data rather than multiple calls to
of_device_is_compatible() by introducing a platform data structure and
adding a quirks mask.

Provide a stub to the compatibles without quirks to simplify the
handling of the upcoming changes.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
[<miquel.raynal@bootlin.com: Minor changes + creation of a real pdata structure]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c    | 42 ++++++++++++++++++++++------
 drivers/tty/serial/8250/8250_dwlib.h |  5 ++++
 2 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index dcbe54ccd16b..7fdb2683f534 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/workqueue.h>
 #include <linux/notifier.h>
 #include <linux/slab.h>
@@ -37,6 +38,11 @@
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE		BIT(6)
 
+/* Quirks */
+#define DW_UART_QUIRK_OCTEON		BIT(0)
+#define DW_UART_QUIRK_ARMADA_38X	BIT(1)
+#define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
+
 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 {
 	return container_of(nb, struct dw8250_data, clk_notifier);
@@ -366,6 +372,7 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	struct device_node *np = p->dev->of_node;
+	unsigned int quirks = data->pdata->quirks;
 
 	if (np) {
 		int id;
@@ -375,7 +382,7 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 		if (id >= 0)
 			p->line = id;
 #ifdef CONFIG_64BIT
-		if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
+		if (quirks & DW_UART_QUIRK_OCTEON) {
 			p->serial_in = dw8250_serial_inq;
 			p->serial_out = dw8250_serial_outq;
 			p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
@@ -391,9 +398,9 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 			p->serial_out = dw8250_serial_out32be;
 		}
 
-		if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
+		if (quirks & DW_UART_QUIRK_ARMADA_38X)
 			p->serial_out = dw8250_serial_out38x;
-		if (of_device_is_compatible(np, "starfive,jh7100-uart"))
+		if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
 			p->set_termios = dw8250_do_set_termios;
 
 	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
@@ -456,6 +463,7 @@ static int dw8250_probe(struct platform_device *pdev)
 
 	data->data.dma.fn = dw8250_fallback_dma_filter;
 	data->usr_reg = DW_UART_USR;
+	data->pdata = device_get_match_data(p->dev);
 	p->private_data = &data->data;
 
 	data->uart_16550_compatible = device_property_read_bool(dev,
@@ -672,12 +680,30 @@ static const struct dev_pm_ops dw8250_pm_ops = {
 	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 };
 
+static const struct dw8250_platform_data dw8250_dw_apb = {
+};
+
+static const struct dw8250_platform_data dw8250_octeon_3860_data = {
+	.quirks = DW_UART_QUIRK_OCTEON,
+};
+
+static const struct dw8250_platform_data dw8250_armada_38x_data = {
+	.quirks = DW_UART_QUIRK_ARMADA_38X,
+};
+
+static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
+};
+
+static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
+};
+
 static const struct of_device_id dw8250_of_match[] = {
-	{ .compatible = "snps,dw-apb-uart" },
-	{ .compatible = "cavium,octeon-3860-uart" },
-	{ .compatible = "marvell,armada-38x-uart" },
-	{ .compatible = "renesas,rzn1-uart" },
-	{ .compatible = "starfive,jh7100-uart" },
+	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
+	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
+	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
+	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
+	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 72e7dbcccad0..68bb81bee660 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -21,8 +21,13 @@ struct dw8250_port_data {
 	u8			dlf_size;
 };
 
+struct dw8250_platform_data {
+	unsigned int quirks;
+};
+
 struct dw8250_data {
 	struct dw8250_port_data	data;
+	const struct dw8250_platform_data *pdata;
 
 	u8			usr_reg;
 	int			msr_mask_on;
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 03/12] serial: 8250: dw: Move the USR register to pdata
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 01/12] serial: 8250: dw: Move definitions to the shared header Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 02/12] serial: 8250: dw: Create a generic platform data structure Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 04/12] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized Miquel Raynal
                   ` (8 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

This offset is a good candidate to pdata's because it changes depending
on the vendor implementation. Let's move the usr_reg entry from regular
to pdata. This way we can drop initializing it at run time.

Let's also use a define for it instead of defining only the default
value.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c    | 11 ++++++++---
 drivers/tty/serial/8250/8250_dwlib.h |  2 +-
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 7fdb2683f534..b34edc88af3d 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -35,6 +35,8 @@
 /* Offsets for the DesignWare specific registers */
 #define DW_UART_USR	0x1f /* UART Status Register */
 
+#define OCTEON_UART_USR	0x27 /* UART Status Register */
+
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE		BIT(6)
 
@@ -251,7 +253,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 
 	if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 		/* Clear the USR */
-		(void)p->serial_in(p, d->usr_reg);
+		(void)p->serial_in(p, d->pdata->usr_reg);
 
 		return 1;
 	}
@@ -387,7 +389,6 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 			p->serial_out = dw8250_serial_outq;
 			p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 			p->type = PORT_OCTEON;
-			data->usr_reg = 0x27;
 			data->skip_autocfg = true;
 		}
 #endif
@@ -462,7 +463,6 @@ static int dw8250_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	data->data.dma.fn = dw8250_fallback_dma_filter;
-	data->usr_reg = DW_UART_USR;
 	data->pdata = device_get_match_data(p->dev);
 	p->private_data = &data->data;
 
@@ -681,20 +681,25 @@ static const struct dev_pm_ops dw8250_pm_ops = {
 };
 
 static const struct dw8250_platform_data dw8250_dw_apb = {
+	.usr_reg = DW_UART_USR,
 };
 
 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
+	.usr_reg = OCTEON_UART_USR,
 	.quirks = DW_UART_QUIRK_OCTEON,
 };
 
 static const struct dw8250_platform_data dw8250_armada_38x_data = {
+	.usr_reg = DW_UART_USR,
 	.quirks = DW_UART_QUIRK_ARMADA_38X,
 };
 
 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
+	.usr_reg = DW_UART_USR,
 };
 
 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+	.usr_reg = DW_UART_USR,
 	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 };
 
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 68bb81bee660..0df6baa6eaee 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -22,6 +22,7 @@ struct dw8250_port_data {
 };
 
 struct dw8250_platform_data {
+	u8 usr_reg;
 	unsigned int quirks;
 };
 
@@ -29,7 +30,6 @@ struct dw8250_data {
 	struct dw8250_port_data	data;
 	const struct dw8250_platform_data *pdata;
 
-	u8			usr_reg;
 	int			msr_mask_on;
 	int			msr_mask_off;
 	struct clk		*clk;
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 04/12] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (2 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 03/12] serial: 8250: dw: Move the USR register to pdata Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 05/12] serial: 8250: dma: Allow driver operations before starting DMA transfers Miquel Raynal
                   ` (7 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen,
	Phil Edworthy

DW UART controllers can be synthesized without the CPR register.
In this case, allow to the platform information to provide a CPR value.

Co-developed-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dwlib.c | 10 +++++++---
 drivers/tty/serial/8250/8250_dwlib.h |  1 +
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index 622d3b0d89e7..f1fb20353612 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -89,6 +89,8 @@ EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
 
 void dw8250_setup_port(struct uart_port *p)
 {
+	struct dw8250_port_data *pd = p->private_data;
+	struct dw8250_data *data = to_dw8250_data(pd);
 	struct uart_8250_port *up = up_to_u8250p(p);
 	u32 reg;
 
@@ -108,14 +110,16 @@ void dw8250_setup_port(struct uart_port *p)
 	dw8250_writel_ext(p, DW_UART_DLF, 0);
 
 	if (reg) {
-		struct dw8250_port_data *d = p->private_data;
-
-		d->dlf_size = fls(reg);
+		pd->dlf_size = fls(reg);
 		p->get_divisor = dw8250_get_divisor;
 		p->set_divisor = dw8250_set_divisor;
 	}
 
 	reg = dw8250_readl_ext(p, DW_UART_CPR);
+	if (!reg) {
+		reg = data->pdata->cpr_val;
+		dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
+	}
 	if (!reg)
 		return;
 
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 0df6baa6eaee..36a839ef5d9a 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -23,6 +23,7 @@ struct dw8250_port_data {
 
 struct dw8250_platform_data {
 	u8 usr_reg;
+	u32 cpr_val;
 	unsigned int quirks;
 };
 
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 05/12] serial: 8250: dma: Allow driver operations before starting DMA transfers
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (3 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 04/12] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 06/12] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path Miquel Raynal
                   ` (6 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

One situation where this could be used is when configuring the UART
controller to be the DMA flow controller. This is a typical case where
the driver might need to program a few more registers before starting a
DMA transfer. Provide the necessary infrastructure to support this
case.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250.h     | 18 ++++++++++++++++++
 drivers/tty/serial/8250/8250_dma.c |  4 ++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index 39ffeb37786f..5a4e05c0e552 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -17,6 +17,8 @@
 struct uart_8250_dma {
 	int (*tx_dma)(struct uart_8250_port *p);
 	int (*rx_dma)(struct uart_8250_port *p);
+	void (*prepare_tx_dma)(struct uart_8250_port *p);
+	void (*prepare_rx_dma)(struct uart_8250_port *p);
 
 	/* Filter function */
 	dma_filter_fn		fn;
@@ -302,6 +304,22 @@ extern int serial8250_rx_dma(struct uart_8250_port *);
 extern void serial8250_rx_dma_flush(struct uart_8250_port *);
 extern int serial8250_request_dma(struct uart_8250_port *);
 extern void serial8250_release_dma(struct uart_8250_port *);
+
+static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
+{
+	struct uart_8250_dma *dma = p->dma;
+
+	if (dma->prepare_tx_dma)
+		dma->prepare_tx_dma(p);
+}
+
+static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
+{
+	struct uart_8250_dma *dma = p->dma;
+
+	if (dma->prepare_rx_dma)
+		dma->prepare_rx_dma(p);
+}
 #else
 static inline int serial8250_tx_dma(struct uart_8250_port *p)
 {
diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c
index b3c3f7e5851a..1bdc8d6432fe 100644
--- a/drivers/tty/serial/8250/8250_dma.c
+++ b/drivers/tty/serial/8250/8250_dma.c
@@ -86,6 +86,8 @@ int serial8250_tx_dma(struct uart_8250_port *p)
 
 	dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 
+	serial8250_do_prepare_tx_dma(p);
+
 	desc = dmaengine_prep_slave_single(dma->txchan,
 					   dma->tx_addr + xmit->tail,
 					   dma->tx_size, DMA_MEM_TO_DEV,
@@ -123,6 +125,8 @@ int serial8250_rx_dma(struct uart_8250_port *p)
 	if (dma->rx_running)
 		return 0;
 
+	serial8250_do_prepare_rx_dma(p);
+
 	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 					   dma->rx_size, DMA_DEV_TO_MEM,
 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 06/12] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (4 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 05/12] serial: 8250: dma: Allow driver operations before starting DMA transfers Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 07/12] serial: 8250: dw: Move the IO accessors to 8250_dwlib.h Miquel Raynal
                   ` (5 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

In a next change we are going to need the same Rx timeout condition as
we already have in the IRQ handling code. Let's just create a boolean to
clarify what this operation does before reusing it.

There is no functional change.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index b34edc88af3d..ef3f05c82ad6 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -225,6 +225,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	struct uart_8250_port *up = up_to_u8250p(p);
 	struct dw8250_data *d = to_dw8250_data(p->private_data);
 	unsigned int iir = p->serial_in(p, UART_IIR);
+	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
 	unsigned int status;
 	unsigned long flags;
 
@@ -238,7 +239,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	 * This problem has only been observed so far when not in DMA mode
 	 * so we limit the workaround only to non-DMA mode.
 	 */
-	if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
+	if (!up->dma && rx_timeout) {
 		spin_lock_irqsave(&p->lock, flags);
 		status = p->serial_in(p, UART_LSR);
 
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 07/12] serial: 8250: dw: Move the IO accessors to 8250_dwlib.h
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (5 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 06/12] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 08/12] serial: 8250: dw: Add support for DMA flow controlling devices Miquel Raynal
                   ` (4 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

These accessors should be used instead of the regular readl/writel()
helpers. In order to use them also from 8250_dw.c in this directory,
move the helpers to 8250_dwlib.h

There is no functional change.

There is no need for declaring `struct uart_port` or even UPIO_MEM32BE
which both are already included in the 8250_dwlib.h header by 8250.h.

Suggested-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dwlib.c | 16 ----------------
 drivers/tty/serial/8250/8250_dwlib.h | 16 ++++++++++++++++
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index f1fb20353612..b3df6dee9ceb 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -3,7 +3,6 @@
 
 #include <linux/bitops.h>
 #include <linux/device.h>
-#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_core.h>
@@ -32,21 +31,6 @@
 /* Helper for FIFO size calculation */
 #define DW_UART_CPR_FIFO_SIZE(a)	(((a >> 16) & 0xff) * 16)
 
-static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
-{
-	if (p->iotype == UPIO_MEM32BE)
-		return ioread32be(p->membase + offset);
-	return readl(p->membase + offset);
-}
-
-static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
-{
-	if (p->iotype == UPIO_MEM32BE)
-		iowrite32be(reg, p->membase + offset);
-	else
-		writel(reg, p->membase + offset);
-}
-
 /*
  * divisor = div(I) + div(F)
  * "I" means integer, "F" means fractional
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 36a839ef5d9a..b10e60a5d16a 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Synopsys DesignWare 8250 library header file. */
 
+#include <linux/io.h>
 #include <linux/notifier.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
@@ -50,3 +51,18 @@ static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
 {
 	return container_of(data, struct dw8250_data, data);
 }
+
+static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
+{
+	if (p->iotype == UPIO_MEM32BE)
+		return ioread32be(p->membase + offset);
+	return readl(p->membase + offset);
+}
+
+static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
+{
+	if (p->iotype == UPIO_MEM32BE)
+		iowrite32be(reg, p->membase + offset);
+	else
+		writel(reg, p->membase + offset);
+}
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 08/12] serial: 8250: dw: Add support for DMA flow controlling devices
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (6 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 07/12] serial: 8250: dw: Move the IO accessors to 8250_dwlib.h Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 09/12] serial: 8250: dw: Improve RZN1 support Miquel Raynal
                   ` (3 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen,
	Phil Edworthy

From: Phil Edworthy <phil.edworthy@renesas.com>

DW based controllers like the one on Renesas RZ/N1 must be programmed as
flow controllers when using DMA.

* Table 11.45 of the system manual, "Flow Control Combinations", states
  that using UART with DMA requires setting the DMA in the peripheral
  flow controller mode regardless of the direction.

* Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions",
  explains that the burst size in the above case must be configured in
  the peripheral's register DEST/SRC_BURST_SIZE.

Experiments shown that upon Rx timeout, the DMA transaction needed to be
manually cleared as well.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index ef3f05c82ad6..90e64c8bd4bf 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -34,16 +34,28 @@
 
 /* Offsets for the DesignWare specific registers */
 #define DW_UART_USR	0x1f /* UART Status Register */
+#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
 
 #define OCTEON_UART_USR	0x27 /* UART Status Register */
 
+#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
+#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
+
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE		BIT(6)
 
+/* Renesas specific register fields */
+#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
+#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
+#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
+#define RZN1_UART_xDMACR_8_WORD_BURST	(3 << 1)
+#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
+
 /* Quirks */
 #define DW_UART_QUIRK_OCTEON		BIT(0)
 #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
 #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
+#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
 
 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 {
@@ -226,6 +238,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	struct dw8250_data *d = to_dw8250_data(p->private_data);
 	unsigned int iir = p->serial_in(p, UART_IIR);
 	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
+	unsigned int quirks = d->pdata->quirks;
 	unsigned int status;
 	unsigned long flags;
 
@@ -249,6 +262,15 @@ static int dw8250_handle_irq(struct uart_port *p)
 		spin_unlock_irqrestore(&p->lock, flags);
 	}
 
+	/* Manually stop the Rx DMA transfer when acting as flow controller */
+	if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
+		status = p->serial_in(p, UART_LSR);
+		if (status & (UART_LSR_DR | UART_LSR_BI)) {
+			dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
+			dw8250_writel_ext(p, DW_UART_DMASA, 1);
+		}
+	}
+
 	if (serial8250_handle_irq(p, iir))
 		return 1;
 
@@ -372,6 +394,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 	return param == chan->device->dev;
 }
 
+static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
+{
+	if (max_burst >= 8)
+		return RZN1_UART_xDMACR_8_WORD_BURST;
+	else if (max_burst >= 4)
+		return RZN1_UART_xDMACR_4_WORD_BURST;
+	else
+		return RZN1_UART_xDMACR_1_WORD_BURST;
+}
+
+static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
+{
+	struct uart_port *up = &p->port;
+	struct uart_8250_dma *dma = p->dma;
+	u32 val;
+
+	dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
+	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
+	      RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
+	      RZN1_UART_xDMACR_DMA_EN;
+	dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
+}
+
+static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
+{
+	struct uart_port *up = &p->port;
+	struct uart_8250_dma *dma = p->dma;
+	u32 val;
+
+	dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
+	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
+	      RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
+	      RZN1_UART_xDMACR_DMA_EN;
+	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
+}
+
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	struct device_node *np = p->dev->of_node;
@@ -404,6 +462,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 			p->serial_out = dw8250_serial_out38x;
 		if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
 			p->set_termios = dw8250_do_set_termios;
+		if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
+			data->data.dma.txconf.device_fc = 1;
+			data->data.dma.rxconf.device_fc = 1;
+			data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
+			data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
+		}
 
 	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
 		p->iotype = UPIO_MEM32;
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 09/12] serial: 8250: dw: Improve RZN1 support
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (7 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 08/12] serial: 8250: dw: Add support for DMA flow controlling devices Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties Miquel Raynal
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen,
	Phil Edworthy

From: Phil Edworthy <phil.edworthy@renesas.com>

Renesas RZ/N1 SoC features a slightly modified DW UART.

On this SoC, the CPR register value is known but not synthetized in
hardware. We hence need to provide a CPR value in the platform
data. This version of the controller also relies on acting as flow
controller when using DMA, so we need to provide the
"is dma flow controller" quirk.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/tty/serial/8250/8250_dw.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 90e64c8bd4bf..0cf1a99dc124 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -761,6 +761,8 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
 
 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
 	.usr_reg = DW_UART_USR,
+	.cpr_val = 0x00012f32,
+	.quirks = DW_UART_QUIRK_IS_DMA_FC,
 };
 
 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (8 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 09/12] serial: 8250: dw: Improve RZN1 support Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-28  9:09   ` Geert Uytterhoeven
  2022-04-21  9:53 ` [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4 Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 12/12] bestla: Add support for RZN1 dmamux Miquel Raynal
  11 siblings, 1 reply; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

UART 0 to 2 do not have DMA support, while UART 3 to 7 do.

Fill the "dmas" and "dma-names" properties for each of these nodes.

Please mind that these nodes go through the dmamux node which will
redirect the requests to the right DMA controller. The first 4 cells of
the "dmas" properties will be transferred as-is to the DMA
controllers. The last 2 cells are consumed by the dmamux. Which means
cell 0 and 4 are almost redundant, one giving the controller request ID
and the other the dmamux channel which is a 1:1 translation of the
request IDs, shifted by 16 when pointing to the second DMA controller.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index c854aa4cfa77..4288b935fcea 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -144,6 +144,9 @@ uart3: serial@50000000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 0 0 0 0 0 1>,
+				<&dmamux 1 0 0 0 1 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -155,6 +158,9 @@ uart4: serial@50001000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 2 0 0 0 2 1>,
+				<&dmamux 3 0 0 0 3 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -166,6 +172,9 @@ uart5: serial@50002000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 4 0 0 0 4 1>,
+				<&dmamux 5 0 0 0 5 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -177,6 +186,9 @@ uart6: serial@50003000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 6 0 0 0 6 1>,
+				<&dmamux 7 0 0 0 7 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -188,6 +200,9 @@ uart7: serial@50004000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 4 0 0 0 20 1>,
+				<&dmamux 5 0 0 0 21 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (9 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  2022-04-21 10:21   ` Miquel Raynal
  2022-04-21  9:53 ` [PATCH v6 12/12] bestla: Add support for RZN1 dmamux Miquel Raynal
  11 siblings, 1 reply; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 .../boot/dts/r9a06g032-rzn1d400-bestla.dts    | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts
index f42a3ba70541..70aa026bd292 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-bestla.dts
@@ -22,6 +22,8 @@ chosen {
 
 	aliases {
 		serial0 = &uart0;
+		serial3 = &uart3;
+
 	};
 };
 
@@ -31,6 +33,22 @@ &uart0 {
 	status = "okay";
 };
 
+&uart3 {
+	pinctrl-0 = <&pins_uart3>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-0 = <&pins_uart4>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
 &nand_controller {
 	pinctrl-0 = <&pins_nand>;
 	pinctrl-names = "default";
@@ -82,4 +100,21 @@ RZN1_PINMUX(104, RZN1_FUNC_UART0_I)	/* UART0_RXD */
 		>;
 		bias-disable;
 	};
+
+	pins_uart3: pins_uart3 {
+		pinmux = <
+			RZN1_PINMUX(123, RZN1_FUNC_UART3)       /* UART3_TXD */
+			RZN1_PINMUX(124, RZN1_FUNC_UART3)       /* UART3_RXD */
+			RZN1_PINMUX(125, RZN1_FUNC_UART3)       /* UART3_RTS_N */
+                >;
+		bias-disable;
+	};
+
+	pins_uart4: pins_uart4 {
+		pinmux = <
+			RZN1_PINMUX(109, RZN1_FUNC_UART4)       /* UART4_TXD */
+			RZN1_PINMUX(110, RZN1_FUNC_UART4)       /* UART4_RXD */
+                >;
+		bias-disable;
+	};
 };
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH v6 12/12] bestla: Add support for RZN1 dmamux
  2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
                   ` (10 preceding siblings ...)
  2022-04-21  9:53 ` [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4 Miquel Raynal
@ 2022-04-21  9:53 ` Miquel Raynal
  11 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21  9:53 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Miquel Raynal, Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm/configs/bestla_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/configs/bestla_defconfig b/arch/arm/configs/bestla_defconfig
index 1d84f44fbf7d..fc573cbdddf4 100644
--- a/arch/arm/configs/bestla_defconfig
+++ b/arch/arm/configs/bestla_defconfig
@@ -66,7 +66,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_BLK_DEV_BSGLIB=y
 CONFIG_KSM=y
 CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
-CONFIG_CLEANCACHE=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
@@ -106,6 +105,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_DMADEVICES=y
 CONFIG_DW_DMAC=y
+CONFIG_RZN1_DMAMUX=y
 CONFIG_DMATEST=y
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_VHOST_MENU is not set
-- 
2.27.0


^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4
  2022-04-21  9:53 ` [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4 Miquel Raynal
@ 2022-04-21 10:21   ` Miquel Raynal
  2022-04-22 14:04     ` Greg Kroah-Hartman
  0 siblings, 1 reply; 19+ messages in thread
From: Miquel Raynal @ 2022-04-21 10:21 UTC (permalink / raw)
  To: Geert Uytterhoeven, Magnus Damm, Greg Kroah-Hartman, Jiri Slaby
  Cc: Andy Shevchenko, linux-renesas-soc, linux-serial,
	Milan Stevanovic, Jimmy Lalande, Pascal Eberhard,
	Thomas Petazzoni, Herve Codina, Clement Leger, Ilpo Jarvinen

Hello,

miquel.raynal@bootlin.com wrote on Thu, 21 Apr 2022 11:53:22 +0200:

> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

Please ignore these two dts patches, they were meant for testing
purposes only, sorry for the noise.

Thanks,
Miquèl

> ---
>  .../boot/dts/r9a06g032-rzn1d400-bestla.dts    | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4
  2022-04-21 10:21   ` Miquel Raynal
@ 2022-04-22 14:04     ` Greg Kroah-Hartman
  2022-04-22 14:26       ` Geert Uytterhoeven
  0 siblings, 1 reply; 19+ messages in thread
From: Greg Kroah-Hartman @ 2022-04-22 14:04 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: Geert Uytterhoeven, Magnus Damm, Jiri Slaby, Andy Shevchenko,
	linux-renesas-soc, linux-serial, Milan Stevanovic, Jimmy Lalande,
	Pascal Eberhard, Thomas Petazzoni, Herve Codina, Clement Leger,
	Ilpo Jarvinen

On Thu, Apr 21, 2022 at 12:21:43PM +0200, Miquel Raynal wrote:
> Hello,
> 
> miquel.raynal@bootlin.com wrote on Thu, 21 Apr 2022 11:53:22 +0200:
> 
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> 
> Please ignore these two dts patches, they were meant for testing
> purposes only, sorry for the noise.

I can't do that, please resend a new version of the series as our tools
take all of the patches in a series.

thanks,

greg k-h

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4
  2022-04-22 14:04     ` Greg Kroah-Hartman
@ 2022-04-22 14:26       ` Geert Uytterhoeven
  2022-04-22 15:52         ` Miquel Raynal
  0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2022-04-22 14:26 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: Greg Kroah-Hartman, Magnus Damm, Jiri Slaby, Andy Shevchenko,
	Linux-Renesas, open list:SERIAL DRIVERS, Milan Stevanovic,
	Jimmy Lalande, Pascal Eberhard, Thomas Petazzoni, Herve Codina,
	Clement Leger, Ilpo Jarvinen

Hi Miquel,

On Fri, Apr 22, 2022 at 4:04 PM Greg Kroah-Hartman
<gregkh@linuxfoundation.org> wrote:
> On Thu, Apr 21, 2022 at 12:21:43PM +0200, Miquel Raynal wrote:
> > miquel.raynal@bootlin.com wrote on Thu, 21 Apr 2022 11:53:22 +0200:
> > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> >
> > Please ignore these two dts patches, they were meant for testing
> > purposes only, sorry for the noise.
>
> I can't do that, please resend a new version of the series as our tools
> take all of the patches in a series.

While at it, please drop patch 10/12 from the reposted series, too,
as it should go in through the renesas-arm-dt and soc trees.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4
  2022-04-22 14:26       ` Geert Uytterhoeven
@ 2022-04-22 15:52         ` Miquel Raynal
  0 siblings, 0 replies; 19+ messages in thread
From: Miquel Raynal @ 2022-04-22 15:52 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Greg Kroah-Hartman, Magnus Damm, Jiri Slaby, Andy Shevchenko,
	Linux-Renesas, open list:SERIAL DRIVERS, Milan Stevanovic,
	Jimmy Lalande, Pascal Eberhard, Thomas Petazzoni, Herve Codina,
	Clement Leger, Ilpo Jarvinen

Hi Greg & Geert,

geert@linux-m68k.org wrote on Fri, 22 Apr 2022 16:26:05 +0200:

> Hi Miquel,
> 
> On Fri, Apr 22, 2022 at 4:04 PM Greg Kroah-Hartman
> <gregkh@linuxfoundation.org> wrote:
> > On Thu, Apr 21, 2022 at 12:21:43PM +0200, Miquel Raynal wrote:  
> > > miquel.raynal@bootlin.com wrote on Thu, 21 Apr 2022 11:53:22 +0200:  
> > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>  
> > >
> > > Please ignore these two dts patches, they were meant for testing
> > > purposes only, sorry for the noise.  
> >
> > I can't do that, please resend a new version of the series as our tools
> > take all of the patches in a series.  
> 
> While at it, please drop patch 10/12 from the reposted series, too,
> as it should go in through the renesas-arm-dt and soc trees.

Sure, no problem.

Thanks,
Miquèl

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties
  2022-04-21  9:53 ` [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties Miquel Raynal
@ 2022-04-28  9:09   ` Geert Uytterhoeven
  2022-05-03  8:36     ` Geert Uytterhoeven
  0 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28  9:09 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: Magnus Damm, Greg Kroah-Hartman, Jiri Slaby, Andy Shevchenko,
	Linux-Renesas, open list:SERIAL DRIVERS, Milan Stevanovic,
	Jimmy Lalande, Pascal Eberhard, Thomas Petazzoni, Herve Codina,
	Clement Leger, Ilpo Jarvinen

On Thu, Apr 21, 2022 at 11:53 AM Miquel Raynal
<miquel.raynal@bootlin.com> wrote:
> UART 0 to 2 do not have DMA support, while UART 3 to 7 do.
>
> Fill the "dmas" and "dma-names" properties for each of these nodes.
>
> Please mind that these nodes go through the dmamux node which will
> redirect the requests to the right DMA controller. The first 4 cells of
> the "dmas" properties will be transferred as-is to the DMA
> controllers. The last 2 cells are consumed by the dmamux. Which means
> cell 0 and 4 are almost redundant, one giving the controller request ID
> and the other the dmamux channel which is a 1:1 translation of the
> request IDs, shifted by 16 when pointing to the second DMA controller.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties
  2022-04-28  9:09   ` Geert Uytterhoeven
@ 2022-05-03  8:36     ` Geert Uytterhoeven
  0 siblings, 0 replies; 19+ messages in thread
From: Geert Uytterhoeven @ 2022-05-03  8:36 UTC (permalink / raw)
  To: Miquel Raynal
  Cc: Magnus Damm, Greg Kroah-Hartman, Jiri Slaby, Andy Shevchenko,
	Linux-Renesas, open list:SERIAL DRIVERS, Milan Stevanovic,
	Jimmy Lalande, Pascal Eberhard, Thomas Petazzoni, Herve Codina,
	Clement Leger, Ilpo Jarvinen

On Thu, Apr 28, 2022 at 11:09 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Thu, Apr 21, 2022 at 11:53 AM Miquel Raynal
> <miquel.raynal@bootlin.com> wrote:
> > UART 0 to 2 do not have DMA support, while UART 3 to 7 do.
> >
> > Fill the "dmas" and "dma-names" properties for each of these nodes.
> >
> > Please mind that these nodes go through the dmamux node which will
> > redirect the requests to the right DMA controller. The first 4 cells of
> > the "dmas" properties will be transferred as-is to the DMA
> > controllers. The last 2 cells are consumed by the dmamux. Which means
> > cell 0 and 4 are almost redundant, one giving the controller request ID
> > and the other the dmamux channel which is a 1:1 translation of the
> > request IDs, shifted by 16 when pointing to the second DMA controller.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Queuing in renesas-devel for v5.19.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2022-05-03  8:37 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-21  9:53 [PATCH v6 00/12] serial: 8250: dw: RZN1 DMA support Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 01/12] serial: 8250: dw: Move definitions to the shared header Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 02/12] serial: 8250: dw: Create a generic platform data structure Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 03/12] serial: 8250: dw: Move the USR register to pdata Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 04/12] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 05/12] serial: 8250: dma: Allow driver operations before starting DMA transfers Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 06/12] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 07/12] serial: 8250: dw: Move the IO accessors to 8250_dwlib.h Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 08/12] serial: 8250: dw: Add support for DMA flow controlling devices Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 09/12] serial: 8250: dw: Improve RZN1 support Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 10/12] ARM: dts: r9a06g032: Fill the UART DMA properties Miquel Raynal
2022-04-28  9:09   ` Geert Uytterhoeven
2022-05-03  8:36     ` Geert Uytterhoeven
2022-04-21  9:53 ` [PATCH v6 11/12] bestla: Enable DMA, UART3 and UART4 Miquel Raynal
2022-04-21 10:21   ` Miquel Raynal
2022-04-22 14:04     ` Greg Kroah-Hartman
2022-04-22 14:26       ` Geert Uytterhoeven
2022-04-22 15:52         ` Miquel Raynal
2022-04-21  9:53 ` [PATCH v6 12/12] bestla: Add support for RZN1 dmamux Miquel Raynal

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