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([2607:fb90:80c8:6cf3:a91a:4957:ba18:ac18]) by smtp.gmail.com with ESMTPSA id z16-20020a056a00241000b004f3a647ae89sm24616248pfh.174.2022.04.21.08.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 08:18:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 29/64] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Date: Thu, 21 Apr 2022 08:17:00 -0700 Message-Id: <20220421151735.31996-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421151735.31996-1-richard.henderson@linaro.org> References: <20220421151735.31996-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 29 +++++++++++++++++++---------- target/nios2/helper.c | 7 ++----- target/nios2/mmu.c | 35 +++++++++++++++++------------------ target/nios2/translate.c | 2 +- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 54b592c422..ec34cebf72 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_G R_CR_TLBACC_G_MASK #define CR_TLBMISC 10 -#define CR_TLBMISC_WAY_SHIFT 20 -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) -#define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WE (1 << 18) -#define CR_TLBMISC_PID_SHIFT 4 -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) -#define CR_TLBMISC_DBL (1 << 3) -#define CR_TLBMISC_BAD (1 << 2) -#define CR_TLBMISC_PERM (1 << 1) -#define CR_TLBMISC_D (1 << 0) + +FIELD(CR_TLBMISC, D, 0, 1) +FIELD(CR_TLBMISC, PERM, 1, 1) +FIELD(CR_TLBMISC, BAD, 2, 1) +FIELD(CR_TLBMISC, DBL, 3, 1) +FIELD(CR_TLBMISC, PID, 4, 14) +FIELD(CR_TLBMISC, WE, 18, 1) +FIELD(CR_TLBMISC, RD, 19, 1) +FIELD(CR_TLBMISC, WAY, 20, 4) +FIELD(CR_TLBMISC, EE, 24, 1) + +#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK +#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK +#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK +#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK +#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK +#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK +#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK + #define CR_ENCINJ 11 #define CR_BADADDR 12 #define CR_CONFIG 13 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 31d83e0291..a56aaaea18 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -281,11 +281,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return false; } - if (access_type == MMU_INST_FETCH) { - env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D; - } else { - env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D; - } + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D, + access_type != MMU_INST_FETCH); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR]; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0f33ea5e04..d9b690b78e 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env, target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu = env_archcpu(env); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int vpn = vaddr >> 12; int way, n_ways = cpu->tlb_num_ways; @@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) /* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { - int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); - int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int g = FIELD_EX32(v, CR_TLBACC, G); int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry = @@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) entry->data = newData; } /* Auto-increment tlbmisc.WAY */ - env->ctrl[CR_TLBMISC] = - (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], + CR_TLBMISC, WAY, + (way + 1) & (cpu->tlb_num_ways - 1)); } /* Writes to TLBACC don't change the read-back value */ @@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v) void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) { Nios2CPU *cpu = env_archcpu(env); + uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID); + uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); + uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY); - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + trace_nios2_mmu_write_tlbmisc(way, (v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); + new_pid); - if ((v & CR_TLBMISC_PID_MASK) != - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); + if (new_pid != old_pid) { + mmu_flush_pid(env, old_pid); } + /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */ if (v & CR_TLBMISC_RD) { - int way = (v >> CR_TLBMISC_WAY_SHIFT); int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry = &env->mmu.tlb[(way * cpu->tlb_num_ways) + @@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |= entry->data; env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->ctrl[CR_TLBMISC] = - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); + env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID, + entry->tag & + ((1 << cpu->pid_num_bits) - 1)); env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, entry->tag >> TARGET_PAGE_BITS); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index baa22c5101..4191db1342 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -925,7 +925,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), env->mmu.tlbacc_wr); #endif qemu_fprintf(f, "\n\n"); -- 2.34.1