From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9148C433F5 for ; Mon, 25 Apr 2022 00:05:34 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A3FCB83E5D; Mon, 25 Apr 2022 02:05:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mirx.dev Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mirx.dev header.i=@mirx.dev header.b="haBUsJc2"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="FFFFTee+"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BF46683D86; Mon, 25 Apr 2022 02:04:39 +0200 (CEST) Received: from wout3-smtp.messagingengine.com (wout3-smtp.messagingengine.com [64.147.123.19]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E8EF683E3B for ; Mon, 25 Apr 2022 02:04:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mirx.dev Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andrew@mirx.dev Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 7D7083201FD3; Sun, 24 Apr 2022 20:04:26 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Sun, 24 Apr 2022 20:04:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mirx.dev; h=cc :cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm3; t=1650845065; x=1650931465; bh=s7 CTCKAFfaMu1z6uh8pyV5KSB9U0lykz6ZHZ7VFFnHc=; b=haBUsJc2PGJTZw8lmG R04bSttKvx6ah0c0nNcD4V0vYsyjmbOnotcm1hhx7P9Mab+G/Z+BRjtXlWVlReR3 /KZVNY6DAirI99Rq+VseHvkWD2fQnMFBy0ChWCVNbUdkIgMzwz2QWf/5XIcdrEeD 5uarTQyoH+4W1JBLH85zC49lgO0m+inn5BGFmoFH9wKh1dHmc8+nGCi5sKR1O8wv Kb43eoi0valvvZ3goTTA9ElHbbQdtSsF0Y0Vi7ifJehCyis3QnKkdpsDifavepzw /vBETdLsyKQnRuoEZ5JeqGnpQbpLDnq/h5Za7JFAGtE1RwzCmZ0ZV+nHYqsbOvRJ hbBg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1650845065; x=1650931465; bh=s7CTCKAFfaMu1z6uh8pyV5KSB9U0lykz6ZH Z7VFFnHc=; b=FFFFTee+8mLxzp8zidV9nO1Hfq078bza7jmANHb++dWrgvdWzcy v8cUxMP8Os9i6J6iPQpFmLsvZVo/9KHHjZKWbPhBwAGkY2tKsOOOjK2jP8yJU9F3 Sj/kpjxy71ToSxbEYJqh7VaPyCXKV+aWN+A/8asyJ4I9qgPPf3uB6IvvWEdn6pQW 1WHWLibX6Rehq7syaLHhQKaiWXyfoTzKmLvgbugmHSHqgpb3+HCh37dc5dbrQBcx qK1gHdgmBUO1FHL4sBbHcPT/HbVA+zDJZ6nZIoffhlD5SIo2iOCG8Vp1ifkJkXtq UL7+99kWeurv+Zzd2VdD7uKfMBkuskE5B+w== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedruddtgdefudcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpeetnhgurhgv ficutegssghothhtuceorghnughrvgifsehmihhrgidruggvvheqnecuggftrfgrthhtvg hrnhepleeigeejjeegvdejjeetheevheetgedvffdtteegvdeltdejgeehkeekfeeviedt necuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomheprghnug hrvgifsehmihhrgidruggvvh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 20:04:22 -0400 (EDT) From: Andrew Abbott To: u-boot@lists.denx.de Cc: Andrew Abbott , Simon Glass , Philipp Tomsich , Kever Yang , Peter Robinson , Akash Gajjar , Jagan Teki , Samuel Dionne-Riel Subject: [RFC PATCH 6/8] rockchip: Enable binman for ARM64 Date: Mon, 25 Apr 2022 10:03:27 +1000 Message-Id: <20220425000329.28124-7-andrew@mirx.dev> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220425000329.28124-1-andrew@mirx.dev> References: <20220425000329.28124-1-andrew@mirx.dev> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Binman is now being used to build the final flashable images for Rockchip devices, thus enabling it for all Rockchip targets here. But it is not yet being used to generate the FIT image (u-boot.itb), thus we need to force it to be built. Signed-off-by: Andrew Abbott --- Question: Will this causes issues with eg. Chromebook gru/bob, which build u-boot.itb with binman already? --- Kconfig | 4 ++-- arch/arm/Kconfig | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index bdae59e06f..99e5491f08 100644 --- a/Kconfig +++ b/Kconfig @@ -406,8 +406,8 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ - ARCH_SUNXI || RISCV || ARCH_ZYNQMP) + default "u-boot.itb" if ARCH_ROCKCHIP || (!BINMAN && SPL_LOAD_FIT && \ + (ARCH_SUNXI || RISCV || ARCH_ZYNQMP)) default "u-boot.kwb" if ARCH_KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT default "u-boot-with-spl.imx" if ARCH_MX6 && SPL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 57946f61fa..7697c74edf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1961,7 +1961,7 @@ config ARCH_STM32MP config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BLK - select BINMAN if SPL_OPTEE || (SPL && !ARM64) + select BINMAN if SPL select DM select DM_GPIO select DM_I2C -- 2.35.3