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From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, richard.henderson@linaro.org,
	gaosong@loongson.cn
Subject: [PATCH v2 30/43] hw/loongarch: Add support loongson3 virt machine type.
Date: Mon, 25 Apr 2022 17:10:14 +0800	[thread overview]
Message-ID: <20220425091027.2877892-31-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <20220425091027.2877892-1-yangxiaojuan@loongson.cn>

Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emulated.

More detailed info you can see
https://github.com/loongson/LoongArch-Documentation

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 MAINTAINERS                                   |  4 +
 .../devices/loongarch64-softmmu/default.mak   |  3 +
 configs/targets/loongarch64-softmmu.mak       |  3 +
 hw/Kconfig                                    |  1 +
 hw/loongarch/Kconfig                          |  4 +
 hw/loongarch/loongson3.c                      | 89 +++++++++++++++++++
 hw/loongarch/meson.build                      |  4 +
 hw/meson.build                                |  1 +
 include/exec/poison.h                         |  2 +
 include/hw/loongarch/virt.h                   | 31 +++++++
 include/sysemu/arch_init.h                    |  1 +
 qapi/machine.json                             |  2 +-
 target/Kconfig                                |  1 +
 target/loongarch/Kconfig                      |  2 +
 target/loongarch/cpu.c                        |  2 +
 15 files changed, 149 insertions(+), 1 deletion(-)
 create mode 100644 configs/devices/loongarch64-softmmu/default.mak
 create mode 100644 configs/targets/loongarch64-softmmu.mak
 create mode 100644 hw/loongarch/Kconfig
 create mode 100644 hw/loongarch/loongson3.c
 create mode 100644 hw/loongarch/meson.build
 create mode 100644 include/hw/loongarch/virt.h
 create mode 100644 target/loongarch/Kconfig

diff --git a/MAINTAINERS b/MAINTAINERS
index 6361c24b3a..69f4f6e60b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1130,6 +1130,10 @@ M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 M: Song Gao <gaosong@loongson.cn>
 S: Maintained
 F: docs/system/loongarch/loongson3.rst
+F: configs/targets/loongarch64-softmmu.mak
+F: configs/devices/loongarch64-softmmu/default.mak
+F: hw/loongarch/
+F: include/hw/loongarch/virt.h
 
 M68K Machines
 -------------
diff --git a/configs/devices/loongarch64-softmmu/default.mak b/configs/devices/loongarch64-softmmu/default.mak
new file mode 100644
index 0000000000..928bc117ef
--- /dev/null
+++ b/configs/devices/loongarch64-softmmu/default.mak
@@ -0,0 +1,3 @@
+# Default configuration for loongarch64-softmmu
+
+CONFIG_LOONGARCH_VIRT=y
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
new file mode 100644
index 0000000000..666154022f
--- /dev/null
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -0,0 +1,3 @@
+TARGET_ARCH=loongarch64
+TARGET_BASE_ARCH=loongarch
+TARGET_SUPPORTS_MTTCG=y
diff --git a/hw/Kconfig b/hw/Kconfig
index ad20cce0a9..f71b2155ed 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -49,6 +49,7 @@ source avr/Kconfig
 source cris/Kconfig
 source hppa/Kconfig
 source i386/Kconfig
+source loongarch/Kconfig
 source m68k/Kconfig
 source microblaze/Kconfig
 source mips/Kconfig
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
new file mode 100644
index 0000000000..13e8501897
--- /dev/null
+++ b/hw/loongarch/Kconfig
@@ -0,0 +1,4 @@
+config LOONGARCH_VIRT
+    bool
+    select PCI
+    select PCI_EXPRESS_GENERIC_BRIDGE
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
new file mode 100644
index 0000000000..a80ce8d383
--- /dev/null
+++ b/hw/loongarch/loongson3.c
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU loongson 3a5000 develop board emulation
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/datadir.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/runstate.h"
+#include "sysemu/reset.h"
+#include "sysemu/rtc.h"
+#include "hw/loongarch/virt.h"
+#include "exec/address-spaces.h"
+#include "target/loongarch/cpu.h"
+
+static void loongarch_init(MachineState *machine)
+{
+    const char *cpu_model = machine->cpu_type;
+    ram_addr_t offset = 0;
+    ram_addr_t ram_size = machine->ram_size;
+    uint64_t highram_size = 0;
+    MemoryRegion *address_space_mem = get_system_memory();
+    LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
+    int i;
+
+    if (!cpu_model) {
+        cpu_model = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
+    }
+
+    if (!strstr(cpu_model, "Loongson-3A5000")) {
+        error_report("LoongArch/TCG needs cpu type Loongson-3A5000");
+        exit(1);
+    }
+
+    /* Init CPUs */
+    for (i = 0; i < machine->smp.cpus; i++) {
+        cpu_create(machine->cpu_type);
+    }
+
+    /* Add memory region */
+    memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
+                             machine->ram, 0, 256 * MiB);
+    memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
+    offset += 256 * MiB;
+
+    highram_size = ram_size - 256 * MiB;
+    memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
+                             machine->ram, offset, highram_size);
+    memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
+
+    /* Add isa io region */
+    memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
+                             get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
+    memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
+                                &lams->isa_io);
+}
+
+static void loongarch_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "Loongson-3A5000 LS7A1000 machine";
+    mc->init = loongarch_init;
+    mc->default_ram_size = 1 * GiB;
+    mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("Loongson-3A5000");
+    mc->default_ram_id = "loongarch.ram";
+    mc->max_cpus = LOONGARCH_MAX_VCPUS;
+    mc->is_default = 1;
+    mc->default_kernel_irqchip_split = false;
+    mc->block_default_type = IF_VIRTIO;
+    mc->default_boot_order = "c";
+    mc->no_cdrom = 1;
+}
+
+static const TypeInfo loongarch_machine_types[] = {
+    {
+        .name           = TYPE_LOONGARCH_MACHINE,
+        .parent         = TYPE_MACHINE,
+        .instance_size  = sizeof(LoongArchMachineState),
+        .class_init     = loongarch_class_init,
+    }
+};
+
+DEFINE_TYPES(loongarch_machine_types)
diff --git a/hw/loongarch/meson.build b/hw/loongarch/meson.build
new file mode 100644
index 0000000000..cecb1a5d65
--- /dev/null
+++ b/hw/loongarch/meson.build
@@ -0,0 +1,4 @@
+loongarch_ss = ss.source_set()
+loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: files('loongson3.c'))
+
+hw_arch += {'loongarch': loongarch_ss}
diff --git a/hw/meson.build b/hw/meson.build
index b3366c888e..95202649b7 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -49,6 +49,7 @@ subdir('avr')
 subdir('cris')
 subdir('hppa')
 subdir('i386')
+subdir('loongarch')
 subdir('m68k')
 subdir('microblaze')
 subdir('mips')
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 9f1ca3409c..bbb82cf9ec 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -14,6 +14,7 @@
 #pragma GCC poison TARGET_CRIS
 #pragma GCC poison TARGET_HEXAGON
 #pragma GCC poison TARGET_HPPA
+#pragma GCC poison TARGET_LOONGARCH64
 #pragma GCC poison TARGET_M68K
 #pragma GCC poison TARGET_MICROBLAZE
 #pragma GCC poison TARGET_MIPS
@@ -71,6 +72,7 @@
 #pragma GCC poison CONFIG_HPPA_DIS
 #pragma GCC poison CONFIG_I386_DIS
 #pragma GCC poison CONFIG_HEXAGON_DIS
+#pragma GCC poison CONFIG_LOONGARCH_DIS
 #pragma GCC poison CONFIG_M68K_DIS
 #pragma GCC poison CONFIG_MICROBLAZE_DIS
 #pragma GCC poison CONFIG_MIPS_DIS
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
new file mode 100644
index 0000000000..4a4bb3f51f
--- /dev/null
+++ b/include/hw/loongarch/virt.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Definitions for loongarch board emulation.
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_H
+#define HW_LOONGARCH_H
+
+#include "target/loongarch/cpu.h"
+#include "hw/boards.h"
+#include "qemu/queue.h"
+
+#define LOONGARCH_MAX_VCPUS     4
+
+#define LOONGARCH_ISA_IO_BASE   0x18000000UL
+#define LOONGARCH_ISA_IO_SIZE   0x0004000
+
+struct LoongArchMachineState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    MemoryRegion lowmem;
+    MemoryRegion highmem;
+    MemoryRegion isa_io;
+};
+
+#define TYPE_LOONGARCH_MACHINE  MACHINE_TYPE_NAME("virt")
+OBJECT_DECLARE_SIMPLE_TYPE(LoongArchMachineState, LOONGARCH_MACHINE)
+#endif
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 79c2591425..8850cb1a14 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
     QEMU_ARCH_RX = (1 << 20),
     QEMU_ARCH_AVR = (1 << 21),
     QEMU_ARCH_HEXAGON = (1 << 22),
+    QEMU_ARCH_LOONGARCH = (1 << 23),
 };
 
 extern const uint32_t arch_type;
diff --git a/qapi/machine.json b/qapi/machine.json
index d25a481ce4..63fdba50d3 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -30,7 +30,7 @@
 ##
 { 'enum' : 'SysEmuTarget',
   'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386',
-             'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
+             'loongarch64', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64',
              'mips64el', 'mipsel', 'nios2', 'or1k', 'ppc',
              'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4',
              'sh4eb', 'sparc', 'sparc64', 'tricore',
diff --git a/target/Kconfig b/target/Kconfig
index ae7f24fc66..83da0bd293 100644
--- a/target/Kconfig
+++ b/target/Kconfig
@@ -4,6 +4,7 @@ source avr/Kconfig
 source cris/Kconfig
 source hppa/Kconfig
 source i386/Kconfig
+source loongarch/Kconfig
 source m68k/Kconfig
 source microblaze/Kconfig
 source mips/Kconfig
diff --git a/target/loongarch/Kconfig b/target/loongarch/Kconfig
new file mode 100644
index 0000000000..46b26b1a85
--- /dev/null
+++ b/target/loongarch/Kconfig
@@ -0,0 +1,2 @@
+config LOONGARCH64
+    bool
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 3167323821..d3e964a4ca 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -82,6 +82,8 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
     env->pc = value;
 }
 
+#include "hw/loongarch/virt.h"
+
 void loongarch_cpu_set_irq(void *opaque, int irq, int level)
 {
     LoongArchCPU *cpu = opaque;
-- 
2.31.1



  parent reply	other threads:[~2022-04-25 10:06 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-25  9:09 [PATCH v2 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 01/43] target/loongarch: Add README Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 05/43] target/loongarch: Add fixed point shift " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 08/43] target/loongarch: Add fixed point atomic " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-04-25  9:09 ` [PATCH v2 15/43] target/loongarch: Add branch " Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-04-25 22:36   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-04-25 22:46   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-04-25 22:30   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-04-25 22:55   ` Richard Henderson
2022-04-26  9:03     ` yangxiaojuan
2022-04-26 14:52       ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-04-27  1:37   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-04-26  0:06   ` Richard Henderson
2022-04-25  9:10 ` Xiaojuan Yang [this message]
2022-04-27  1:43   ` [PATCH v2 30/43] hw/loongarch: Add support loongson3 virt machine type Richard Henderson
2022-04-25  9:10 ` [PATCH v2 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-04-27  1:49   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-04-28  8:15   ` Mark Cave-Ayland
2022-04-25  9:10 ` [PATCH v2 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-04-27  2:01   ` Richard Henderson
2022-04-28  7:40     ` Mark Cave-Ayland
2022-04-28  8:16   ` Mark Cave-Ayland
2022-04-25  9:10 ` [PATCH v2 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-04-25 16:27   ` Mark Cave-Ayland
2022-04-27 10:02     ` yangxiaojuan
2022-04-27  2:07   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-04-27  2:21   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-04-27  2:23   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 40/43] hw/loongarch: Add LoongArch ls7a acpi device support Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-04-27  2:24   ` Richard Henderson
2022-04-25  9:10 ` [PATCH v2 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-04-25  9:10 ` [PATCH v2 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang

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