From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3502CC433F5 for ; Mon, 25 Apr 2022 14:51:02 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BA1B683C79; Mon, 25 Apr 2022 16:50:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="uedZoNhh"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 062BD83C79; Mon, 25 Apr 2022 16:50:58 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D2254833D7 for ; Mon, 25 Apr 2022 16:50:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6F46961677; Mon, 25 Apr 2022 14:50:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87177C385A7; Mon, 25 Apr 2022 14:50:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1650898252; bh=T3TEwJhz15X1AUDTcWVnHjoDmW81X6qrMWi1W6zwuP4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uedZoNhhiA2sR9GD1kzRRQ2L+UJwj7y09Pl7LmeqdTTrKx/OU3EszwgtLGRcvZ/ay Hn7WcydqjM+Lxr5ryGLh1lHHRni7fB9iTHJvZI8PifcgeDU3xtWjLmy0jU+e1FNWlf VcMBk5PgzkihIJBA6mYd2f07+Kju+NPDkAyR/pbem2ZAWGERxq4zBb+olgsy7wfq/h db+tFm7OJhWkWCv7QlWFavhVd3qFSOK6aQJVd2ixX3r7SUFulY651ox+QoWPJBCQ2q smceTEWeufWLWhkBfGVC7QNBTYPOqItvTDhAIvFi6JG3IgBNmlQN2Im5W9kRwnHtt9 +fLH2+oNoGdxw== Received: by pali.im (Postfix) id 2F9544A32; Mon, 25 Apr 2022 16:50:50 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Priyanka Jain , Qiang Zhao , Shengzhou Liu , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH v2] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot Date: Mon, 25 Apr 2022 16:50:43 +0200 Message-Id: <20220425145043.9945-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20220407101624.15850-12-pali@kernel.org> References: <20220407101624.15850-12-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean All *boot env commands overrides default boot source location via i2c. After board reset without power off, BootROM then starts booting U-Boot from this specified location instead of the default one. Add new env command defboot which reverts boot location to the default value, which in most cases is configurable by HW DIP switches. And add new env commands norlowerboot, norupperboot, sd2boot to boot from other locations. norlowerboot would instruct BootROM to boot from lower NOR bank, norupperboot from upper NOR bank and sd2boot from SD card with alternative configuration. Signed-off-by: Pali Rohár --- Changes in v2: * Fix commit message * Adapt code to use p1_p2_bootsrc.h --- include/configs/p1_p2_bootsrc.h | 20 ++++++++++++++++++++ include/configs/p1_p2_rdb_pc.h | 13 +++++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h index a274c57786f5..60741ef544c0 100644 --- a/include/configs/p1_p2_bootsrc.h +++ b/include/configs/p1_p2_bootsrc.h @@ -30,6 +30,18 @@ #define RST_NOR_CMD(var, ...) "" #endif +#ifdef __SW_BOOT_NOR_BANK_LO +#define RST_NOR_LO_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_MASK)) +#else +#define RST_NOR_LO_CMD(var, ...) "" +#endif + +#ifdef __SW_BOOT_NOR_BANK_UP +#define RST_NOR_UP_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_MASK)) +#else +#define RST_NOR_UP_CMD(var, ...) "" +#endif + #ifdef __SW_BOOT_SPI #define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)) #else @@ -42,6 +54,12 @@ #define RST_SD_CMD(var, ...) "" #endif +#ifdef __SW_BOOT_SD2 +#define RST_SD2_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK)) +#else +#define RST_SD2_CMD(var, ...) "" +#endif + #ifdef __SW_BOOT_NAND #define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)) #else @@ -53,3 +71,5 @@ #else #define RST_PCIE_CMD(var, ...) "" #endif + +#define RST_DEF_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(0x00, 0xff)) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 47bd20eeeafb..50ce2d9aaed4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -25,6 +25,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -54,6 +57,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -73,6 +79,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -605,10 +614,14 @@ __VSCFW_ADDR \ MAP_NOR_LO_CMD(map_lowernorbank) \ MAP_NOR_UP_CMD(map_uppernorbank) \ RST_NOR_CMD(norboot) \ +RST_NOR_LO_CMD(norlowerboot) \ +RST_NOR_UP_CMD(norupperboot) \ RST_SPI_CMD(spiboot) \ RST_SD_CMD(sdboot) \ +RST_SD2_CMD(sd2boot) \ RST_NAND_CMD(nandboot) \ RST_PCIE_CMD(pciboot) \ +RST_DEF_CMD(defboot) \ "" #define CONFIG_USB_FAT_BOOT \ -- 2.20.1