From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C58DC433F5 for ; Tue, 26 Apr 2022 07:07:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=k8rZFUgo4ZdorU+esh5I0WCnloAdnGgKPMHQwoYM2lI=; b=F+H+jWS6uStA3V TVHs/f+CEG8ttz0OYos4SCEmsnUU00PHRGypwz6HsDsBu57+FI99Sjd2FtIP1WVwDprdthQrm0Opl L3qibSK3gjQH/AGe9RxkcXDV0eAYxXpMLyXhqISGZ2llaDijt1qtnMhLZ2zFdBxZdL9KbXssi9n/6 Ka3zSiLiA76RUB6dxOa/TDmRJpF6hiflYxwFnOlSnu4dZFbtsuieF169I7ROjy/H9pv/xyXV0jC7k o1QSY19/yRwEyMu9lunoGc5Oow3F954eEUiXE1XHW6qCiG4fpIniXHLuqTDh1MRWTwEgOi76J89dD 5wiVJ51Y2UVZWiIHCrfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njFHI-00CsDA-RC; Tue, 26 Apr 2022 07:06:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njFHF-00CsBL-H6 for linux-arm-kernel@lists.infradead.org; Tue, 26 Apr 2022 07:06:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EC7E23A; Tue, 26 Apr 2022 00:06:22 -0700 (PDT) Received: from e129167.arm.com (unknown [10.57.12.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 05D3E3F73B; Tue, 26 Apr 2022 00:06:20 -0700 (PDT) From: Michal Orzel To: catalin.marinas@arm.com, Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michal.orzel@arm.com, bertrand.marquis@arm.com Subject: [PATCH] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK Date: Tue, 26 Apr 2022 09:06:03 +0200 Message-Id: <20220426070603.56031-1-michal.orzel@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_000625_646479_0D43B6F1 X-CRM114-Status: GOOD ( 10.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Value of macro MIDR_IMPLEMENTOR_MASK exceeds the range of integer and can lead to overflow. Currently there is no issue as it is used in expressions implicitly casting it to u32. To avoid possible problems, fix the macro. Signed-off-by: Michal Orzel --- Should we also add a U suffix to ARM_CPU_IMP_* macros that are also shifted by MIDR_IMPLEMENTOR_SHIFT? None of them has bit 7 set but we could take some precaution steps. --- arch/arm64/include/asm/cputype.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index ff8f4511df71..92331c07c2d1 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -36,7 +36,7 @@ #define MIDR_VARIANT(midr) \ (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) #define MIDR_IMPLEMENTOR_SHIFT 24 -#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0B27C4332F for ; Tue, 26 Apr 2022 07:08:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343690AbiDZHLu (ORCPT ); Tue, 26 Apr 2022 03:11:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343784AbiDZHJa (ORCPT ); Tue, 26 Apr 2022 03:09:30 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C1F5637033 for ; Tue, 26 Apr 2022 00:06:22 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8EC7E23A; Tue, 26 Apr 2022 00:06:22 -0700 (PDT) Received: from e129167.arm.com (unknown [10.57.12.129]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 05D3E3F73B; Tue, 26 Apr 2022 00:06:20 -0700 (PDT) From: Michal Orzel To: catalin.marinas@arm.com, Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michal.orzel@arm.com, bertrand.marquis@arm.com Subject: [PATCH] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK Date: Tue, 26 Apr 2022 09:06:03 +0200 Message-Id: <20220426070603.56031-1-michal.orzel@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Value of macro MIDR_IMPLEMENTOR_MASK exceeds the range of integer and can lead to overflow. Currently there is no issue as it is used in expressions implicitly casting it to u32. To avoid possible problems, fix the macro. Signed-off-by: Michal Orzel --- Should we also add a U suffix to ARM_CPU_IMP_* macros that are also shifted by MIDR_IMPLEMENTOR_SHIFT? None of them has bit 7 set but we could take some precaution steps. --- arch/arm64/include/asm/cputype.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index ff8f4511df71..92331c07c2d1 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -36,7 +36,7 @@ #define MIDR_VARIANT(midr) \ (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) #define MIDR_IMPLEMENTOR_SHIFT 24 -#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) -- 2.25.1