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From: Frank Wunderlich <linux@fw-web.de>
To: linux-rockchip@lists.infradead.org
Cc: "Frank Wunderlich" <frank-w@public-files.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Johan Jonker" <jbx6244@gmail.com>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [RFC/RFT v2 09/11] dt-bindings: pci: add lane-map to rockchip PCIe binding
Date: Tue, 26 Apr 2022 15:21:37 +0200	[thread overview]
Message-ID: <20220426132139.26761-10-linux@fw-web.de> (raw)
In-Reply-To: <20220426132139.26761-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w@public-files.de>

Create new property for (rockchip) PCIe controller binding to
define lane mapping.

Rockchip driver uses this for bifurcation (true/false) based
on lanes should be splitted across controllers or not.

On rk3568 there are 2 PCIe Controllers which share 2 PCIe lanes.

pcie3x1: pcie@fe270000 //lane1 when using 1+1
pcie3x2: pcie@fe280000 //lane0 when using 1+1

This ends up in one Controller (pcie3x1) uses lane-map = <0 1>; and
the other lane-map = <1 0>; (pcie3x2)

This means there are 2 lanes (count of numbers), one (by position)
is mapped to the first controller, the other one is used on the other
controller.

In rockchip PCIe driver the lane-map is simply converted to the
bifurcation bool instead of direct mapping a specific lane to a
controller.

There is not yet any slot mapping below one controller.
But for binding this may be possible like:

lane-map = <1 2 3 3 4 4 4 4>;
            | | | ...
        lane0 | |
          lane1 |
            lane2

on a 8-lane phy.

This can map lane0 to port1 (number used at this position),
lane1 to port2, lanes 2+3 to port 3 and lanes 4,5,6,7 to port 4.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v2:
- new patch
---
 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index a992970e8b85..998b20b3a9dc 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -52,6 +52,8 @@ properties:
       - const: pclk
       - const: aux
 
+  lane-map: true
+
   msi-map: true
 
   num-lanes: true
@@ -74,8 +76,6 @@ properties:
   reset-names:
     const: pipe
 
-  bifurcation: true
-
   vpcie3v3-supply: true
 
 required:
@@ -115,6 +115,7 @@ examples:
                           "aclk_dbi", "pclk",
                           "aux";
             device_type = "pci";
+            lane-map = <0 1>;
             linux,pci-domain = <2>;
             max-link-speed = <2>;
             msi-map = <0x2000 &its 0x2000 0x1000>;
-- 
2.25.1


WARNING: multiple messages have this Message-ID
From: Frank Wunderlich <linux@fw-web.de>
To: linux-rockchip@lists.infradead.org
Cc: "Frank Wunderlich" <frank-w@public-files.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Johan Jonker" <jbx6244@gmail.com>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [RFC/RFT v2 09/11] dt-bindings: pci: add lane-map to rockchip PCIe binding
Date: Tue, 26 Apr 2022 15:21:37 +0200	[thread overview]
Message-ID: <20220426132139.26761-10-linux@fw-web.de> (raw)
In-Reply-To: <20220426132139.26761-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w@public-files.de>

Create new property for (rockchip) PCIe controller binding to
define lane mapping.

Rockchip driver uses this for bifurcation (true/false) based
on lanes should be splitted across controllers or not.

On rk3568 there are 2 PCIe Controllers which share 2 PCIe lanes.

pcie3x1: pcie@fe270000 //lane1 when using 1+1
pcie3x2: pcie@fe280000 //lane0 when using 1+1

This ends up in one Controller (pcie3x1) uses lane-map = <0 1>; and
the other lane-map = <1 0>; (pcie3x2)

This means there are 2 lanes (count of numbers), one (by position)
is mapped to the first controller, the other one is used on the other
controller.

In rockchip PCIe driver the lane-map is simply converted to the
bifurcation bool instead of direct mapping a specific lane to a
controller.

There is not yet any slot mapping below one controller.
But for binding this may be possible like:

lane-map = <1 2 3 3 4 4 4 4>;
            | | | ...
        lane0 | |
          lane1 |
            lane2

on a 8-lane phy.

This can map lane0 to port1 (number used at this position),
lane1 to port2, lanes 2+3 to port 3 and lanes 4,5,6,7 to port 4.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v2:
- new patch
---
 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index a992970e8b85..998b20b3a9dc 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -52,6 +52,8 @@ properties:
       - const: pclk
       - const: aux
 
+  lane-map: true
+
   msi-map: true
 
   num-lanes: true
@@ -74,8 +76,6 @@ properties:
   reset-names:
     const: pipe
 
-  bifurcation: true
-
   vpcie3v3-supply: true
 
 required:
@@ -115,6 +115,7 @@ examples:
                           "aclk_dbi", "pclk",
                           "aux";
             device_type = "pci";
+            lane-map = <0 1>;
             linux,pci-domain = <2>;
             max-link-speed = <2>;
             msi-map = <0x2000 &its 0x2000 0x1000>;
-- 
2.25.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID
From: Frank Wunderlich <linux@fw-web.de>
To: linux-rockchip@lists.infradead.org
Cc: "Frank Wunderlich" <frank-w@public-files.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Johan Jonker" <jbx6244@gmail.com>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [RFC/RFT v2 09/11] dt-bindings: pci: add lane-map to rockchip PCIe binding
Date: Tue, 26 Apr 2022 15:21:37 +0200	[thread overview]
Message-ID: <20220426132139.26761-10-linux@fw-web.de> (raw)
In-Reply-To: <20220426132139.26761-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w@public-files.de>

Create new property for (rockchip) PCIe controller binding to
define lane mapping.

Rockchip driver uses this for bifurcation (true/false) based
on lanes should be splitted across controllers or not.

On rk3568 there are 2 PCIe Controllers which share 2 PCIe lanes.

pcie3x1: pcie@fe270000 //lane1 when using 1+1
pcie3x2: pcie@fe280000 //lane0 when using 1+1

This ends up in one Controller (pcie3x1) uses lane-map = <0 1>; and
the other lane-map = <1 0>; (pcie3x2)

This means there are 2 lanes (count of numbers), one (by position)
is mapped to the first controller, the other one is used on the other
controller.

In rockchip PCIe driver the lane-map is simply converted to the
bifurcation bool instead of direct mapping a specific lane to a
controller.

There is not yet any slot mapping below one controller.
But for binding this may be possible like:

lane-map = <1 2 3 3 4 4 4 4>;
            | | | ...
        lane0 | |
          lane1 |
            lane2

on a 8-lane phy.

This can map lane0 to port1 (number used at this position),
lane1 to port2, lanes 2+3 to port 3 and lanes 4,5,6,7 to port 4.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v2:
- new patch
---
 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index a992970e8b85..998b20b3a9dc 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -52,6 +52,8 @@ properties:
       - const: pclk
       - const: aux
 
+  lane-map: true
+
   msi-map: true
 
   num-lanes: true
@@ -74,8 +76,6 @@ properties:
   reset-names:
     const: pipe
 
-  bifurcation: true
-
   vpcie3v3-supply: true
 
 required:
@@ -115,6 +115,7 @@ examples:
                           "aclk_dbi", "pclk",
                           "aux";
             device_type = "pci";
+            lane-map = <0 1>;
             linux,pci-domain = <2>;
             max-link-speed = <2>;
             msi-map = <0x2000 &its 0x2000 0x1000>;
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID
From: Frank Wunderlich <linux@fw-web.de>
To: linux-rockchip@lists.infradead.org
Cc: "Frank Wunderlich" <frank-w@public-files.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kishon Vijay Abraham I" <kishon@ti.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Johan Jonker" <jbx6244@gmail.com>,
	"Peter Geis" <pgwipeout@gmail.com>,
	"Michael Riesch" <michael.riesch@wolfvision.net>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [RFC/RFT v2 09/11] dt-bindings: pci: add lane-map to rockchip PCIe binding
Date: Tue, 26 Apr 2022 15:21:37 +0200	[thread overview]
Message-ID: <20220426132139.26761-10-linux@fw-web.de> (raw)
In-Reply-To: <20220426132139.26761-1-linux@fw-web.de>

From: Frank Wunderlich <frank-w@public-files.de>

Create new property for (rockchip) PCIe controller binding to
define lane mapping.

Rockchip driver uses this for bifurcation (true/false) based
on lanes should be splitted across controllers or not.

On rk3568 there are 2 PCIe Controllers which share 2 PCIe lanes.

pcie3x1: pcie@fe270000 //lane1 when using 1+1
pcie3x2: pcie@fe280000 //lane0 when using 1+1

This ends up in one Controller (pcie3x1) uses lane-map = <0 1>; and
the other lane-map = <1 0>; (pcie3x2)

This means there are 2 lanes (count of numbers), one (by position)
is mapped to the first controller, the other one is used on the other
controller.

In rockchip PCIe driver the lane-map is simply converted to the
bifurcation bool instead of direct mapping a specific lane to a
controller.

There is not yet any slot mapping below one controller.
But for binding this may be possible like:

lane-map = <1 2 3 3 4 4 4 4>;
            | | | ...
        lane0 | |
          lane1 |
            lane2

on a 8-lane phy.

This can map lane0 to port1 (number used at this position),
lane1 to port2, lanes 2+3 to port 3 and lanes 4,5,6,7 to port 4.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v2:
- new patch
---
 Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
index a992970e8b85..998b20b3a9dc 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
@@ -52,6 +52,8 @@ properties:
       - const: pclk
       - const: aux
 
+  lane-map: true
+
   msi-map: true
 
   num-lanes: true
@@ -74,8 +76,6 @@ properties:
   reset-names:
     const: pipe
 
-  bifurcation: true
-
   vpcie3v3-supply: true
 
 required:
@@ -115,6 +115,7 @@ examples:
                           "aclk_dbi", "pclk",
                           "aux";
             device_type = "pci";
+            lane-map = <0 1>;
             linux,pci-domain = <2>;
             max-link-speed = <2>;
             msi-map = <0x2000 &its 0x2000 0x1000>;
-- 
2.25.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  parent reply	other threads:[~2022-04-26 13:22 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-26 13:21 [RFC/RFT v2 00/11] RK3568 PCIe V3 support Frank Wunderlich
2022-04-26 13:21 ` Frank Wunderlich
2022-04-26 13:21 ` Frank Wunderlich
2022-04-26 13:21 ` Frank Wunderlich
2022-04-26 13:21 ` [RFC/RFT v2 01/11] dt-bindings: phy: rockchip: add PCIe v3 phy Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-28  6:33   ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-26 13:21 ` [RFC/RFT v2 02/11] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-28  6:33   ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-28  6:33     ` Krzysztof Kozlowski
2022-04-26 13:21 ` [RFC/RFT v2 03/11] dt-bindings: phy: rockchip: add PCIe v3 constants Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-28  6:34   ` Krzysztof Kozlowski
2022-04-28  6:34     ` Krzysztof Kozlowski
2022-04-28  6:34     ` Krzysztof Kozlowski
2022-04-28  6:34     ` Krzysztof Kozlowski
2022-04-28  9:27     ` Aw: " Frank Wunderlich
2022-04-28  9:27       ` Frank Wunderlich
2022-04-28  9:27       ` Frank Wunderlich
2022-04-28  9:27       ` Frank Wunderlich
2022-04-28  9:28       ` Krzysztof Kozlowski
2022-04-28  9:28         ` Krzysztof Kozlowski
2022-04-28  9:28         ` Krzysztof Kozlowski
2022-04-28  9:28         ` Krzysztof Kozlowski
2022-04-26 13:21 ` [RFC/RFT v2 04/11] phy: rockchip: Support PCIe v3 Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-28  7:38   ` Philipp Zabel
2022-04-28  7:38     ` Philipp Zabel
2022-04-28  7:38     ` Philipp Zabel
2022-04-28  7:38     ` Philipp Zabel
2022-04-26 13:21 ` [RFC/RFT v2 05/11] dt-bindings: pci: add bifurcation option to Rockchip DesignWare binding Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-28  6:37   ` Krzysztof Kozlowski
2022-04-28  6:37     ` Krzysztof Kozlowski
2022-04-28  6:37     ` Krzysztof Kozlowski
2022-04-28  6:37     ` Krzysztof Kozlowski
2022-04-28  7:25     ` Aw: " Frank Wunderlich
2022-04-28  7:25       ` Frank Wunderlich
2022-04-28  7:25       ` Frank Wunderlich
2022-04-28  7:25       ` Frank Wunderlich
2022-04-28  7:28       ` Krzysztof Kozlowski
2022-04-28  7:28         ` Krzysztof Kozlowski
2022-04-28  7:28         ` Krzysztof Kozlowski
2022-04-28  7:28         ` Krzysztof Kozlowski
2022-04-26 13:21 ` [RFC/RFT v2 06/11] PCI: rockchip-dwc: add PCIe bifurcation Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21 ` [RFC/RFT v2 07/11] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21 ` [RFC/RFT v2 08/11] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21 ` Frank Wunderlich [this message]
2022-04-26 13:21   ` [RFC/RFT v2 09/11] dt-bindings: pci: add lane-map to rockchip PCIe binding Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 16:04   ` Bjorn Helgaas
2022-04-26 16:04     ` Bjorn Helgaas
2022-04-26 16:04     ` Bjorn Helgaas
2022-04-26 16:04     ` Bjorn Helgaas
2022-04-26 17:27     ` Aw: " Frank Wunderlich
2022-04-26 17:27       ` Frank Wunderlich
2022-04-26 17:27       ` Frank Wunderlich
2022-04-26 17:27       ` Frank Wunderlich
2022-04-26 13:21 ` [RFC/RFT v2 10/11] PCI: rockchip: add a lane-map to rockchip pcie driver Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 16:07   ` Bjorn Helgaas
2022-04-26 16:07     ` Bjorn Helgaas
2022-04-26 16:07     ` Bjorn Helgaas
2022-04-26 16:07     ` Bjorn Helgaas
2022-04-26 13:21 ` [RFC/RFT v2 11/11] arm64: dts: rockchip: add basic lane-map and drop bifurcation from r2pro Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 13:21   ` Frank Wunderlich
2022-04-26 16:01 ` [RFC/RFT v2 00/11] RK3568 PCIe V3 support Bjorn Helgaas
2022-04-26 16:01   ` Bjorn Helgaas
2022-04-26 16:01   ` Bjorn Helgaas
2022-04-26 16:01   ` Bjorn Helgaas

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