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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2022 18:27:50.5682 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14544be2-a174-47d1-d49e-08da27b27889 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1197 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This data has no dependencies, so encapsulate it all within amdgpu_discovery.c. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 29 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 6 ---- drivers/gpu/drm/amd/amdgpu/soc15.c | 13 --------- 4 files changed, 14 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2e77362b32da..bbd5c2570e92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1926,11 +1926,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) adev->firmware.gpu_info_fw = NULL; if (adev->mman.discovery_bin) { - amdgpu_discovery_get_gfx_info(adev); - /* * FIXME: The bounding box is still needed by Navi12, so - * temporarily read it from gpu_info firmware. Should be droped + * temporarily read it from gpu_info firmware. Should be dropped * when DAL no longer needs it. */ if (adev->asic_type != CHIP_NAVI12) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index a676685c103c..0c359ad9fd63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1046,7 +1046,7 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) /* ================================================== */ -int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) +static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) { struct binary_header *bhdr; struct ip_discovery_header *ihdr; @@ -1212,7 +1212,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n return -EINVAL; } -void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) +static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) { int vcn_harvest_count = 0; int umc_harvest_count = 0; @@ -1257,7 +1257,7 @@ union gc_info { struct gc_info_v2_0 v2; }; -int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) +static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) { struct binary_header *bhdr; union gc_info *gc_info; @@ -1271,10 +1271,8 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) bhdr = (struct binary_header *)adev->mman.discovery_bin; offset = le16_to_cpu(bhdr->table_list[GC].offset); - if (!offset) { - dev_err(adev->dev, "invalid GC table offset\n"); - return -EINVAL; - } + if (!offset) + return 0; gc_info = (union gc_info *)(adev->mman.discovery_bin + offset); @@ -1363,10 +1361,8 @@ int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) bhdr = (struct binary_header *)adev->mman.discovery_bin; offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); - if (!offset) { - dev_err(adev->dev, "invalid mall table offset\n"); - return -EINVAL; - } + if (!offset) + return 0; mall_info = (union mall_info *)(adev->mman.discovery_bin + offset); @@ -1400,7 +1396,7 @@ union vcn_info { struct vcn_info_v1_0 v1; }; -int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) +static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) { struct binary_header *bhdr; union vcn_info *vcn_info; @@ -1420,10 +1416,8 @@ int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) bhdr = (struct binary_header *)adev->mman.discovery_bin; offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); - if (!offset) { - dev_err(adev->dev, "invalid vcn table offset\n"); - return -EINVAL; - } + if (!offset) + return 0; vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset); @@ -2037,6 +2031,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) return -EINVAL; amdgpu_discovery_harvest_ip(adev); + amdgpu_discovery_get_gfx_info(adev); + amdgpu_discovery_get_mall_info(adev); + amdgpu_discovery_get_vcn_info(adev); break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 3735c535d27d..8563dd4a7dc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -28,14 +28,8 @@ #define DISCOVERY_TMR_OFFSET (64 << 10) void amdgpu_discovery_fini(struct amdgpu_device *adev); -int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev); -void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev); int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance, int *major, int *minor, int *revision); - -int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev); -int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev); -int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev); int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); #endif /* __AMDGPU_DISCOVERY__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 3ee7322081d2..fde6154f2009 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -701,25 +701,12 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) static void soc15_reg_base_init(struct amdgpu_device *adev) { - int r; - /* Set IP register base before any HW register access */ switch (adev->asic_type) { case CHIP_VEGA10: case CHIP_VEGA12: case CHIP_RAVEN: - vega10_reg_base_init(adev); - break; case CHIP_RENOIR: - /* It's safe to do ip discovery here for Renoir, - * it doesn't support SRIOV. */ - if (amdgpu_discovery) { - r = amdgpu_discovery_reg_base_init(adev); - if (r == 0) - break; - DRM_WARN("failed to init reg base from ip discovery table, " - "fallback to legacy init method\n"); - } vega10_reg_base_init(adev); break; case CHIP_VEGA20: -- 2.35.1