[PATCH 01/11] drm/amdgpu: update latest IP discovery table structures

* [PATCH 01/11] drm/amdgpu: update latest IP discovery table structures
@ 2022-04-26 18:27 Alex Deucher
  2022-04-26 18:27 ` [PATCH 02/11] drm/amdgpu/discovery: populate additional GC info Alex Deucher
                   ` (10 more replies)
  0 siblings, 11 replies; 13+ messages in thread
From: Alex Deucher @ 2022-04-26 18:27 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

Add new tables.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/discovery.h | 114 +++++++++++++++++++++++-
 1 file changed, 111 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h
index b25026c3ec96..f150404ffc68 100644
--- a/drivers/gpu/drm/amd/include/discovery.h
+++ b/drivers/gpu/drm/amd/include/discovery.h
@@ -27,15 +27,19 @@
 #define PSP_HEADER_SIZE                 256
 #define BINARY_SIGNATURE                0x28211407
 #define DISCOVERY_TABLE_SIGNATURE       0x53445049
+#define GC_TABLE_ID                     0x4347
+#define HARVEST_TABLE_SIGNATURE         0x56524148
+#define VCN_INFO_TABLE_ID               0x004E4356
+#define MALL_INFO_TABLE_ID              0x4D414C4C
 
 typedef enum
 {
 	IP_DISCOVERY = 0,
 	GC,
 	HARVEST_INFO,
-	TABLE_4,
+	VCN_INFO,
+	MALL_INFO,
 	RESERVED_1,
-	RESERVED_2,
 	TOTAL_TABLES = 6
 } table;
 
@@ -96,6 +100,24 @@ typedef struct ip
 	uint32_t base_address[]; /* variable number of Addresses */
 } ip;
 
+typedef struct ip_v3
+{
+	uint16_t hw_id;                         /* Hardware ID */
+	uint8_t instance_number;                /* Instance number for the IP */
+	uint8_t num_base_address;               /* Number of base addresses*/
+	uint8_t major;                          /* Hardware ID.major version */
+	uint8_t minor;                          /* Hardware ID.minor version */
+	uint8_t revision;                       /* Hardware ID.revision version */
+#if defined(__BIG_ENDIAN)
+	uint8_t variant : 4;                    /* HW variant */
+	uint8_t sub_revision : 4;               /* HCID Sub-Revision */
+#else
+	uint8_t sub_revision : 4;               /* HCID Sub-Revision */
+	uint8_t variant : 4;                    /* HW variant */
+#endif
+	uint32_t base_address[1];               /* Base Address list. Corresponds to the num_base_address field*/
+} ip_v3;
+
 typedef struct die_header
 {
 	uint16_t die_id;
@@ -108,7 +130,11 @@ typedef struct ip_structure
 	struct die
 	{
 		die_header *die_header;
-		ip *ip_list;
+		union
+		{
+			ip *ip_list;
+			ip_v3 *ip_v3_list;
+		};                                  /* IP list. Variable size*/
 	} die;
 } ip_structure;
 
@@ -170,6 +196,40 @@ struct gc_info_v1_1 {
 	uint32_t gc_num_tcps;
 };
 
+struct gc_info_v1_2 {
+	struct gpu_info_header header;
+	uint32_t gc_num_se;
+	uint32_t gc_num_wgp0_per_sa;
+	uint32_t gc_num_wgp1_per_sa;
+	uint32_t gc_num_rb_per_se;
+	uint32_t gc_num_gl2c;
+	uint32_t gc_num_gprs;
+	uint32_t gc_num_max_gs_thds;
+	uint32_t gc_gs_table_depth;
+	uint32_t gc_gsprim_buff_depth;
+	uint32_t gc_parameter_cache_depth;
+	uint32_t gc_double_offchip_lds_buffer;
+	uint32_t gc_wave_size;
+	uint32_t gc_max_waves_per_simd;
+	uint32_t gc_max_scratch_slots_per_cu;
+	uint32_t gc_lds_size;
+	uint32_t gc_num_sc_per_se;
+	uint32_t gc_num_sa_per_se;
+	uint32_t gc_num_packer_per_sc;
+	uint32_t gc_num_gl2a;
+	uint32_t gc_num_tcp_per_sa;
+	uint32_t gc_num_sdp_interface;
+	uint32_t gc_num_tcps;
+	uint32_t gc_num_tcp_per_wpg;
+	uint32_t gc_tcp_l1_size;
+	uint32_t gc_num_sqc_per_wgp;
+	uint32_t gc_l1_instruction_cache_size_per_sqc;
+	uint32_t gc_l1_data_cache_size_per_sqc;
+	uint32_t gc_gl1c_per_sa;
+	uint32_t gc_gl1c_size_per_instance;
+	uint32_t gc_gl2c_per_gpu;
+};
+
 struct gc_info_v2_0 {
 	struct gpu_info_header header;
 
@@ -208,6 +268,54 @@ typedef struct harvest_table {
 	harvest_info list[32];
 } harvest_table;
 
+struct mall_info_header {
+	uint32_t table_id; /* table ID */
+	uint16_t version_major; /* table version */
+	uint16_t version_minor; /* table version */
+	uint32_t size_bytes; /* size of the entire header+data in bytes */
+};
+
+struct mall_info_v1_0 {
+	struct mall_info_header header;
+	uint32_t mall_size_per_m;
+	uint32_t m_s_present;
+	uint32_t m_half_use;
+	uint32_t m_mall_config;
+	uint32_t reserved[5];
+};
+
+#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
+
+struct vcn_info_header {
+    uint32_t table_id; /* table ID */
+    uint16_t version_major; /* table version */
+    uint16_t version_minor; /* table version */
+    uint32_t size_bytes; /* size of the entire header+data in bytes */
+};
+
+struct vcn_instance_info_v1_0
+{
+	uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
+	union _fuse_data {
+		struct {
+			uint32_t av1_disabled : 1;
+			uint32_t vp9_disabled : 1;
+			uint32_t hevc_disabled : 1;
+			uint32_t h264_disabled : 1;
+			uint32_t reserved : 28;
+		} bits;
+		uint32_t all_bits;
+	} fuse_data;
+	uint32_t reserved[2];
+};
+
+struct vcn_info_v1_0 {
+	struct vcn_info_header header;
+	uint32_t num_of_instances; /* number of entries used in instance_info below*/
+	struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
+	uint32_t reserved[4];
+};
+
 #pragma pack()
 
 #endif
-- 
2.35.1


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