From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53604C433F5 for ; Wed, 27 Apr 2022 04:53:10 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 679C083A95; Wed, 27 Apr 2022 06:53:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B9Og4f2s"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id ADED683937; Wed, 27 Apr 2022 06:53:03 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 709B583A95 for ; Wed, 27 Apr 2022 06:52:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=tien.fong.chee@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651035179; x=1682571179; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=D/u/swOsiYRers20U4Jgj95jSFqrlso4Ut6JVr29kzI=; b=B9Og4f2sj2fBhdYoMzAeDbvW5XnNFoPugq4fu7jLYDB5evwCJB2YOWSg sTS1enVFkOhXDcj4baFa4arvlBcnGCE4lI8kpsYLI7dOTUl7XXS2E32mG vsgdr+jwc9hYEcncT+O5E81Vx0lMx936ul+ahszUfzhxT6x89hib+o1eG TGrNR0AKgPLVjaZI0JyCLgh4IGLv85Pys1G4Jw6B1MArfO+giZILy6otT ZUlakw1WyC6x1X6UNhZ5q+B7tC5VKChYNjJe6g97nm6rRjbJNcZfS1OyH IGlEFauJJ1jU60JITjCuVVL3cMjwO+B3PvkjN0eZFwD4dJW9f8PifgmOT A==; X-IronPort-AV: E=McAfee;i="6400,9594,10329"; a="352251896" X-IronPort-AV: E=Sophos;i="5.90,292,1643702400"; d="scan'208";a="352251896" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2022 21:52:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,292,1643702400"; d="scan'208";a="596100356" Received: from pglc1230.png.intel.com ([10.221.139.25]) by orsmga001.jf.intel.com with ESMTP; 26 Apr 2022 21:52:54 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Kok Kiang , Yau Wai , Sin Hui , Raaj , Dinesh , Tien Fong Chee Subject: [PATCH] ddr: altera: Stratix10: Use phys_size_t for memory size Date: Wed, 27 Apr 2022 12:52:42 +0800 Message-Id: <20220427045242.9974-1-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean From: Tien Fong Chee Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d3a6d21860..4d36fb4533 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation * */ @@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(plat); + phys_size_t size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; -- 2.19.0