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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id o6-20020a05600c378600b0038eca3cdbb3sm1646899wmr.13.2022.04.27.07.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 07:27:04 -0700 (PDT) From: Daniel Thompson To: Marc Zyngier , Thomas Gleixner Cc: Daniel Thompson , Catalin Marinas , Will Deacon , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] irqchip/exiu: Fix acknowledgment of edge triggered interrupts Date: Wed, 27 Apr 2022 15:26:47 +0100 Message-Id: <20220427142647.1736658-1-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently the EXIU uses the fasteoi interrupt flow that is configured by it's parent (irq-gic-v3.c). With this flow the only chance to clear the interrupt request happens during .irq_eoi() and (obviously) this happens after the interrupt handler has run. EXIU requires edge triggered interrupts to be acked prior to interrupt handling. Without this we risk incorrect interrupt dismissal when a new interrupt is delivered after the handler reads and acknowledges the peripheral but before the irq_eoi() takes place. Fix this by clearing the interrupt request from .irq_ack() instead. This requires switching to the fasteoi-ack flow instead of the fasteoi flow. This approach is inspired by the nmi code found in irq-sun6i-r.c . Note: It *is* intentional not to call irq_chip_ack_parent() from exiu_irq_ack(). Parents that implement the fasteoi-ack flow don't want us to do that (and we'd crash if we tried). This problem was discovered through code review rather then reproducing missed interrupts in a real platform. Nevertheless the change has been tested for regression on a Developerbox/SC2A11 using the power button (which is edge triggered and is the only thing connected to the EXIU on this platform). Fixes: 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") Signed-off-by: Daniel Thompson --- arch/arm64/Kconfig.platforms | 1 + drivers/irqchip/irq-sni-exiu.c | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..aaeaf57c8222 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -253,6 +253,7 @@ config ARCH_INTEL_SOCFPGA config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" + select IRQ_FASTEOI_HIERARCHY_HANDLERS config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index abd011fcecf4..1cc2ec272ebd 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -37,12 +37,11 @@ struct exiu_irq_data { u32 spi_base; }; -static void exiu_irq_eoi(struct irq_data *d) +static void exiu_irq_ack(struct irq_data *d) { struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); writel(BIT(d->hwirq), data->base + EIREQCLR); - irq_chip_eoi_parent(d); } static void exiu_irq_mask(struct irq_data *d) @@ -104,7 +103,8 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) static struct irq_chip exiu_irq_chip = { .name = "EXIU", - .irq_eoi = exiu_irq_eoi, + .irq_ack = exiu_irq_ack, + .irq_eoi = irq_chip_eoi_parent, .irq_enable = exiu_irq_enable, .irq_mask = exiu_irq_mask, .irq_unmask = exiu_irq_unmask, @@ -148,6 +148,7 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct irq_fwspec parent_fwspec; struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; + int i, ret; parent_fwspec = *fwspec; if (is_of_node(dom->parent->fwnode)) { @@ -165,7 +166,14 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); parent_fwspec.fwnode = dom->parent->fwnode; - return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + ret = irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_set_handler(virq+i, handle_fasteoi_ack_irq); + + return 0; } static const struct irq_domain_ops exiu_domain_ops = { base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64386C433F5 for ; Wed, 27 Apr 2022 14:28:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; 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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id o6-20020a05600c378600b0038eca3cdbb3sm1646899wmr.13.2022.04.27.07.27.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 07:27:04 -0700 (PDT) From: Daniel Thompson To: Marc Zyngier , Thomas Gleixner Cc: Daniel Thompson , Catalin Marinas , Will Deacon , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] irqchip/exiu: Fix acknowledgment of edge triggered interrupts Date: Wed, 27 Apr 2022 15:26:47 +0100 Message-Id: <20220427142647.1736658-1-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220427_072712_473416_E7174ECC X-CRM114-Status: GOOD ( 22.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the EXIU uses the fasteoi interrupt flow that is configured by it's parent (irq-gic-v3.c). With this flow the only chance to clear the interrupt request happens during .irq_eoi() and (obviously) this happens after the interrupt handler has run. EXIU requires edge triggered interrupts to be acked prior to interrupt handling. Without this we risk incorrect interrupt dismissal when a new interrupt is delivered after the handler reads and acknowledges the peripheral but before the irq_eoi() takes place. Fix this by clearing the interrupt request from .irq_ack() instead. This requires switching to the fasteoi-ack flow instead of the fasteoi flow. This approach is inspired by the nmi code found in irq-sun6i-r.c . Note: It *is* intentional not to call irq_chip_ack_parent() from exiu_irq_ack(). Parents that implement the fasteoi-ack flow don't want us to do that (and we'd crash if we tried). This problem was discovered through code review rather then reproducing missed interrupts in a real platform. Nevertheless the change has been tested for regression on a Developerbox/SC2A11 using the power button (which is edge triggered and is the only thing connected to the EXIU on this platform). Fixes: 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") Signed-off-by: Daniel Thompson --- arch/arm64/Kconfig.platforms | 1 + drivers/irqchip/irq-sni-exiu.c | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..aaeaf57c8222 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -253,6 +253,7 @@ config ARCH_INTEL_SOCFPGA config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" + select IRQ_FASTEOI_HIERARCHY_HANDLERS config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index abd011fcecf4..1cc2ec272ebd 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -37,12 +37,11 @@ struct exiu_irq_data { u32 spi_base; }; -static void exiu_irq_eoi(struct irq_data *d) +static void exiu_irq_ack(struct irq_data *d) { struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); writel(BIT(d->hwirq), data->base + EIREQCLR); - irq_chip_eoi_parent(d); } static void exiu_irq_mask(struct irq_data *d) @@ -104,7 +103,8 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) static struct irq_chip exiu_irq_chip = { .name = "EXIU", - .irq_eoi = exiu_irq_eoi, + .irq_ack = exiu_irq_ack, + .irq_eoi = irq_chip_eoi_parent, .irq_enable = exiu_irq_enable, .irq_mask = exiu_irq_mask, .irq_unmask = exiu_irq_unmask, @@ -148,6 +148,7 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct irq_fwspec parent_fwspec; struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; + int i, ret; parent_fwspec = *fwspec; if (is_of_node(dom->parent->fwnode)) { @@ -165,7 +166,14 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); parent_fwspec.fwnode = dom->parent->fwnode; - return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + ret = irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + irq_set_handler(virq+i, handle_fasteoi_ack_irq); + + return 0; } static const struct irq_domain_ops exiu_domain_ops = { base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel