From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5566C433EF for ; Thu, 28 Apr 2022 10:49:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343942AbiD1Kw1 (ORCPT ); Thu, 28 Apr 2022 06:52:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231765AbiD1Kw0 (ORCPT ); Thu, 28 Apr 2022 06:52:26 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85C8189321 for ; Thu, 28 Apr 2022 03:49:12 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3FB9CB82919 for ; Thu, 28 Apr 2022 10:49:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C33B6C385A9; Thu, 28 Apr 2022 10:49:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651142950; bh=3AM7hjMP5FZp+VYPxxlIsZyIgjgdKYMnzPk2OZ7fWik=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lzqcmZxRjBXAmnpf3HE3/Px6ORmTvynmeErUOAAHE2PAT1d76SYPqe4sauqX20Ml+ kJ3fTMlJl2nwl8vsz2rEDD3GXKT7s02T+rsdFgKVAHWu0lrvcBgpfMCFg24n7XOtjF erGy21ZVROw0Xh/X9CilPe6RGYHjxrxq5SOvUUL2gqTVmuevyr1q9v3ntSUDXiyru7 DMtRTWc7Ymft0cnT0Fb3zON51SLzCKoGtSXBTPEpqylCpPf3MqK2P1ySALgPTAmFo0 VtfVcRP3rih/oLchzKnofLXwCqsqogNnxMUrpbPrBPK9nuQIXwLQ/vNaqMHAD2K0CA uQbcG5oKvThQg== Date: Thu, 28 Apr 2022 11:49:05 +0100 From: Will Deacon To: Mark Rutland Cc: Marco Elver , Kefeng Wang , catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: kcsan: Fix kcsan test_barrier fail and panic Message-ID: <20220428104904.GB14515@willie-the-truck> References: <20220426081700.1376542-1-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 26, 2022 at 01:50:39PM +0100, Mark Rutland wrote: > On Tue, Apr 26, 2022 at 02:10:06PM +0200, Marco Elver wrote: > > On Tue, Apr 26, 2022 at 08:17AM +0000, Kefeng Wang wrote: > > > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > > > index fd7e8fbaeef1..18863c50e9ce 100644 > > > --- a/include/asm-generic/barrier.h > > > +++ b/include/asm-generic/barrier.h > > > @@ -38,6 +38,10 @@ > > > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > > > #endif > > > > > > +#ifdef __dma_mb > > > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > > > +#endif > > > + > > > > So it looks like arm64 is the only arch that defines dma_mb(). By adding > > it to asm-generic, we'd almost be encouraging other architectures to add > > it, which I don't know we want. > > > > Documentation/memory-barriers.txt doesn't mention dma_mb() either - so > > perhaps dma_mb() doesn't belong in asm-generic/barrier.h, and you could > > only change arm64's definition of dma_mb() to add the kcsan_mb(). > > > > Preferences? Maybe arch64 maintainers have more background on why arm64 > > is an anomaly here. > > Looking around, there's a single user: > > [mark@lakrids:~/src/linux]% git grep -w dma_mb > arch/arm64/include/asm/barrier.h:#define dma_mb() dmb(osh) > arch/arm64/include/asm/io.h:#define __iomb() dma_mb() > > [mark@lakrids:~/src/linux]% git grep -w __iomb > arch/arm64/include/asm/io.h:#define __iomb() dma_mb() > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: __iomb(); > > ... and that was introduced in commit: > > a76a37777f2c936b ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer") > > ... where it is used to ensure that prior (read and write) accesses to > memory by a CPU are ordered w.r.t. a subsequent MMIO write. > > That seems like it could be a generic shape of problem (especially for > IOMMUs), even if arm64 is the only architecture with an implementation > today. From my PoV it would weem to make sense as a generic thing, and > should probably be added to Documentation/memory-barriers.txt. > > Will, thoughts? Given that the read and write variants are generic, making the full-fat version version as well makes sense to me. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46E94C433EF for ; Thu, 28 Apr 2022 10:50:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hj3kRrl/G8XgIE34uySdSLzWw8Qfs44IpAkukTW7zng=; b=Yf+Cmj0d6+2EC4 s2wP2/AQA4E5GdfVK9q4RBar7tkQtNl2Zj5xnLpoPXhOfUBAZTIZxIKHg8bw9HOwu+nwTzc25zw5y +zjO/kt7LOa9UsD0Jc+gUCjPTMCtBiaEvmzQFcCGDMmDlg1Q9e/fOhuBLCNhgjoNDPTOugWxqVuCp 2cH61MyMJn1C0jAhafA0FxJrD1GWbZTsk6zailowOWXpmmtYHJN6vPRT3nsyNUwEf0AY/sYCvcWK2 M89hLYBNEXJPy0ocnUiq0OCA3lkYtxSecEjp2BoDDuj5tJEh88mf+ZEYio12fYpOe8of8tyPcaeMb CQLD/Edmp4vGHhNCph4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nk1hy-006FzK-Qt; Thu, 28 Apr 2022 10:49:14 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nk1hv-006Fwf-D9 for linux-arm-kernel@lists.infradead.org; Thu, 28 Apr 2022 10:49:12 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B90FB61E73; Thu, 28 Apr 2022 10:49:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C33B6C385A9; Thu, 28 Apr 2022 10:49:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651142950; bh=3AM7hjMP5FZp+VYPxxlIsZyIgjgdKYMnzPk2OZ7fWik=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lzqcmZxRjBXAmnpf3HE3/Px6ORmTvynmeErUOAAHE2PAT1d76SYPqe4sauqX20Ml+ kJ3fTMlJl2nwl8vsz2rEDD3GXKT7s02T+rsdFgKVAHWu0lrvcBgpfMCFg24n7XOtjF erGy21ZVROw0Xh/X9CilPe6RGYHjxrxq5SOvUUL2gqTVmuevyr1q9v3ntSUDXiyru7 DMtRTWc7Ymft0cnT0Fb3zON51SLzCKoGtSXBTPEpqylCpPf3MqK2P1ySALgPTAmFo0 VtfVcRP3rih/oLchzKnofLXwCqsqogNnxMUrpbPrBPK9nuQIXwLQ/vNaqMHAD2K0CA uQbcG5oKvThQg== Date: Thu, 28 Apr 2022 11:49:05 +0100 From: Will Deacon To: Mark Rutland Cc: Marco Elver , Kefeng Wang , catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: kcsan: Fix kcsan test_barrier fail and panic Message-ID: <20220428104904.GB14515@willie-the-truck> References: <20220426081700.1376542-1-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220428_034911_505548_F4FC156E X-CRM114-Status: GOOD ( 24.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 26, 2022 at 01:50:39PM +0100, Mark Rutland wrote: > On Tue, Apr 26, 2022 at 02:10:06PM +0200, Marco Elver wrote: > > On Tue, Apr 26, 2022 at 08:17AM +0000, Kefeng Wang wrote: > > > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > > > index fd7e8fbaeef1..18863c50e9ce 100644 > > > --- a/include/asm-generic/barrier.h > > > +++ b/include/asm-generic/barrier.h > > > @@ -38,6 +38,10 @@ > > > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > > > #endif > > > > > > +#ifdef __dma_mb > > > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > > > +#endif > > > + > > > > So it looks like arm64 is the only arch that defines dma_mb(). By adding > > it to asm-generic, we'd almost be encouraging other architectures to add > > it, which I don't know we want. > > > > Documentation/memory-barriers.txt doesn't mention dma_mb() either - so > > perhaps dma_mb() doesn't belong in asm-generic/barrier.h, and you could > > only change arm64's definition of dma_mb() to add the kcsan_mb(). > > > > Preferences? Maybe arch64 maintainers have more background on why arm64 > > is an anomaly here. > > Looking around, there's a single user: > > [mark@lakrids:~/src/linux]% git grep -w dma_mb > arch/arm64/include/asm/barrier.h:#define dma_mb() dmb(osh) > arch/arm64/include/asm/io.h:#define __iomb() dma_mb() > > [mark@lakrids:~/src/linux]% git grep -w __iomb > arch/arm64/include/asm/io.h:#define __iomb() dma_mb() > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: __iomb(); > > ... and that was introduced in commit: > > a76a37777f2c936b ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer") > > ... where it is used to ensure that prior (read and write) accesses to > memory by a CPU are ordered w.r.t. a subsequent MMIO write. > > That seems like it could be a generic shape of problem (especially for > IOMMUs), even if arm64 is the only architecture with an implementation > today. From my PoV it would weem to make sense as a generic thing, and > should probably be added to Documentation/memory-barriers.txt. > > Will, thoughts? Given that the read and write variants are generic, making the full-fat version version as well makes sense to me. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel