From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, richard.henderson@linaro.org,
gaosong@loongson.cn
Subject: [PATCH v3 15/43] target/loongarch: Add branch instruction translation
Date: Fri, 29 Apr 2022 18:07:01 +0800 [thread overview]
Message-ID: <20220429100729.1572481-16-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <20220429100729.1572481-1-yangxiaojuan@loongson.cn>
From: Song Gao <gaosong@loongson.cn>
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
.../loongarch/insn_trans/trans_branch.c.inc | 83 +++++++++++++++++++
target/loongarch/insns.decode | 28 +++++++
target/loongarch/translate.c | 1 +
3 files changed, 112 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_branch.c.inc
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
new file mode 100644
index 0000000000..65dbdff41e
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static bool trans_b(DisasContext *ctx, arg_b *a)
+{
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_bl(DisasContext *ctx, arg_bl *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ tcg_gen_addi_tl(cpu_pc, src1, a->offs);
+ tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+ tcg_gen_lookup_and_goto_ptr();
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
+ target_long offs, TCGCond cond)
+{
+ TCGLabel *l = gen_new_label();
+ tcg_gen_brcond_tl(cond, src1, src2, l);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static bool gen_rr_bc(DisasContext *ctx, arg_rr_offs *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
+
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+static bool gen_rz_bc(DisasContext *ctx, arg_r_offs *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = tcg_constant_tl(0);
+
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_constant_tl(0);
+
+ tcg_gen_ld8u_tl(src1, cpu_env,
+ offsetof(CPULoongArchState, cf[a->cj]));
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+TRANS(beq, gen_rr_bc, TCG_COND_EQ)
+TRANS(bne, gen_rr_bc, TCG_COND_NE)
+TRANS(blt, gen_rr_bc, TCG_COND_LT)
+TRANS(bge, gen_rr_bc, TCG_COND_GE)
+TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
+TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
+TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
+TRANS(bnez, gen_rz_bc, TCG_COND_NE)
+TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
+TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8f286e7233..9b293dfdf9 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -10,6 +10,9 @@
#
%i14s2 10:s14 !function=shl_2
%sa2p1 15:2 !function=plus_1
+%offs21 0:s5 10:16 !function=shl_2
+%offs16 10:s16 !function=shl_2
+%offs26 0:s10 10:16 !function=shl_2
#
# Argument sets
@@ -38,6 +41,10 @@
&rc rd cj
&frr fd rj rk
&fr_i fd rj imm
+&r_offs rj offs
+&c_offs cj offs
+&offs offs
+&rr_offs rj rd offs
#
# Formats
@@ -74,6 +81,10 @@
@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
+@r_offs21 .... .. ................ rj:5 ..... &r_offs offs=%offs21
+@c_offs21 .... .. ................ .. cj:3 ..... &c_offs offs=%offs21
+@offs26 .... .. .......................... &offs offs=%offs26
+@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs offs=%offs16
#
# Fixed point arithmetic operation instruction
@@ -409,3 +420,20 @@ fstgt_s 0011 10000111 01100 ..... ..... ..... @frr
fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
fstle_s 0011 10000111 01110 ..... ..... ..... @frr
fstle_d 0011 10000111 01111 ..... ..... ..... @frr
+
+#
+# Branch instructions
+#
+beqz 0100 00 ................ ..... ..... @r_offs21
+bnez 0100 01 ................ ..... ..... @r_offs21
+bceqz 0100 10 ................ 00 ... ..... @c_offs21
+bcnez 0100 10 ................ 01 ... ..... @c_offs21
+jirl 0100 11 ................ ..... ..... @rr_offs16
+b 0101 00 .......................... @offs26
+bl 0101 01 .......................... @offs26
+beq 0101 10 ................ ..... ..... @rr_offs16
+bne 0101 11 ................ ..... ..... @rr_offs16
+blt 0110 00 ................ ..... ..... @rr_offs16
+bge 0110 01 ................ ..... ..... @rr_offs16
+bltu 0110 10 ................ ..... ..... @rr_offs16
+bgeu 0110 11 ................ ..... ..... @rr_offs16
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 6a3fffdbe0..e850c55b0c 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -171,6 +171,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_fcnv.c.inc"
#include "insn_trans/trans_fmov.c.inc"
#include "insn_trans/trans_fmemory.c.inc"
+#include "insn_trans/trans_branch.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
2.31.1
next prev parent reply other threads:[~2022-04-29 10:21 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 10:06 [PATCH v3 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 01/43] target/loongarch: Add README Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-05-09 20:29 ` Richard Henderson
2022-05-10 12:01 ` yangxiaojuan
2022-04-29 10:06 ` [PATCH v3 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 05/43] target/loongarch: Add fixed point shift " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 08/43] target/loongarch: Add fixed point atomic " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-04-29 10:06 ` [PATCH v3 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-04-29 10:07 ` Xiaojuan Yang [this message]
2022-04-29 10:07 ` [PATCH v3 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-04-30 17:22 ` Richard Henderson
2022-05-05 7:22 ` yangxiaojuan
2022-04-29 10:07 ` [PATCH v3 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-04-30 17:35 ` Richard Henderson
2022-04-29 10:07 ` [PATCH v3 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 30/43] hw/loongarch: Add support loongson3 virt machine type Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-04-30 17:41 ` Richard Henderson
2022-04-29 10:07 ` [PATCH v3 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-05-07 15:31 ` Richard Henderson
2022-05-09 9:38 ` yangxiaojuan
2022-05-09 17:56 ` Richard Henderson
2022-05-09 18:04 ` Peter Maydell
2022-05-09 18:25 ` Richard Henderson
2022-05-10 2:54 ` maobibo
2022-05-10 3:11 ` maobibo
2022-05-10 3:56 ` Richard Henderson
2022-05-10 9:13 ` maobibo
2022-05-11 9:54 ` yangxiaojuan
2022-05-11 14:14 ` Richard Henderson
2022-05-12 1:58 ` maobibo
2022-05-13 8:41 ` yangxiaojuan
2022-05-13 8:27 ` yangxiaojuan
2022-05-09 10:14 ` yangxiaojuan
2022-04-29 10:07 ` [PATCH v3 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-05-07 21:55 ` Richard Henderson
2022-05-10 9:11 ` yangxiaojuan
2022-05-10 15:09 ` Richard Henderson
2022-04-29 10:07 ` [PATCH v3 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-05-07 22:08 ` Richard Henderson
2022-04-29 10:07 ` [PATCH v3 40/43] hw/loongarch: Add LoongArch ls7a acpi device support Xiaojuan Yang
2022-05-09 18:01 ` Richard Henderson
2022-04-29 10:07 ` [PATCH v3 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-04-29 10:07 ` [PATCH v3 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang
2022-05-05 7:32 ` [PATCH v3 00/43] Add LoongArch softmmu support yangxiaojuan
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