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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id l5-20020adfa385000000b0020adb3ae75dsm2913406wrb.3.2022.04.29.09.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 09:53:17 -0700 (PDT) From: Daniel Thompson To: Marc Zyngier , Thomas Gleixner Cc: Daniel Thompson , Catalin Marinas , Will Deacon , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] irqchip/exiu: Fix acknowledgment of edge triggered interrupts Date: Fri, 29 Apr 2022 17:53:14 +0100 Message-Id: <20220429165314.2343705-1-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently the EXIU uses the fasteoi interrupt flow that is configured by it's parent (irq-gic-v3.c). With this flow the only chance to clear the interrupt request happens during .irq_eoi() and (obviously) this happens after the interrupt handler has run. EXIU requires edge triggered interrupts to be acked prior to interrupt handling. Without this we risk incorrect interrupt dismissal when a new interrupt is delivered after the handler reads and acknowledges the peripheral but before the irq_eoi() takes place. Fix this by clearing the interrupt request from .irq_ack() if we are configured for edge triggered interrupts. This requires adopting the fasteoi-ack flow instead of the fasteoi to ensure the ack gets called. These changes have been tested using the power button on a Developerbox/SC2A11 combined with some hackery in gpio-keys so I can play with the different trigger mode (and an mdelay(500) so I can can check what happens on a double click in both modes. Fixes: 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") Signed-off-by: Daniel Thompson --- Notes: Changes in v2: * Switch to dynamic selection of handle_fasteoi_irq and handle_fasteoi_ack_irq and reintroduce exiu_irq_eoi() since we need that for level triggered interrupts (Ard B). * Above changes mean we are no longer using sun6i NMI code as a template to tidy up the description accordingly. arch/arm64/Kconfig.platforms | 1 + drivers/irqchip/irq-sni-exiu.c | 33 +++++++++++++++++++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..aaeaf57c8222 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -253,6 +253,7 @@ config ARCH_INTEL_SOCFPGA config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" + select IRQ_FASTEOI_HIERARCHY_HANDLERS config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index abd011fcecf4..651a82dead01 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -37,11 +37,20 @@ struct exiu_irq_data { u32 spi_base; }; -static void exiu_irq_eoi(struct irq_data *d) +static void exiu_irq_ack(struct irq_data *d) { struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); writel(BIT(d->hwirq), data->base + EIREQCLR); +} + +static void exiu_irq_eoi(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 edge_triggered = readl_relaxed(data->base + EIEDG); + + if (!(edge_triggered & BIT(d->hwirq))) + writel(BIT(d->hwirq), data->base + EIREQCLR); irq_chip_eoi_parent(d); } @@ -91,10 +100,13 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) writel_relaxed(val, data->base + EILVL); val = readl_relaxed(data->base + EIEDG); - if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) { val &= ~BIT(d->hwirq); - else + irq_set_handler_locked(d, handle_fasteoi_irq); + } else { val |= BIT(d->hwirq); + irq_set_handler_locked(d, handle_fasteoi_ack_irq); + } writel_relaxed(val, data->base + EIEDG); writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); @@ -104,6 +116,7 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) static struct irq_chip exiu_irq_chip = { .name = "EXIU", + .irq_ack = exiu_irq_ack, .irq_eoi = exiu_irq_eoi, .irq_enable = exiu_irq_enable, .irq_mask = exiu_irq_mask, @@ -148,6 +161,8 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct irq_fwspec parent_fwspec; struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; + int i, ret; + u32 edge_triggered; parent_fwspec = *fwspec; if (is_of_node(dom->parent->fwnode)) { @@ -165,7 +180,17 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); parent_fwspec.fwnode = dom->parent->fwnode; - return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + ret = irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + if (ret) + return ret; + + edge_triggered = readl_relaxed(info->base + EIEDG); + for (i = 0; i < nr_irqs; i++) + irq_set_handler(virq + i, edge_triggered & BIT(i) ? + handle_fasteoi_ack_irq : + handle_fasteoi_irq); + + return 0; } static const struct irq_domain_ops exiu_domain_ops = { base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3870FC433F5 for ; Fri, 29 Apr 2022 16:54:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=fsINgfJ7busJ3pbPZgSgBDKcE4d2H0DFpZz3TtFSb1E=; b=4/AKnDgu/zxuTI hRRzfPlCZIPgiiLITtbH5i5Qilj7fGpUSyqmerRFk3bP/sri5W6+wstyQZQsXMpAhK79iejz/WAV5 KyvRHvwXtjiNCqyaZQhji6C4TziAtk+/cg+QI8YO6lexKhv4LmnU9/5Vi5sEfvhlgw2XkaylG+Yjo qqY4X7mn31NonTf9LMOCgn29kIxvZYzTy8CawvLQOxJc1zFek5Fl+Cx5/l4PuDyR3ViE2VvuXXdFt vVtyLCDgZVf+khGmCdkaee6wh/0UEYrmGOHbA+R+l/fL6BUyP5f132o4izNAJaIKUphNI1MKW5Bcf E+xxm5a+fw5npwDLDhhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkTry-00C19k-2H; Fri, 29 Apr 2022 16:53:26 +0000 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nkTru-00C190-0N for linux-arm-kernel@lists.infradead.org; Fri, 29 Apr 2022 16:53:23 +0000 Received: by mail-wr1-x42e.google.com with SMTP id i5so11517449wrc.13 for ; Fri, 29 Apr 2022 09:53:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Y88LxLAo1nli95Xm48q+VVmonwLpJPWWjtF+CYOqhhg=; b=kS0rLjIyQx4LL9BzaS8ekgzOXMz5x7UtOlmNj8ZPfhfk6Vac1b5tVtEPfTOw0NGIXU fCCCfb/tKTQUy3u1/0En3ZMcASkSEF8O3X/lcqEYhqBouaDdu3bE94L/w92RCp46nRpm 1mie0gAthvPqIUPCYOWv+NQ5vYgmGAu5cRTWxUvtq8bPlM8MIoxR/NDHE54stJgXBCS/ i6pCixktzJtRZOXajWExqFNgHpYrEQrkf5jnEItlbqoeLB590JZWBtlRmmHeMd/RpuCI QKlyIncNJsN+x82rDKsJY4juduOHt/PWHClkpFN5DXUczOKM34JHTqf82+9GDXFY5anL NJRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Y88LxLAo1nli95Xm48q+VVmonwLpJPWWjtF+CYOqhhg=; b=xh1YJWmzgJxBi3ROiZmhLv9h8FN9g0OVh9qYVHz0D87wSVQnXaQxa5EGkamir64jQp KTQS2yvGpY31PdrzwZWC064zI5g20GnV6A4uipwWlsWWPXhs0ow6RPIk/vHIAeKYCP1h 7sWdXYtDhQ2BM27IUFWoWFjQ5+WlswX4CKAMZQ5gc1qGwwPxGhnnMgOqTb5YYS4ycXSq +O3kUaPQaesQI3lAFd1Ie5+53qPEv/GUyGMLyZvxuJhH6g9ZMJ73FY7xprkadtgduwxT jmfT3iX99vsjBQoYlwBHg5zn8tRqyTIfWqvpacUKGsSm7ySGouAqsEKJh8ufwmbhVDH0 i4ow== X-Gm-Message-State: AOAM531vsq9dHxmVkX4yTQ+rsRDQZeDo1oBMsKSg2/561iOHaOll/Gp6 M0QKJxty9N/G/NyqU7rVtO6n1g== X-Google-Smtp-Source: ABdhPJzwer+SFr6WMGhlQdZX7bXuKXtmeQyttshlEfVpyCWfe1WLLeyjMlbv0DmRBMCU+MECobo61Q== X-Received: by 2002:a05:6000:1810:b0:20a:d512:96b9 with SMTP id m16-20020a056000181000b0020ad51296b9mr5762wrh.611.1651251198660; Fri, 29 Apr 2022 09:53:18 -0700 (PDT) Received: from maple.lan (cpc141216-aztw34-2-0-cust174.18-1.cable.virginm.net. [80.7.220.175]) by smtp.gmail.com with ESMTPSA id l5-20020adfa385000000b0020adb3ae75dsm2913406wrb.3.2022.04.29.09.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 09:53:17 -0700 (PDT) From: Daniel Thompson To: Marc Zyngier , Thomas Gleixner Cc: Daniel Thompson , Catalin Marinas , Will Deacon , Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] irqchip/exiu: Fix acknowledgment of edge triggered interrupts Date: Fri, 29 Apr 2022 17:53:14 +0100 Message-Id: <20220429165314.2343705-1-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220429_095322_093704_6818C91E X-CRM114-Status: GOOD ( 23.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently the EXIU uses the fasteoi interrupt flow that is configured by it's parent (irq-gic-v3.c). With this flow the only chance to clear the interrupt request happens during .irq_eoi() and (obviously) this happens after the interrupt handler has run. EXIU requires edge triggered interrupts to be acked prior to interrupt handling. Without this we risk incorrect interrupt dismissal when a new interrupt is delivered after the handler reads and acknowledges the peripheral but before the irq_eoi() takes place. Fix this by clearing the interrupt request from .irq_ack() if we are configured for edge triggered interrupts. This requires adopting the fasteoi-ack flow instead of the fasteoi to ensure the ack gets called. These changes have been tested using the power button on a Developerbox/SC2A11 combined with some hackery in gpio-keys so I can play with the different trigger mode (and an mdelay(500) so I can can check what happens on a double click in both modes. Fixes: 706cffc1b912 ("irqchip/exiu: Add support for Socionext Synquacer EXIU controller") Signed-off-by: Daniel Thompson --- Notes: Changes in v2: * Switch to dynamic selection of handle_fasteoi_irq and handle_fasteoi_ack_irq and reintroduce exiu_irq_eoi() since we need that for level triggered interrupts (Ard B). * Above changes mean we are no longer using sun6i NMI code as a template to tidy up the description accordingly. arch/arm64/Kconfig.platforms | 1 + drivers/irqchip/irq-sni-exiu.c | 33 +++++++++++++++++++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..aaeaf57c8222 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -253,6 +253,7 @@ config ARCH_INTEL_SOCFPGA config ARCH_SYNQUACER bool "Socionext SynQuacer SoC Family" + select IRQ_FASTEOI_HIERARCHY_HANDLERS config ARCH_TEGRA bool "NVIDIA Tegra SoC Family" diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index abd011fcecf4..651a82dead01 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -37,11 +37,20 @@ struct exiu_irq_data { u32 spi_base; }; -static void exiu_irq_eoi(struct irq_data *d) +static void exiu_irq_ack(struct irq_data *d) { struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); writel(BIT(d->hwirq), data->base + EIREQCLR); +} + +static void exiu_irq_eoi(struct irq_data *d) +{ + struct exiu_irq_data *data = irq_data_get_irq_chip_data(d); + u32 edge_triggered = readl_relaxed(data->base + EIEDG); + + if (!(edge_triggered & BIT(d->hwirq))) + writel(BIT(d->hwirq), data->base + EIREQCLR); irq_chip_eoi_parent(d); } @@ -91,10 +100,13 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) writel_relaxed(val, data->base + EILVL); val = readl_relaxed(data->base + EIEDG); - if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) + if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) { val &= ~BIT(d->hwirq); - else + irq_set_handler_locked(d, handle_fasteoi_irq); + } else { val |= BIT(d->hwirq); + irq_set_handler_locked(d, handle_fasteoi_ack_irq); + } writel_relaxed(val, data->base + EIEDG); writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR); @@ -104,6 +116,7 @@ static int exiu_irq_set_type(struct irq_data *d, unsigned int type) static struct irq_chip exiu_irq_chip = { .name = "EXIU", + .irq_ack = exiu_irq_ack, .irq_eoi = exiu_irq_eoi, .irq_enable = exiu_irq_enable, .irq_mask = exiu_irq_mask, @@ -148,6 +161,8 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct irq_fwspec parent_fwspec; struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; + int i, ret; + u32 edge_triggered; parent_fwspec = *fwspec; if (is_of_node(dom->parent->fwnode)) { @@ -165,7 +180,17 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); parent_fwspec.fwnode = dom->parent->fwnode; - return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + ret = irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); + if (ret) + return ret; + + edge_triggered = readl_relaxed(info->base + EIEDG); + for (i = 0; i < nr_irqs; i++) + irq_set_handler(virq + i, edge_triggered & BIT(i) ? + handle_fasteoi_ack_irq : + handle_fasteoi_irq); + + return 0; } static const struct irq_domain_ops exiu_domain_ops = { base-commit: b2d229d4ddb17db541098b83524d901257e93845 -- 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel