From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44704C433F5 for ; Fri, 29 Apr 2022 18:27:52 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E9AF88393F; Fri, 29 Apr 2022 20:27:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="AzYZXeL5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 6B7FD81A02; Fri, 29 Apr 2022 20:27:48 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E11FA8393F for ; Fri, 29 Apr 2022 20:27:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 8CC57B8377D; Fri, 29 Apr 2022 18:27:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28AD4C385AE; Fri, 29 Apr 2022 18:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651256864; bh=iYgdBXyG16IapMDsnR7t0ayNFx9RYsDlHtUNyAvQqNU=; h=From:To:Cc:Subject:Date:From; b=AzYZXeL5VPuW/iWhCNJPiOF6UQOL0U2KkQ3chNs9g/YW3LY3/lfagAaTfpklYBmrm O05/5ixkVAPugyFdn6GJ5FXnFobd5JlxSH26d10Db4Dlk2kerOPVTCm27as5x+vehl NCxg3/YwA1qgEFHQ18LLikuHOA/OxuNRlKmAOW+4xTDQYJGQGALrfzAlU/xeZ/aBdA T/v9anz7XdwYBpYk387+1ZCclrQjPJL8XGCTPeA1eVuNLETDx5LBPh3hVOmOa8yOLe Z6v8gyYUgDamp2rdUYYRZbe7zIPn8sSQzv4ACnHnz3gVgVmT4HuSWfIc5+Ox2my+CU jepfs+0lqN3Kw== Received: by pali.im (Postfix) id 8C2F3CAF; Fri, 29 Apr 2022 20:27:41 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: Peng Fan , Priyanka Jain , Jaehoon Chung , Sinan Akman Cc: u-boot@lists.denx.de Subject: [PATCH] mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error Date: Fri, 29 Apr 2022 20:27:34 +0200 Message-Id: <20220429182734.4281-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for fixed amount of time like it was before commit 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support"). This change fixes error 'Internal clock never stabilised.' which is printed on P2020 board at every access to SD card. Fixes: 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support") Signed-off-by: Pali Rohár --- drivers/mmc/fsl_esdhc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fdf2cc290e06..3b3587bd8d72 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -503,6 +503,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) u32 time_out; u32 value; uint clk; + u32 hostver; if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; @@ -543,6 +544,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ + hostver = esdhc_read32(&priv->esdhc_regs->hostver); + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { + udelay(10000); + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); + return; + } + time_out = 20; value = PRSSTAT_SDSTB; while (!(esdhc_read32(®s->prsstat) & value)) { @@ -562,6 +571,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) struct fsl_esdhc *regs = priv->esdhc_regs; u32 value; u32 time_out; + u32 hostver; value = esdhc_read32(®s->sysctl); @@ -572,6 +582,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) esdhc_write32(®s->sysctl, value); + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ + hostver = esdhc_read32(&priv->esdhc_regs->hostver); + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { + udelay(10000); + return; + } + time_out = 20; value = PRSSTAT_SDSTB; while (!(esdhc_read32(®s->prsstat) & value)) { -- 2.20.1