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From: Nate Drude <nate.d@variscite.com>
To: netdev@vger.kernel.org
Cc: michael.hennerich@analog.com, eran.m@variscite.com,
	Nate Drude <nate.d@variscite.com>
Subject: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property
Date: Fri, 29 Apr 2022 13:44:31 -0500	[thread overview]
Message-ID: <20220429184432.962738-1-nate.d@variscite.com> (raw)

Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG),
causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at
the GP_CLK pin.

Signed-off-by: Nate Drude <nate.d@variscite.com>
---
 Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml
index 1129f2b58e98..5fdbbd5aff82 100644
--- a/Documentation/devicetree/bindings/net/adi,adin.yaml
+++ b/Documentation/devicetree/bindings/net/adi,adin.yaml
@@ -36,6 +36,11 @@ properties:
     enum: [ 4, 8, 12, 16, 20, 24 ]
     default: 8
 
+  adi,clk_rcvr_125_en:
+    description: |
+      Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz
+      PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin.
+
 unevaluatedProperties: false
 
 examples:
-- 
2.25.1


             reply	other threads:[~2022-04-29 18:45 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-29 18:44 Nate Drude [this message]
2022-04-29 18:44 ` [PATCH 2/2] net: phy: adin: add adi,clk_rcvr_125_en property Nate Drude
2022-05-02 22:03   ` Jakub Kicinski
2022-04-29 22:37 ` [PATCH 1/2] dt-bindings: net: adin: document " Andrew Lunn
2022-05-02  9:03 ` Paolo Abeni
2022-05-03 11:50   ` Krzysztof Kozlowski
2022-05-05 12:40     ` Nate Drude

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