From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35303C433EF for ; Tue, 3 May 2022 08:52:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbiECIz4 (ORCPT ); Tue, 3 May 2022 04:55:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230464AbiECIzy (ORCPT ); Tue, 3 May 2022 04:55:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9A6C20BFD for ; Tue, 3 May 2022 01:52:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 765B4612DD for ; Tue, 3 May 2022 08:52:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B26F0C385A9; Tue, 3 May 2022 08:52:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651567941; bh=qM//c9ayuCqnoyQxEHD2ne7ItUofq48CK9Nuw0vQYM0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fMGVIYotC34U7aPBduKrrOqWRreRp1byN5Nx/aw2ZbqXSkMlegeV9A8gYzhA7kX/W aibz9B3n6eNnlbB+McWWTfDsvLGVI5j1aJL7IuDHKx/7Q3yYRRiepc2FLvqzJ2sS6q wMi5cv9YjLsWwt43c+7IwQfd8Cxqn5+vDT9utV18FmaHxqtrr825ntNicFb8xPYUJz 7s/wnLwHtoE33m4BSIjjVCZUfFeWUE6q8JftCrGNHZrEUsiV0IGQUrV++viu0BjJbi 2iJ2x+m8UlDLSge+C0Uh0v1JfMM2V0N9OE+57n2a0OMdPxx19Jmbohce/XI16wiUrK EKaEjJzDZubhw== From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Akinobu Mita , Alexandru Lazar , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , Cristian Pop , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?UTF-8?q?M=C3=A5rten=20Lindahl?= , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , =?UTF-8?q?Nuno=20S=C3=A1?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Jonathan Cameron , Cosmin Tanislav Subject: [PATCH 04/92] iio: accel: adxl367: Fix alignment for DMA safety Date: Tue, 3 May 2022 09:58:07 +0100 Message-Id: <20220503085935.1533814-5-jic23@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220503085935.1533814-1-jic23@kernel.org> References: <20220503085935.1533814-1-jic23@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Jonathan Cameron ____cacheline_aligned is insufficient guarantee for non-coherent DMA. Switch to the updated IIO_ALIGN definition. Update comment to reflect that DMA safety may require separate cachelines. Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver") Signed-off-by: Jonathan Cameron Cc: Cosmin Tanislav --- drivers/iio/accel/adxl367.c | 2 +- drivers/iio/accel/adxl367_spi.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c index 62960134ea19..9b933c5715c3 100644 --- a/drivers/iio/accel/adxl367.c +++ b/drivers/iio/accel/adxl367.c @@ -179,7 +179,7 @@ struct adxl367_state { unsigned int fifo_set_size; unsigned int fifo_watermark; - __be16 fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned; + __be16 fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_ALIGN); __be16 sample_buf; u8 act_threshold_buf[2]; u8 inact_time_buf[2]; diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c index 26dfc821ebbe..872b1c5a2cc5 100644 --- a/drivers/iio/accel/adxl367_spi.c +++ b/drivers/iio/accel/adxl367_spi.c @@ -9,6 +9,8 @@ #include #include +#include + #include "adxl367.h" #define ADXL367_SPI_WRITE_COMMAND 0x0A @@ -28,10 +30,10 @@ struct adxl367_spi_state { struct spi_transfer fifo_xfer[2]; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - u8 reg_write_tx_buf[1] ____cacheline_aligned; + u8 reg_write_tx_buf[1] __aligned(IIO_ALIGN); u8 reg_read_tx_buf[2]; u8 fifo_tx_buf[1]; }; -- 2.36.0