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From: Phil Edworthy <phil.edworthy@renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: Phil Edworthy <phil.edworthy@renesas.com>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org
Subject: [PATCH v3 05/12] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
Date: Tue,  3 May 2022 12:55:50 +0100	[thread overview]
Message-ID: <20220503115557.53370-6-phil.edworthy@renesas.com> (raw)
In-Reply-To: <20220503115557.53370-1-phil.edworthy@renesas.com>

We only ever use ARRAY_SIZE() to populate the number of parents, so
move this into the macro to always detect it automatically. This
also makes the tables of clocks a little simpler.
Similarly for the DEF_SD_MUX macro.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
---
v3:
 - New patch inserted
---
 drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++------
 drivers/clk/renesas/r9a07g044-cpg.c | 15 ++++++---------
 drivers/clk/renesas/rzg2l-cpg.h     | 16 +++++++++-------
 3 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 7ef2c43ea891..8241f5972de1 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -99,7 +99,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
 	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
 	DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
-		sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
+		sel_pll3_3, 0, CLK_MUX_READ_ONLY),
 	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
 		DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
@@ -123,13 +123,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
 	DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
 	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
 	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,
-		sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
+		sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
 	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
-	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0,
-		   sel_shdi, ARRAY_SIZE(sel_shdi)),
-	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1,
-		   sel_shdi, ARRAY_SIZE(sel_shdi)),
+	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),
+	DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi),
 	DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
 	DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
 };
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0a5c2265b842..43c4d6b8ccf4 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -139,18 +139,17 @@ static const struct {
 		DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
 		DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
 		DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,
-			sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY),
+			sel_pll3_3, 0, CLK_MUX_READ_ONLY),
 		DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
 			DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 
 		DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
 		DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
 		DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
-			sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
+			sel_gpu2, 0, CLK_MUX_READ_ONLY),
 		DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
 		DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
-		DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,
-			       sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),
+		DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
 		DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
 			DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK),
 
@@ -169,13 +168,11 @@ static const struct {
 		DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
 		DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
 		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
-			sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
+			sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
 		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
 		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
-		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0,
-			   sel_shdi, ARRAY_SIZE(sel_shdi)),
-		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1,
-			   sel_shdi, ARRAY_SIZE(sel_shdi)),
+		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
+		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
 		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
 		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
 		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 1be29cec0cb2..dfef1e2792fa 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -138,19 +138,21 @@ enum clk_types {
 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
 		 .parent = _parent, .dtable = _dtable, .flag = _flag)
-#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
-		_mux_flags) \
+#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
-		 .parent_names = _parent_names, .num_parents = _num_parents, \
+		 .parent_names = _parent_names, \
+		 .num_parents = ARRAY_SIZE(_parent_names), \
 		 .flag = _flag, .mux_flags = _mux_flags)
-#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
+#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
-		 .parent_names = _parent_names, .num_parents = _num_parents)
+		 .parent_names = _parent_names, \
+		 .num_parents = ARRAY_SIZE(_parent_names))
 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
-#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \
+#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
-		 .parent_names = _parent_names, .num_parents = _num_parents)
+		 .parent_names = _parent_names, \
+		 .num_parents = ARRAY_SIZE(_parent_names))
 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
 
-- 
2.32.0


  parent reply	other threads:[~2022-05-03 12:01 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 11:55 [PATCH v3 00/12] Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support Phil Edworthy
2022-05-03 11:55 ` [PATCH v3 01/12] dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers Phil Edworthy
2022-05-04  8:06   ` Geert Uytterhoeven
2022-05-04  8:13     ` Phil Edworthy
2022-05-03 11:55 ` [PATCH v3 02/12] dt-bindings: clock: Add r9a09g011 CPG Clock Definitions Phil Edworthy
2022-05-04  8:43   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 03/12] dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC Phil Edworthy
2022-05-04  8:43   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 04/12] dt-bindings: timer: arm,arch_timer: Add optional clock and reset Phil Edworthy
2022-05-03 13:11   ` Mark Rutland
2022-05-04 22:33     ` Rob Herring
2022-05-05  6:42       ` Geert Uytterhoeven
2022-05-03 13:12   ` Marc Zyngier
2022-05-03 14:22     ` Geert Uytterhoeven
2022-05-03 14:55       ` Mark Rutland
2022-05-03 15:56       ` Marc Zyngier
2022-05-04  9:05         ` Phil Edworthy
2022-05-03 11:55 ` Phil Edworthy [this message]
2022-05-04  8:44   ` [PATCH v3 05/12] clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 06/12] clk: renesas: rzg2l: Add read only versions of the clk macros Phil Edworthy
2022-05-04  8:44   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 07/12] clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers Phil Edworthy
2022-05-04  8:44   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 08/12] clk: renesas: rzg2l: Make use of CLK_MON registers optional Phil Edworthy
2022-05-04  8:44   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 09/12] clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg Phil Edworthy
2022-05-04  8:44   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 10/12] clk: renesas: Add RZ/V2M support using the rzg2l driver Phil Edworthy
2022-05-04  8:44   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 11/12] arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC Phil Edworthy
2022-05-04  8:47   ` Geert Uytterhoeven
2022-05-03 11:55 ` [PATCH v3 12/12] arm64: dts: renesas: Add initial device tree for RZ/V2M EVK Phil Edworthy
2022-05-04  8:51   ` Geert Uytterhoeven
2022-05-04  9:00     ` Phil Edworthy

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