From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96B1EC433FE for ; Tue, 3 May 2022 17:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240204AbiECRWf (ORCPT ); Tue, 3 May 2022 13:22:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232716AbiECRWc (ORCPT ); Tue, 3 May 2022 13:22:32 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D8F422BEF; Tue, 3 May 2022 10:18:55 -0700 (PDT) X-UUID: ce9a7978bb5e4c5490f9d6ec351fac8e-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:6ad70994-0b93-4c29-b97c-0c2157893154,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:ff1c912f-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: ce9a7978bb5e4c5490f9d6ec351fac8e-20220504 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 16904984; Wed, 04 May 2022 01:18:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 01:18:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 01:18:48 +0800 From: Miles Chen To: CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to support TTBR up to 35bit for MediaTek Date: Wed, 4 May 2022 01:18:48 +0800 Message-ID: <20220503171848.24992-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220429143411.7640-2-yf.wang@mediatek.com> References: <20220429143411.7640-2-yf.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi YF, > The calling to kmem_cache_alloc for level 2 page table allocation may > run in atomic context, and it fails sometimes when DMA32 zone runs out > of memory. > > Since Mediatek IOMMU hardware support at most 35bit PA in page table, s/Mediatek/MediaTek/ s/support/supports/ > so add a quirk to allow the PA of level 2 pgtable support bit35. 35bits PA, right? > > ...snip... > > phys = virt_to_phys(table); > - if (phys != (arm_v7s_iopte)phys) { > + if (phys != (arm_v7s_iopte)phys && > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) { I have one question while reading this. If IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, it means that the phys can be up to 35 bits. In aarch64, kmalloc() could return up to 52 bits PA (e.g., ARM64_PA_BITS_52=y) How do we guarantee that phys is safe (<= 35 bits) in this case? For example: When IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, the platform guarantees its PAs are at most 35 bits? Thanks, Miles > /* Doesn't fit in PTE */ > dev_err(dev, "Page table does not fit in PTE: %pa", &phys); > goto out_free; > @@ -457,9 +464,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, > arm_v7s_iopte curr, > struct io_pgtable_cfg *cfg) > { > + phys_addr_t phys = virt_to_phys(table); > arm_v7s_iopte old, new; > > - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; > + new = phys | ARM_V7S_PTE_TYPE_TABLE; > + > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + new = to_iopte_mtk(phys, new, cfg); > + > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) > new |= ARM_V7S_ATTR_NS_TABLE; > > @@ -778,6 +790,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > void *cookie) > { > + slab_flags_t slab_flag = ARM_V7S_TABLE_SLAB_FLAGS; > struct arm_v7s_io_pgtable *data; > > if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > @@ -788,7 +801,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > IO_PGTABLE_QUIRK_NO_PERMS | > - IO_PGTABLE_QUIRK_ARM_MTK_EXT)) > + IO_PGTABLE_QUIRK_ARM_MTK_EXT | > + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) > return NULL; > > /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ > @@ -801,10 +815,12 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > return NULL; > > spin_lock_init(&data->split_lock); > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + slab_flag = 0; > data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", > ARM_V7S_TABLE_SIZE(2, cfg), > ARM_V7S_TABLE_SIZE(2, cfg), > - ARM_V7S_TABLE_SLAB_FLAGS, NULL); > + slab_flag, NULL); > if (!data->l2_tables) > goto out_free_data; > > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 86af6f0a00a2..7ed15ad4710c 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -74,17 +74,22 @@ struct io_pgtable_cfg { > * to support up to 35 bits PA where the bit32, bit33 and bit34 are > * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs > + * extend the translation table support up to 35 bits PA, the > + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. > + * > * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table > * for use in the upper half of a split address space. > * > * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability > * attributes set in the TCR for a non-coherent page-table walker. > */ > - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) > + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > unsigned long quirks; > unsigned long pgsize_bitmap; > unsigned int ias; > -- > 2.18.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A7EFC433F5 for ; Tue, 3 May 2022 17:19:07 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 01C986102F; Tue, 3 May 2022 17:19:07 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hva8Od6k_dne; Tue, 3 May 2022 17:19:06 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [IPv6:2605:bc80:3010:104::8cd3:938]) by smtp3.osuosl.org (Postfix) with ESMTPS id A6B0860E03; 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Wed, 04 May 2022 01:18:50 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 01:18:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 01:18:48 +0800 To: Subject: Re: [PATCH 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to support TTBR up to 35bit for MediaTek Date: Wed, 4 May 2022 01:18:48 +0800 Message-ID: <20220503171848.24992-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220429143411.7640-2-yf.wang@mediatek.com> References: <20220429143411.7640-2-yf.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: isaacm@codeaurora.org, wsd_upstream@mediatek.com, will@kernel.org, linux-kernel@vger.kernel.org, Libo.Kang@mediatek.com, iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, ning.li@mediatek.com, matthias.bgg@gmail.com, stable@vger.kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Miles Chen via iommu Reply-To: Miles Chen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi YF, > The calling to kmem_cache_alloc for level 2 page table allocation may > run in atomic context, and it fails sometimes when DMA32 zone runs out > of memory. > > Since Mediatek IOMMU hardware support at most 35bit PA in page table, s/Mediatek/MediaTek/ s/support/supports/ > so add a quirk to allow the PA of level 2 pgtable support bit35. 35bits PA, right? > > ...snip... > > phys = virt_to_phys(table); > - if (phys != (arm_v7s_iopte)phys) { > + if (phys != (arm_v7s_iopte)phys && > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) { I have one question while reading this. If IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, it means that the phys can be up to 35 bits. In aarch64, kmalloc() could return up to 52 bits PA (e.g., ARM64_PA_BITS_52=y) How do we guarantee that phys is safe (<= 35 bits) in this case? For example: When IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, the platform guarantees its PAs are at most 35 bits? Thanks, Miles > /* Doesn't fit in PTE */ > dev_err(dev, "Page table does not fit in PTE: %pa", &phys); > goto out_free; > @@ -457,9 +464,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, > arm_v7s_iopte curr, > struct io_pgtable_cfg *cfg) > { > + phys_addr_t phys = virt_to_phys(table); > arm_v7s_iopte old, new; > > - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; > + new = phys | ARM_V7S_PTE_TYPE_TABLE; > + > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + new = to_iopte_mtk(phys, new, cfg); > + > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) > new |= ARM_V7S_ATTR_NS_TABLE; > > @@ -778,6 +790,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > void *cookie) > { > + slab_flags_t slab_flag = ARM_V7S_TABLE_SLAB_FLAGS; > struct arm_v7s_io_pgtable *data; > > if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > @@ -788,7 +801,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > IO_PGTABLE_QUIRK_NO_PERMS | > - IO_PGTABLE_QUIRK_ARM_MTK_EXT)) > + IO_PGTABLE_QUIRK_ARM_MTK_EXT | > + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) > return NULL; > > /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ > @@ -801,10 +815,12 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > return NULL; > > spin_lock_init(&data->split_lock); > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + slab_flag = 0; > data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", > ARM_V7S_TABLE_SIZE(2, cfg), > ARM_V7S_TABLE_SIZE(2, cfg), > - ARM_V7S_TABLE_SLAB_FLAGS, NULL); > + slab_flag, NULL); > if (!data->l2_tables) > goto out_free_data; > > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 86af6f0a00a2..7ed15ad4710c 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -74,17 +74,22 @@ struct io_pgtable_cfg { > * to support up to 35 bits PA where the bit32, bit33 and bit34 are > * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs > + * extend the translation table support up to 35 bits PA, the > + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. > + * > * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table > * for use in the upper half of a split address space. > * > * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability > * attributes set in the TCR for a non-coherent page-table walker. > */ > - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) > + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > unsigned long quirks; > unsigned long pgsize_bitmap; > unsigned int ias; > -- > 2.18.0 > > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58625C433EF for ; Tue, 3 May 2022 17:19:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 03 May 2022 10:18:51 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 May 2022 10:18:50 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 01:18:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 01:18:48 +0800 From: Miles Chen To: CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to support TTBR up to 35bit for MediaTek Date: Wed, 4 May 2022 01:18:48 +0800 Message-ID: <20220503171848.24992-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220429143411.7640-2-yf.wang@mediatek.com> References: <20220429143411.7640-2-yf.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_101901_398637_07E255C1 X-CRM114-Status: GOOD ( 23.80 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi YF, > The calling to kmem_cache_alloc for level 2 page table allocation may > run in atomic context, and it fails sometimes when DMA32 zone runs out > of memory. > > Since Mediatek IOMMU hardware support at most 35bit PA in page table, s/Mediatek/MediaTek/ s/support/supports/ > so add a quirk to allow the PA of level 2 pgtable support bit35. 35bits PA, right? > > ...snip... > > phys = virt_to_phys(table); > - if (phys != (arm_v7s_iopte)phys) { > + if (phys != (arm_v7s_iopte)phys && > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) { I have one question while reading this. If IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, it means that the phys can be up to 35 bits. In aarch64, kmalloc() could return up to 52 bits PA (e.g., ARM64_PA_BITS_52=y) How do we guarantee that phys is safe (<= 35 bits) in this case? For example: When IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, the platform guarantees its PAs are at most 35 bits? Thanks, Miles > /* Doesn't fit in PTE */ > dev_err(dev, "Page table does not fit in PTE: %pa", &phys); > goto out_free; > @@ -457,9 +464,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, > arm_v7s_iopte curr, > struct io_pgtable_cfg *cfg) > { > + phys_addr_t phys = virt_to_phys(table); > arm_v7s_iopte old, new; > > - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; > + new = phys | ARM_V7S_PTE_TYPE_TABLE; > + > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + new = to_iopte_mtk(phys, new, cfg); > + > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) > new |= ARM_V7S_ATTR_NS_TABLE; > > @@ -778,6 +790,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > void *cookie) > { > + slab_flags_t slab_flag = ARM_V7S_TABLE_SLAB_FLAGS; > struct arm_v7s_io_pgtable *data; > > if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > @@ -788,7 +801,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > IO_PGTABLE_QUIRK_NO_PERMS | > - IO_PGTABLE_QUIRK_ARM_MTK_EXT)) > + IO_PGTABLE_QUIRK_ARM_MTK_EXT | > + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) > return NULL; > > /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ > @@ -801,10 +815,12 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > return NULL; > > spin_lock_init(&data->split_lock); > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + slab_flag = 0; > data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", > ARM_V7S_TABLE_SIZE(2, cfg), > ARM_V7S_TABLE_SIZE(2, cfg), > - ARM_V7S_TABLE_SLAB_FLAGS, NULL); > + slab_flag, NULL); > if (!data->l2_tables) > goto out_free_data; > > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 86af6f0a00a2..7ed15ad4710c 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -74,17 +74,22 @@ struct io_pgtable_cfg { > * to support up to 35 bits PA where the bit32, bit33 and bit34 are > * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs > + * extend the translation table support up to 35 bits PA, the > + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. > + * > * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table > * for use in the upper half of a split address space. > * > * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability > * attributes set in the TCR for a non-coherent page-table walker. > */ > - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) > + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > unsigned long quirks; > unsigned long pgsize_bitmap; > unsigned int ias; > -- > 2.18.0 > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5700C433EF for ; Tue, 3 May 2022 17:20:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 03 May 2022 10:18:51 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 May 2022 10:18:50 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 4 May 2022 01:18:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 01:18:48 +0800 From: Miles Chen To: CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to support TTBR up to 35bit for MediaTek Date: Wed, 4 May 2022 01:18:48 +0800 Message-ID: <20220503171848.24992-1-miles.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220429143411.7640-2-yf.wang@mediatek.com> References: <20220429143411.7640-2-yf.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220503_101901_398637_07E255C1 X-CRM114-Status: GOOD ( 23.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi YF, > The calling to kmem_cache_alloc for level 2 page table allocation may > run in atomic context, and it fails sometimes when DMA32 zone runs out > of memory. > > Since Mediatek IOMMU hardware support at most 35bit PA in page table, s/Mediatek/MediaTek/ s/support/supports/ > so add a quirk to allow the PA of level 2 pgtable support bit35. 35bits PA, right? > > ...snip... > > phys = virt_to_phys(table); > - if (phys != (arm_v7s_iopte)phys) { > + if (phys != (arm_v7s_iopte)phys && > + !(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) { I have one question while reading this. If IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, it means that the phys can be up to 35 bits. In aarch64, kmalloc() could return up to 52 bits PA (e.g., ARM64_PA_BITS_52=y) How do we guarantee that phys is safe (<= 35 bits) in this case? For example: When IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT is set, the platform guarantees its PAs are at most 35 bits? Thanks, Miles > /* Doesn't fit in PTE */ > dev_err(dev, "Page table does not fit in PTE: %pa", &phys); > goto out_free; > @@ -457,9 +464,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table, > arm_v7s_iopte curr, > struct io_pgtable_cfg *cfg) > { > + phys_addr_t phys = virt_to_phys(table); > arm_v7s_iopte old, new; > > - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE; > + new = phys | ARM_V7S_PTE_TYPE_TABLE; > + > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + new = to_iopte_mtk(phys, new, cfg); > + > if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) > new |= ARM_V7S_ATTR_NS_TABLE; > > @@ -778,6 +790,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops, > static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > void *cookie) > { > + slab_flags_t slab_flag = ARM_V7S_TABLE_SLAB_FLAGS; > struct arm_v7s_io_pgtable *data; > > if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS)) > @@ -788,7 +801,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > > if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | > IO_PGTABLE_QUIRK_NO_PERMS | > - IO_PGTABLE_QUIRK_ARM_MTK_EXT)) > + IO_PGTABLE_QUIRK_ARM_MTK_EXT | > + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)) > return NULL; > > /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */ > @@ -801,10 +815,12 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg, > return NULL; > > spin_lock_init(&data->split_lock); > + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) > + slab_flag = 0; > data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2", > ARM_V7S_TABLE_SIZE(2, cfg), > ARM_V7S_TABLE_SIZE(2, cfg), > - ARM_V7S_TABLE_SLAB_FLAGS, NULL); > + slab_flag, NULL); > if (!data->l2_tables) > goto out_free_data; > > diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h > index 86af6f0a00a2..7ed15ad4710c 100644 > --- a/include/linux/io-pgtable.h > +++ b/include/linux/io-pgtable.h > @@ -74,17 +74,22 @@ struct io_pgtable_cfg { > * to support up to 35 bits PA where the bit32, bit33 and bit34 are > * encoded in the bit9, bit4 and bit5 of the PTE respectively. > * > + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs > + * extend the translation table support up to 35 bits PA, the > + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. > + * > * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table > * for use in the upper half of a split address space. > * > * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability > * attributes set in the TCR for a non-coherent page-table walker. > */ > - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) > + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) > + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) > + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) > + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) > + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) > unsigned long quirks; > unsigned long pgsize_bitmap; > unsigned int ias; > -- > 2.18.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel