From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0B7EC433EF for ; Tue, 3 May 2022 18:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3531810E854; Tue, 3 May 2022 18:23:00 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C83C010E854 for ; Tue, 3 May 2022 18:22:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651602178; x=1683138178; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Q5S3r7w2s7jebNjjfif9zZ9v4IH6naNsxuE7Rznxjok=; b=VmczHTPYiJDOO9P74fWpZIjx52T4f+cLJB9msXIS/IYDqqDjZWmjQ+XK k3Mi8Pg8YwTeC2Qly0wRYL3Q3cYA96TQlZJEYeWdhjwF11FbbsKSoe9AL H9wvTzUR0PNkgQ4iuSA1cs1WM5QWzD6Ui+BiVnSWVRQsZNUjRqbtpwsLc D4GBw6pfVLWt6CqI/WInpn2EUvfuubi2Bn2QAsNWTqThko/7M5wQMC4n4 +pMH6LGX7aDIQdh7sf3vMqnhwsYRcr4/MPpGx61jHaUh5DFZKJuuqrju6 ddAdfiZlq7LvkyxfJhPbr7b7yo+R5KDK5KwiRXMIfwLRXW0kkDdX8kPCl A==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="249532704" X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="249532704" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 11:22:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,195,1647327600"; d="scan'208";a="620450842" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.51]) by fmsmga008.fm.intel.com with SMTP; 03 May 2022 11:22:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 03 May 2022 21:22:55 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 3 May 2022 21:22:20 +0300 Message-Id: <20220503182242.18797-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220503182242.18797-1-ville.syrjala@linux.intel.com> References: <20220503182242.18797-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Only reassign the pipe's DPLL if it's going through a full .compute_config() cycle. If OTOH it's just getting modeset eg. in order to change cdclk there doesn't seem much point in picking a new DPLL for it. This should also prevent .get_dplls() from seeing a funky port_clock for DP even in cases where the readout produces a non-standard clock and we (for some reason) have decided to not fully recompute the state to remedy the situation. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 17 +---------------- drivers/gpu/drm/i915/display/intel_dpll.c | 6 ++---- 2 files changed, 3 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5e50e0d56088..7d488d320762 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6955,20 +6955,6 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) } } -static void intel_modeset_clear_plls(struct intel_atomic_state *state) -{ - struct intel_crtc_state *new_crtc_state; - struct intel_crtc *crtc; - int i; - - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { - if (!intel_crtc_needs_modeset(new_crtc_state)) - continue; - - intel_release_shared_dplls(state, crtc); - } -} - /* * This implements the workaround described in the "notes" section of the mode * set sequence documentation. When going from no pipes or single pipe to @@ -7802,6 +7788,7 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; + intel_release_shared_dplls(state, crtc); continue; } @@ -7849,8 +7836,6 @@ static int intel_atomic_check(struct drm_device *dev, ret = intel_modeset_calc_cdclk(state); if (ret) return ret; - - intel_modeset_clear_plls(state); } ret = intel_atomic_check_crtcs(state); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 2b3f72550e5a..afd30c6cc34c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, int ret; drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); + drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); - if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll)) - return 0; - - if (!crtc_state->hw.enable) + if (!crtc_state->hw.enable || crtc_state->shared_dpll) return 0; if (!i915->dpll_funcs->crtc_get_shared_dpll) -- 2.35.1