From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D32C433EF for ; Wed, 4 May 2022 18:49:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377385AbiEDSxJ (ORCPT ); Wed, 4 May 2022 14:53:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377378AbiEDSw5 (ORCPT ); Wed, 4 May 2022 14:52:57 -0400 Received: from smtp-fw-2101.amazon.com (smtp-fw-2101.amazon.com [72.21.196.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A748E1A80E; Wed, 4 May 2022 11:49:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1651690152; x=1683226152; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=h/C/5yjGgoLTn6Dm77IcH1vaUCc1paTnbF0Lky4zSkc=; b=WAX7qFInmCXhZg3fiEhBS2hiuvHmlXTMZg6Ma9kDa8nXW9Ib9j3QweDl oIrIxELTCL60AcOvlbqFzYXmKESdkgM/uDL3cIeQ5IfhuvwqaYl/tTgUC 4CUeYGhe4StyPTdrUp/Z8suZdkBMFcHISdXD7cF3+lrtSQrqABSsOOwdh A=; X-IronPort-AV: E=Sophos;i="5.91,198,1647302400"; d="scan'208";a="195376184" Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-pdx-2a-7d84505d.us-west-2.amazon.com) ([10.43.8.2]) by smtp-border-fw-2101.iad2.amazon.com with ESMTP; 04 May 2022 18:49:05 +0000 Received: from EX13MTAUWC002.ant.amazon.com (pdx1-ws-svc-p6-lb9-vlan2.pdx.amazon.com [10.236.137.194]) by email-inbound-relay-pdx-2a-7d84505d.us-west-2.amazon.com (Postfix) with ESMTPS id 8094B8388B; Wed, 4 May 2022 18:48:59 +0000 (UTC) Received: from EX13D02UWC001.ant.amazon.com (10.43.162.243) by EX13MTAUWC002.ant.amazon.com (10.43.162.240) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 4 May 2022 18:48:58 +0000 Received: from EX13MTAUWC001.ant.amazon.com (10.43.162.135) by EX13D02UWC001.ant.amazon.com (10.43.162.243) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 4 May 2022 18:48:58 +0000 Received: from dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (172.19.181.128) by mail-relay.amazon.com (10.43.162.232) with Microsoft SMTP Server id 15.0.1497.32 via Frontend Transport; Wed, 4 May 2022 18:48:58 +0000 Received: by dev-dsk-alisaidi-1d-b9a0e636.us-east-1.amazon.com (Postfix, from userid 5131138) id 7441220F9; Wed, 4 May 2022 18:48:57 +0000 (UTC) From: Ali Saidi To: , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v8 0/4] perf: arm-spe: Decode SPE source and use for perf c2c Date: Wed, 4 May 2022 18:48:45 +0000 Message-ID: <20220504184850.24986-1-alisaidi@amazon.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When synthesizing data from SPE, augment the type with source information for Arm Neoverse cores so we can detect situtions like cache line contention and transfers on Arm platforms. This changes enables future changes to c2c on a system with SPE where lines that are shared among multiple cores show up in perf c2c output. Changes in v8: * Report NA for both mem_lvl and mem_lvl_num for stores where we have no information Changes in v7: * Minor change requested by Leo Yan Changes in v6: * Drop changes to c2c command which will come from Leo Yan Changes in v5: * Add a new snooping type to disambiguate cache-to-cache transfers where we don't know if the data is clean or dirty. * Set snoop flags on all the data-source cases * Special case stores as we have no information on them Changes in v4: * Bring-in the kernel's arch/arm64/include/asm/cputype.h into tools/ * Add neoverse-v1 to the neoverse cores list Ali Saidi (4): tools: arm64: Import cputype.h perf arm-spe: Use SPE data source for neoverse cores perf mem: Support mem_lvl_num in c2c command perf mem: Support HITM for when mem_lvl_num is any tools/arch/arm64/include/asm/cputype.h | 258 ++++++++++++++++++ .../util/arm-spe-decoder/arm-spe-decoder.c | 1 + .../util/arm-spe-decoder/arm-spe-decoder.h | 12 + tools/perf/util/arm-spe.c | 110 +++++++- tools/perf/util/mem-events.c | 20 +- 5 files changed, 383 insertions(+), 18 deletions(-) create mode 100644 tools/arch/arm64/include/asm/cputype.h -- 2.32.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC356C433F5 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When synthesizing data from SPE, augment the type with source information for Arm Neoverse cores so we can detect situtions like cache line contention and transfers on Arm platforms. This changes enables future changes to c2c on a system with SPE where lines that are shared among multiple cores show up in perf c2c output. Changes in v8: * Report NA for both mem_lvl and mem_lvl_num for stores where we have no information Changes in v7: * Minor change requested by Leo Yan Changes in v6: * Drop changes to c2c command which will come from Leo Yan Changes in v5: * Add a new snooping type to disambiguate cache-to-cache transfers where we don't know if the data is clean or dirty. * Set snoop flags on all the data-source cases * Special case stores as we have no information on them Changes in v4: * Bring-in the kernel's arch/arm64/include/asm/cputype.h into tools/ * Add neoverse-v1 to the neoverse cores list Ali Saidi (4): tools: arm64: Import cputype.h perf arm-spe: Use SPE data source for neoverse cores perf mem: Support mem_lvl_num in c2c command perf mem: Support HITM for when mem_lvl_num is any tools/arch/arm64/include/asm/cputype.h | 258 ++++++++++++++++++ .../util/arm-spe-decoder/arm-spe-decoder.c | 1 + .../util/arm-spe-decoder/arm-spe-decoder.h | 12 + tools/perf/util/arm-spe.c | 110 +++++++- tools/perf/util/mem-events.c | 20 +- 5 files changed, 383 insertions(+), 18 deletions(-) create mode 100644 tools/arch/arm64/include/asm/cputype.h -- 2.32.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel