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* [Intel-gfx] [PATCH 0/1] DG2 DMC Support
@ 2022-05-05 17:38 Anusha Srivatsa
  2022-05-05 17:38 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
  2022-05-05 19:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: Load DMC on DG2 (rev3) Patchwork
  0 siblings, 2 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-05 17:38 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

While DG2 supports DC5 and DC9, some of the tests in
fast-feedback blew up DG2 when the tests forced transition
from dc5->dc9 on suspend and dc9->dc5 on resume. Some local
experiments performed with Rodrigo on a RIL system  showed promising
results when dc5 was completely diabled and i915 took only dc9 paths.

Sending this so we can check the CI results to confirm the
findings from local testing which will hopefully help narrow
down the root cause of MMIO BAR lost issue

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>

Anusha Srivatsa (1):
  drm/i915/dmc: Load DMC on DG2

 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-05 17:38 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
@ 2022-05-05 17:38 ` Anusha Srivatsa
  2022-05-05 19:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: Load DMC on DG2 (rev3) Patchwork
  1 sibling, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-05 17:38 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 11 +++++++++--
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..2271f88e9a25 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -906,8 +906,15 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
-
-	if (IS_DG1(dev_priv))
+	/* FIXME: change max_dc back to 3 once
+	 * we have DC5 bugs resolved. Till then,
+	 * DG2 will use only DC9. Though DC9 does
+	 * not depend on DMC, loading it in order
+	 * to unblock runtime PM
+	 */
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: Load DMC on DG2 (rev3)
  2022-05-05 17:38 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
  2022-05-05 17:38 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
@ 2022-05-05 19:18 ` Patchwork
  1 sibling, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-05-05 19:18 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 10979 bytes --]

== Series Details ==

Series: drm/i915/dmc: Load DMC on DG2 (rev3)
URL   : https://patchwork.freedesktop.org/series/103625/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11611 -> Patchwork_103625v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_103625v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103625v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/index.html

Participating hosts (39 -> 39)
------------------------------

  Additional (3): bat-rpls-2 fi-rkl-11600 fi-icl-u2 
  Missing    (3): fi-bsw-cyan fi-hsw-4770 bat-jsl-2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_103625v3:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@reset:
    - fi-bdw-5557u:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/fi-bdw-5557u/igt@i915_selftest@live@reset.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-bdw-5557u/igt@i915_selftest@live@reset.html

  
Known issues
------------

  Here are the changes found in Patchwork_103625v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
    - fi-icl-u2:          NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][8] ([i915#3012])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][9] -> [INCOMPLETE][10] ([i915#3921])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-pnv-d510:        NOTRUN -> [SKIP][11] ([fdo#109271])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-pnv-d510/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-rkl-11600:       NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][14] ([i915#4070] / [i915#4103]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          NOTRUN -> [SKIP][15] ([fdo#109278]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
    - bat-adlp-4:         [PASS][16] -> [DMESG-WARN][17] ([i915#3576]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][18] ([fdo#109285] / [i915#4098])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
    - fi-icl-u2:          NOTRUN -> [SKIP][19] ([fdo#109285])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-rkl-11600:       NOTRUN -> [SKIP][20] ([i915#4070] / [i915#533])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-rkl-11600:       NOTRUN -> [SKIP][21] ([i915#1072]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-icl-u2:          NOTRUN -> [SKIP][22] ([i915#3555])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][23] ([i915#3555] / [i915#4098])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][24] ([i915#3301] / [i915#3708])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
    - fi-icl-u2:          NOTRUN -> [SKIP][25] ([i915#3301])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@prime_vgem@basic-write:
    - fi-rkl-11600:       NOTRUN -> [SKIP][26] ([i915#3291] / [i915#3708]) +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-rkl-11600/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-soraka:      [DMESG-WARN][27] ([i915#1982]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - {fi-ehl-2}:         [DMESG-WARN][29] ([i915#5122]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [DMESG-FAIL][31] ([i915#4528]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - {bat-adlp-6}:       [DMESG-WARN][33] ([i915#3576]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11611/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828


Build changes
-------------

  * Linux: CI_DRM_11611 -> Patchwork_103625v3

  CI-20190529: 20190529
  CI_DRM_11611: 230f973b9a1501831552e7b401eea59405143273 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6466: 4e3a37b27cad645b15485403284eee5d03a9ada7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_103625v3: 230f973b9a1501831552e7b401eea59405143273 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

584b06482f2e drm/i915/dmc: Load DMC on DG2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103625v3/index.html

[-- Attachment #2: Type: text/html, Size: 12526 bytes --]

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-06 17:13 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
@ 2022-05-06 17:13 ` Anusha Srivatsa
  0 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-06 17:13 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)
v4: Add FIXME (Rodrigo)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 11 +++++++++--
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..2271f88e9a25 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -906,8 +906,15 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
-
-	if (IS_DG1(dev_priv))
+	/* FIXME: change max_dc back to 3 once
+	 * we have DC5 bugs resolved. Till then,
+	 * DG2 will use only DC9. Though DC9 does
+	 * not depend on DMC, loading it in order
+	 * to unblock runtime PM
+	 */
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-05 16:58 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
@ 2022-05-05 17:04   ` Vivi, Rodrigo
  0 siblings, 0 replies; 11+ messages in thread
From: Vivi, Rodrigo @ 2022-05-05 17:04 UTC (permalink / raw)
  To: Srivatsa, Anusha, intel-gfx

On Thu, 2022-05-05 at 09:58 -0700, Anusha Srivatsa wrote:
> Add Support for DC states on Dg2.
> 
> v2: Add dc9 as the max supported DC states and disable DC5.
> v3: set max_dc to 0. (Imre)
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
>  drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1d9bd5808849..15b15f434fcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
>         if (!HAS_DISPLAY(dev_priv))
>                 return 0;
>  
> -       if (IS_DG1(dev_priv))
> +       if (IS_DG2(dev_priv))
> +               max_dc = 0;

Please add a /* FIXME: */
explaining the DC5 bugs that are under investigation or something like
that... and that DC9 doesn't depend on DMC, but we are loading it
in order to unblock the runtime_pm.

> +       else if (IS_DG1(dev_priv))
>                 max_dc = 3;
>         else if (DISPLAY_VER(dev_priv) >= 12)
>                 max_dc = 4;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 257cf662f9f4..2f01aca4d981 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -52,6 +52,10 @@
>  
>  #define DISPLAY_VER12_DMC_MAX_FW_SIZE  ICL_DMC_MAX_FW_SIZE
>  
> +#define DG2_DMC_PATH                   DMC_PATH(dg2, 2, 06)
> +#define DG2_DMC_VERSION_REQUIRED       DMC_VERSION(2, 06)
> +MODULE_FIRMWARE(DG2_DMC_PATH);
> +
>  #define ADLP_DMC_PATH                  DMC_PATH(adlp, 2, 16)
>  #define ADLP_DMC_VERSION_REQUIRED      DMC_VERSION(2, 16)
>  MODULE_FIRMWARE(ADLP_DMC_PATH);
> @@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct
> drm_i915_private *dev_priv)
>          */
>         intel_dmc_runtime_pm_get(dev_priv);
>  
> -       if (IS_ALDERLAKE_P(dev_priv)) {
> +       if (IS_DG2(dev_priv)) {
> +               dmc->fw_path = DG2_DMC_PATH;
> +               dmc->required_version = DG2_DMC_VERSION_REQUIRED;
> +               dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
> +       } else if (IS_ALDERLAKE_P(dev_priv)) {
>                 dmc->fw_path = ADLP_DMC_PATH;
>                 dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
>                 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;


^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-05 16:58 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
@ 2022-05-05 16:58 ` Anusha Srivatsa
  2022-05-05 17:04   ` Vivi, Rodrigo
  0 siblings, 1 reply; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-05 16:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..15b15f434fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG1(dev_priv))
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-05 16:57 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
@ 2022-05-05 16:57 ` Anusha Srivatsa
  0 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-05 16:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..15b15f434fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG1(dev_priv))
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-05-04 20:22 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
@ 2022-05-04 20:22 ` Anusha Srivatsa
  0 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-05-04 20:22 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Add Support for DC states on Dg2.

v2: Add dc9 as the max supported DC states and disable DC5.
v3: set max_dc to 0. (Imre)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>(v1)
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1d9bd5808849..15b15f434fcf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -907,7 +907,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG1(dev_priv))
+	if (IS_DG2(dev_priv))
+		max_dc = 0;
+	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-04-13  0:57 Anusha Srivatsa
  2022-04-13 20:56 ` Rodrigo Vivi
@ 2022-04-15  4:32 ` Lucas De Marchi
  1 sibling, 0 replies; 11+ messages in thread
From: Lucas De Marchi @ 2022-04-15  4:32 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

On Tue, Apr 12, 2022 at 05:57:07PM -0700, Anusha Srivatsa wrote:
>Add Support for DC states on Dg2.
>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Failure in CI seems unrelated. Although it's unfortunate the DG2
couldn't get tested with this patch.

were you able to test this locally and get a pass on tests not currently
passing in BAT?

thanks
Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_display_power.c |  2 +-
> drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 6a5695008f7c..5a0cab82a156 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -4770,7 +4770,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
> 	if (!HAS_DISPLAY(dev_priv))
> 		return 0;
>
>-	if (IS_DG1(dev_priv))
>+	if (IS_DG1(dev_priv) || IS_DG2(dev_priv))
> 		max_dc = 3;
> 	else if (DISPLAY_VER(dev_priv) >= 12)
> 		max_dc = 4;
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 257cf662f9f4..2f01aca4d981 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -52,6 +52,10 @@
>
> #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
>
>+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
>+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
>+MODULE_FIRMWARE(DG2_DMC_PATH);
>+
> #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
> #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
> MODULE_FIRMWARE(ADLP_DMC_PATH);
>@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
> 	 */
> 	intel_dmc_runtime_pm_get(dev_priv);
>
>-	if (IS_ALDERLAKE_P(dev_priv)) {
>+	if (IS_DG2(dev_priv)) {
>+		dmc->fw_path = DG2_DMC_PATH;
>+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
>+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
>+	} else if (IS_ALDERLAKE_P(dev_priv)) {
> 		dmc->fw_path = ADLP_DMC_PATH;
> 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
> 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
>-- 
>2.25.1
>

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
  2022-04-13  0:57 Anusha Srivatsa
@ 2022-04-13 20:56 ` Rodrigo Vivi
  2022-04-15  4:32 ` Lucas De Marchi
  1 sibling, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2022-04-13 20:56 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

On Tue, Apr 12, 2022 at 05:57:07PM -0700, Anusha Srivatsa wrote:
> Add Support for DC states on Dg2.
> 
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 6a5695008f7c..5a0cab82a156 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4770,7 +4770,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>  	if (!HAS_DISPLAY(dev_priv))
>  		return 0;
>  
> -	if (IS_DG1(dev_priv))
> +	if (IS_DG1(dev_priv) || IS_DG2(dev_priv))
>  		max_dc = 3;

Oh, this max_dc and the enable_dc param is so ugly...
it should deserve at least a enum, but with the dc9 being totally independent
on the decision I couldn't see a clean and quick way... so let's continue
with this for now


>  	else if (DISPLAY_VER(dev_priv) >= 12)
>  		max_dc = 4;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 257cf662f9f4..2f01aca4d981 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -52,6 +52,10 @@
>  
>  #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
>  
> +#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
> +#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
> +MODULE_FIRMWARE(DG2_DMC_PATH);
> +
>  #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
>  #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
>  MODULE_FIRMWARE(ADLP_DMC_PATH);
> @@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dmc_runtime_pm_get(dev_priv);
>  
> -	if (IS_ALDERLAKE_P(dev_priv)) {
> +	if (IS_DG2(dev_priv)) {
> +		dmc->fw_path = DG2_DMC_PATH;
> +		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
> +		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
> +	} else if (IS_ALDERLAKE_P(dev_priv)) {
>  		dmc->fw_path = ADLP_DMC_PATH;
>  		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
>  		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;

probably worth to rename the dev_priv to i915 on these functions you are touching in here...

anyway:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2
@ 2022-04-13  0:57 Anusha Srivatsa
  2022-04-13 20:56 ` Rodrigo Vivi
  2022-04-15  4:32 ` Lucas De Marchi
  0 siblings, 2 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2022-04-13  0:57 UTC (permalink / raw)
  To: intel-gfx

Add Support for DC states on Dg2.

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dmc.c           | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 6a5695008f7c..5a0cab82a156 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4770,7 +4770,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	if (!HAS_DISPLAY(dev_priv))
 		return 0;
 
-	if (IS_DG1(dev_priv))
+	if (IS_DG1(dev_priv) || IS_DG2(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
 		max_dc = 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 257cf662f9f4..2f01aca4d981 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -52,6 +52,10 @@
 
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define DG2_DMC_PATH			DMC_PATH(dg2, 2, 06)
+#define DG2_DMC_VERSION_REQUIRED	DMC_VERSION(2, 06)
+MODULE_FIRMWARE(DG2_DMC_PATH);
+
 #define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 16)
 #define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 16)
 MODULE_FIRMWARE(ADLP_DMC_PATH);
@@ -688,7 +692,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_P(dev_priv)) {
+	if (IS_DG2(dev_priv)) {
+		dmc->fw_path = DG2_DMC_PATH;
+		dmc->required_version = DG2_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_P(dev_priv)) {
 		dmc->fw_path = ADLP_DMC_PATH;
 		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-05-06 17:17 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-05 17:38 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
2022-05-05 17:38 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
2022-05-05 19:18 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dmc: Load DMC on DG2 (rev3) Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2022-05-06 17:13 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
2022-05-06 17:13 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
2022-05-05 16:58 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
2022-05-05 16:58 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
2022-05-05 17:04   ` Vivi, Rodrigo
2022-05-05 16:57 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
2022-05-05 16:57 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
2022-05-04 20:22 [Intel-gfx] [PATCH 0/1] DG2 DMC Support Anusha Srivatsa
2022-05-04 20:22 ` [Intel-gfx] [PATCH] drm/i915/dmc: Load DMC on DG2 Anusha Srivatsa
2022-04-13  0:57 Anusha Srivatsa
2022-04-13 20:56 ` Rodrigo Vivi
2022-04-15  4:32 ` Lucas De Marchi

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