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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/4] target/arm: Implement S2FWB Date: Thu, 5 May 2022 19:39:46 +0100 Message-Id: <20220505183950.2781801-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In the original Arm v8 two-stage translation, both stage 1 and stage 2 specify memory attributes (memory type, cacheability, shareability); these are then combined to produce the overall memory attributes for the whole stage 1+2 access. The new FEAT_S2FWB feature allows the guest to enable a different interpretation of the attribute bits in the stage 2 descriptors. These bits can now be used to control details of how the stage 1 and 2 attributes should be combined (for instance they can say "always use the stage 1 attributes" or "ignore the stage 1 attributes and always be Device memory"). This series implements support for FEAT_S2FWB. It starts by postponing interpretation of the attribute bits in a stage 2 descriptor until the point where we need to combine them with the stage 1 attributes. It then pulls out the HCR_EL2.FWB=0 specific code into its own function, so that the support for FWB=1 that we add in patch 3 slots in neatly. Finally, patch 4 turns it on for -cpu max. I have tested that a Linux nested-guest setup works OK (and that the guest really is turning on HCR_EL2.FWB), but since we don't do anything with memory attributes except return them in the PAR_EL1 when the guest does AT instructions, you probably wouldn't find bugs in this unless you explicitly went and wrote a bunch of test cases that set up page tables and ran AT instructions to check what memory attributes we report. -- PMM Peter Maydell (4): target/arm: Postpone interpretation of stage 2 descriptor attribute bits target/arm: Factor out FWB=0 specific part of combine_cacheattrs() target/arm: Implement FEAT_S2FWB target/arm: Enable FEAT_S2FWB for -cpu max docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 + target/arm/internals.h | 7 +- target/arm/cpu64.c | 10 ++ target/arm/helper.c | 200 +++++++++++++++++++++++++++------- 5 files changed, 182 insertions(+), 41 deletions(-) -- 2.25.1