* [PATCH v4 0/3] Add support for different mediatek pinctrl designs
@ 2022-04-21 6:23 Sam Shih
2022-04-21 6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Sam Shih @ 2022-04-21 6:23 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun,
GSS_MTK_Uboot_upstream, u-boot
Cc: Sam Shih
MediaTek SoC's pinconf register usage varies by SoC,
So the original code uses V0/V1 to mark different pinconf design.
But actually, the real difference is the design of the "pin" itself.
Different SoCs will choose specify "pin design", which we call the
"io_type" of the pin.
For a better understanding of mediatek pinctrl design. and make the
driver clear and flexible, this patch series changes common parts
of mediatek pinctrl driver to support various pinctrl controller
designs.
The following mediatek config were tested to ensure the build passed:
- mt7622_rfb_defconfig
- mt7623a_unielec_u7623_02_defconfig
- mt7623n_bpir2_defconfig
- mt7629_rfb_defconfig
- mt8183_pumpkin_defconfig
- mt8512_bm1_emmc_defconfig
- mt8516_pumpkin_defconfig
- mt8518_ap1_emmc_defconfig
---
v4: fix mt8518_ap1_emmc build fail
v3: fix v2 patch series misapplied
v2: fix build fail caused by patch [2/3]
Sam Shih (3):
pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
pinctrl: mediatek: introduce multiple memory bases support
pinctrl: mediatek: add support for different types of IO pins
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 221 ++++++++++++++----
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 78 ++++++-
2 files changed, 248 insertions(+), 51 deletions(-)
--
2.18.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
2022-04-21 6:23 [PATCH v4 0/3] Add support for different mediatek pinctrl designs Sam Shih
@ 2022-04-21 6:23 ` Sam Shih
2022-05-05 18:52 ` Tom Rini
2022-04-21 6:23 ` [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
2022-04-21 6:23 ` [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih
2 siblings, 1 reply; 7+ messages in thread
From: Sam Shih @ 2022-04-21 6:23 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun,
GSS_MTK_Uboot_upstream, u-boot
Cc: Sam Shih
There are many pins in a SoCs, and different pin may belong
to different "io_type", For example: some pins of MT7622 belongs
to "io_type A", the other belongs to "io_type B", and pinctrl "V0"
means handle pinconf via "io_type A" or "io_type B", so SoCs that
contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver.
This patch separates the implementation of register operations
(e.g: "bias-pull-up/down", "driving" and "input-enable") into
different functions, and lets the original V0/V1
ops to call the new functions.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 126 +++++++++++++-----
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 18 +++
2 files changed, 114 insertions(+), 30 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index a9cedda164..4ae328699e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -308,13 +308,31 @@ static const struct pinconf_param mtk_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
};
+int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val)
+{
+ return mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val);
+}
-int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val)
+int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val)
{
- int err, disable, pullup;
+ int err;
- disable = (arg == PIN_CONFIG_BIAS_DISABLE);
- pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+ /* try pupd_r1_r0 if pullen_pullsel return error */
+ err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
+ val);
+ if (err)
+ return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
+ pullup, val);
+
+ return err;
+}
+
+int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val)
+{
+ int err;
if (disable) {
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
@@ -323,7 +341,6 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val)
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
if (err)
return err;
-
} else {
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
if (err)
@@ -336,14 +353,10 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val)
return 0;
}
-int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val)
+int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
+ bool disable, bool pullup, u32 val)
{
- int err, disable, pullup, r0, r1;
-
- disable = (arg == PIN_CONFIG_BIAS_DISABLE);
- pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
- r0 = !!(val & 1);
- r1 = !!(val & 2);
+ int err;
if (disable) {
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
@@ -359,16 +372,53 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val)
return err;
}
- /* Also set PUPD/R0/R1 if the pin has them */
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
- if (err != -EINVAL) {
- mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
- mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
+ return 0;
+}
+
+int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val)
+{
+ int err, r0, r1;
+
+ r0 = !!(val & 1);
+ r1 = !!(val & 2);
+
+ if (disable) {
+ pullup = 0;
+ r0 = 0;
+ r1 = 0;
}
+ /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
+ if (err)
+ return err;
+
+ /* Also set PUPD/R0/R1 if the pin has them */
+ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
+ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
+
return 0;
}
+int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val)
+{
+ int err;
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ int rev = priv->soc->rev;
+ bool disable, pullup;
+
+ disable = (arg == PIN_CONFIG_BIAS_DISABLE);
+ pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val);
+ else
+ err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val);
+
+ return err;
+}
+
int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
{
int err;
@@ -379,6 +429,18 @@ int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
if (err)
return err;
+
+ return 0;
+}
+
+int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg)
+{
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ int rev = priv->soc->rev;
+
+ if (rev == MTK_PINCTRL_V1)
+ return mtk_pinconf_input_enable_v1(dev, pin, arg);
+
return 0;
}
@@ -410,7 +472,6 @@ int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
return 0;
}
-
int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
@@ -429,21 +490,30 @@ int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
return 0;
}
+int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err;
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ int rev = priv->soc->rev;
+
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_drive_set_v0(dev, pin, arg);
+ else
+ err = mtk_pinconf_drive_set_v1(dev, pin, arg);
+
+ return err;
+}
+
static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
unsigned int param, unsigned int arg)
{
int err = 0;
- struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
- int rev = priv->soc->rev;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
- if (rev == MTK_PINCTRL_V0)
- err = mtk_pinconf_bias_set_v0(dev, pin, param, arg);
- else
- err = mtk_pinconf_bias_set_v1(dev, pin, param, arg);
+ err = mtk_pinconf_bias_set(dev, pin, param, arg);
if (err)
goto err;
break;
@@ -456,8 +526,7 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
- if (rev == MTK_PINCTRL_V1)
- err = mtk_pinconf_input_enable_v1(dev, pin, param);
+ err = mtk_pinconf_input_enable(dev, pin, param);
if (err)
goto err;
break;
@@ -486,10 +555,7 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- if (rev == MTK_PINCTRL_V0)
- err = mtk_pinconf_drive_set_v0(dev, pin, arg);
- else
- err = mtk_pinconf_drive_set_v1(dev, pin, arg);
+ err = mtk_pinconf_drive_set(dev, pin, arg);
if (err)
goto err;
break;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 5e51a9a90c..735fb6fef8 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -192,4 +192,22 @@ void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
int mtk_pinctrl_common_probe(struct udevice *dev,
struct mtk_pinctrl_soc *soc);
+#if CONFIG_IS_ENABLED(PINCONF)
+
+int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
+int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
+ bool disable, bool pullup, u32 val);
+int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
+int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
+int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
+int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg);
+int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg);
+int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg);
+
+#endif
+
#endif /* __PINCTRL_MEDIATEK_H__ */
--
2.18.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support
2022-04-21 6:23 [PATCH v4 0/3] Add support for different mediatek pinctrl designs Sam Shih
2022-04-21 6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
@ 2022-04-21 6:23 ` Sam Shih
2022-05-05 18:52 ` Tom Rini
2022-04-21 6:23 ` [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih
2 siblings, 1 reply; 7+ messages in thread
From: Sam Shih @ 2022-04-21 6:23 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun,
GSS_MTK_Uboot_upstream, u-boot
Cc: Sam Shih
Pinctrl design of some mediatek SoC need to access registers that
distribute in multiple memory base address. this patch introduce new
mechanism in mediatek pinctrl driver to support the chips which have
the new design.
This patch add a member 'base_calc' in pinctrl private data, and changed
original 'base' private data to an array of *iomem.
When 'base_calc' attribute is set, it will requests multiplue regs base
from the DT, if 'base_calc' attribute is not set, it only use legacy way
to request single reg resource from the DT.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
v3: fix v2 patch series misapplied
v2: fix build fail caused by patch [2/3]
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 55 +++++++++++++------
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 22 +++++++-
2 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 4ae328699e..ebab43e50a 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -45,18 +45,18 @@ static const struct mtk_drive_desc mtk_drive[] = {
static const char *mtk_pinctrl_dummy_name = "_dummy";
-static void mtk_w32(struct udevice *dev, u32 reg, u32 val)
+static void mtk_w32(struct udevice *dev, u8 i, u32 reg, u32 val)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
- __raw_writel(val, priv->base + reg);
+ __raw_writel(val, priv->base[i] + reg);
}
-static u32 mtk_r32(struct udevice *dev, u32 reg)
+static u32 mtk_r32(struct udevice *dev, u8 i, u32 reg)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
- return __raw_readl(priv->base + reg);
+ return __raw_readl(priv->base[i] + reg);
}
static inline int get_count_order(unsigned int count)
@@ -70,21 +70,28 @@ static inline int get_count_order(unsigned int count)
}
void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
+{
+ return mtk_i_rmw(dev, 0, reg, mask, set);
+}
+
+void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set)
{
u32 val;
- val = mtk_r32(dev, reg);
+ val = mtk_r32(dev, i, reg);
val &= ~mask;
val |= set;
- mtk_w32(dev, reg, val);
+ mtk_w32(dev, i, reg, val);
}
static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
const struct mtk_pin_reg_calc *rc,
struct mtk_pin_field *pfd)
{
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
const struct mtk_pin_field_calc *c, *e;
u32 bits;
+ u32 base_calc = priv->soc->base_calc;
c = rc->range;
e = c + rc->nranges;
@@ -111,6 +118,11 @@ static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
pfd->bitpos = bits % c->sz_reg;
pfd->mask = (1 << c->x_bits) - 1;
+ if (base_calc)
+ pfd->index = c->i_base;
+ else
+ pfd->index = 0;
+
/* pfd->next is used for indicating that bit wrapping-around happens
* which requires the manipulation for bit 0 starting in the next
* register to form the complete field read/write.
@@ -150,10 +162,10 @@ static void mtk_hw_write_cross_field(struct udevice *dev,
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
- mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,
+ mtk_i_rmw(dev, pf->index, pf->offset, pf->mask << pf->bitpos,
(value & pf->mask) << pf->bitpos);
- mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,
+ mtk_i_rmw(dev, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
(value & pf->mask) >> nbits_l);
}
@@ -164,8 +176,8 @@ static void mtk_hw_read_cross_field(struct udevice *dev,
mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
- l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
- h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
+ l = (mtk_r32(dev, pf->index, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
+ h = (mtk_r32(dev, pf->index, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
*value = (h << nbits_l) | l;
}
@@ -181,7 +193,7 @@ static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
return err;
if (!pf.next)
- mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos,
+ mtk_i_rmw(dev, pf.index, pf.offset, pf.mask << pf.bitpos,
(value & pf.mask) << pf.bitpos);
else
mtk_hw_write_cross_field(dev, &pf, value);
@@ -200,7 +212,7 @@ static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
return err;
if (!pf.next)
- *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask;
+ *value = (mtk_r32(dev, pf.index, pf.offset) >> pf.bitpos) & pf.mask;
else
mtk_hw_read_cross_field(dev, &pf, value);
@@ -236,7 +248,6 @@ static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector,
char *buf, int size)
{
int val, err;
-
err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val);
if (err)
return err;
@@ -722,13 +733,23 @@ int mtk_pinctrl_common_probe(struct udevice *dev,
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
int ret = 0;
-
- priv->base = dev_read_addr_ptr(dev);
- if (!priv->base)
- return -EINVAL;
+ u32 i = 0;
+ fdt_addr_t addr;
+ u32 base_calc = soc->base_calc;
+ u32 nbase_names = soc->nbase_names;
priv->soc = soc;
+ if (!base_calc)
+ nbase_names = 1;
+
+ for (i = 0; i < nbase_names; i++) {
+ addr = devfdt_get_addr_index(dev, i);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->base[i] = (void __iomem *)addr;
+ }
+
#if CONFIG_IS_ENABLED(DM_GPIO) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
ret = mtk_gpiochip_register(dev);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 735fb6fef8..91a8c0581f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -8,6 +8,8 @@
#define MTK_PINCTRL_V0 0x0
#define MTK_PINCTRL_V1 0x1
+#define BASE_CALC_NONE 0
+#define MAX_BASE_CALC 10
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_PIN(_number, _name, _drv_n) { \
@@ -24,10 +26,11 @@
id##_funcs, \
}
-#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
- _x_bits, _sz_reg, _fixed) { \
+#define PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
+ _s_bit, _x_bits, _sz_reg, _fixed) { \
.s_pin = _s_pin, \
.e_pin = _e_pin, \
+ .i_base = _i_base, \
.s_addr = _s_addr, \
.x_addrs = _x_addrs, \
.s_bit = _s_bit, \
@@ -36,6 +39,11 @@
.fixed = _fixed, \
}
+#define PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, _sz_reg, _fixed) \
+ PIN_FIELD_BASE_CALC(_s_pin, _e_pin, BASE_CALC_NONE, _s_addr, \
+ _x_addrs, _s_bit, _x_bits, _sz_reg, _fixed)
+
/* List these attributes which could be modified for the pin */
enum {
PINCTRL_PIN_REG_MODE,
@@ -70,6 +78,7 @@ enum {
/**
* struct mtk_pin_field - the structure that holds the information of the field
* used to describe the attribute for the pin
+ * @index: the index pointing to the entry in base address list
* @offset: the register offset relative to the base address
* @mask: the mask used to filter out the field from the register
* @bitpos: the start bit relative to the register
@@ -77,6 +86,7 @@ enum {
next register
*/
struct mtk_pin_field {
+ u8 index;
u32 offset;
u32 mask;
u8 bitpos;
@@ -88,6 +98,7 @@ struct mtk_pin_field {
* the guide used to look up the relevant field
* @s_pin: the start pin within the range
* @e_pin: the end pin within the range
+ * @i_base: the index pointing to the entry in base address list
* @s_addr: the start address for the range
* @x_addrs: the address distance between two consecutive registers
* within the range
@@ -101,6 +112,7 @@ struct mtk_pin_field {
struct mtk_pin_field_calc {
u16 s_pin;
u16 e_pin;
+ u8 i_base;
u32 s_addr;
u8 x_addrs;
u8 s_bit;
@@ -171,7 +183,10 @@ struct mtk_pinctrl_soc {
const struct mtk_function_desc *funcs;
int nfuncs;
int gpio_mode;
+ const char * const *base_names;
+ unsigned int nbase_names;
int rev;
+ int base_calc;
};
/**
@@ -181,7 +196,7 @@ struct mtk_pinctrl_soc {
* @soc: SoC specific data
*/
struct mtk_pinctrl_priv {
- void __iomem *base;
+ void __iomem *base[MAX_BASE_CALC];
struct mtk_pinctrl_soc *soc;
};
@@ -189,6 +204,7 @@ extern const struct pinctrl_ops mtk_pinctrl_ops;
/* A common read-modify-write helper for MediaTek chips */
void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set);
+void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set);
int mtk_pinctrl_common_probe(struct udevice *dev,
struct mtk_pinctrl_soc *soc);
--
2.18.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins
2022-04-21 6:23 [PATCH v4 0/3] Add support for different mediatek pinctrl designs Sam Shih
2022-04-21 6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
2022-04-21 6:23 ` [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
@ 2022-04-21 6:23 ` Sam Shih
2022-05-05 18:52 ` Tom Rini
2 siblings, 1 reply; 7+ messages in thread
From: Sam Shih @ 2022-04-21 6:23 UTC (permalink / raw)
To: Tom Rini, Ryder Lee, Weijie Gao, Chunfeng Yun,
GSS_MTK_Uboot_upstream, u-boot
Cc: Sam Shih
There are many pins in an SoC, and register usage may vary by pins.
This patch introduces a concept of "io type" and "io type group"
to mediatek pinctrl drivers. This can provide different pinconf
handlers implementation (eg: "bias-pull-up/down", "driving" and
"input-enable") for IO pins that belong to different types.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
v4: fix mt8518_ap1_emmc build fail
v3: fix v2 patch series misapplied
v2: fix build fail caused by patch [2/3]
---
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 48 +++++++++++++++++--
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 38 ++++++++++++++-
2 files changed, 81 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index ebab43e50a..47e2d67426 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -219,6 +219,25 @@ static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
return 0;
}
+#if CONFIG_IS_ENABLED(PINCONF)
+static int mtk_get_pin_io_type(struct udevice *dev, int pin,
+ struct mtk_io_type_desc *io_type)
+{
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ u8 io_n = priv->soc->pins[pin].io_n;
+
+ if (io_n >= priv->soc->ntype)
+ return -EINVAL;
+
+ io_type->name = priv->soc->io_type[io_n].name;
+ io_type->bias_set = priv->soc->io_type[io_n].bias_set;
+ io_type->drive_set = priv->soc->io_type[io_n].drive_set;
+ io_type->input_enable = priv->soc->io_type[io_n].input_enable;
+
+ return 0;
+}
+#endif
+
static int mtk_get_groups_count(struct udevice *dev)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
@@ -416,16 +435,25 @@ int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val)
{
int err;
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ struct mtk_io_type_desc io_type;
int rev = priv->soc->rev;
bool disable, pullup;
disable = (arg == PIN_CONFIG_BIAS_DISABLE);
pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
- if (rev == MTK_PINCTRL_V0)
+ if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
+ if (io_type.bias_set)
+ err = io_type.bias_set(dev, pin, disable, pullup,
+ val);
+ else
+ err = -EINVAL;
+
+ } else if (rev == MTK_PINCTRL_V0) {
err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val);
- else
+ } else {
err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val);
+ }
return err;
}
@@ -447,8 +475,13 @@ int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ struct mtk_io_type_desc io_type;
+
int rev = priv->soc->rev;
+ if (!mtk_get_pin_io_type(dev, pin, &io_type))
+ if (io_type.input_enable)
+ return io_type.input_enable(dev, pin, arg);
if (rev == MTK_PINCTRL_V1)
return mtk_pinconf_input_enable_v1(dev, pin, arg);
@@ -505,12 +538,19 @@ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
{
int err;
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ struct mtk_io_type_desc io_type;
int rev = priv->soc->rev;
- if (rev == MTK_PINCTRL_V0)
+ if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
+ if (io_type.drive_set)
+ err = io_type.drive_set(dev, pin, arg);
+ else
+ err = -EINVAL;
+ } else if (rev == MTK_PINCTRL_V0) {
err = mtk_pinconf_drive_set_v0(dev, pin, arg);
- else
+ } else {
err = mtk_pinconf_drive_set_v1(dev, pin, arg);
+ }
return err;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 91a8c0581f..0d9596fa72 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -12,10 +12,15 @@
#define MAX_BASE_CALC 10
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
-#define MTK_PIN(_number, _name, _drv_n) { \
+
+#define MTK_PIN(_number, _name, _drv_n) \
+ MTK_TYPED_PIN(_number, _name, _drv_n, IO_TYPE_DEFAULT)
+
+#define MTK_TYPED_PIN(_number, _name, _drv_n, _io_n) { \
.number = _number, \
.name = _name, \
.drv_n = _drv_n, \
+ .io_n = _io_n, \
}
#define PINCTRL_PIN_GROUP(name, id) \
@@ -75,6 +80,18 @@ enum {
DRV_GRP4,
};
+/* Group the pins by the io type */
+enum {
+ IO_TYPE_DEFAULT,
+ IO_TYPE_GRP0,
+ IO_TYPE_GRP1,
+ IO_TYPE_GRP2,
+ IO_TYPE_GRP3,
+ IO_TYPE_GRP4,
+ IO_TYPE_GRP5,
+ IO_TYPE_GRP6,
+};
+
/**
* struct mtk_pin_field - the structure that holds the information of the field
* used to describe the attribute for the pin
@@ -139,11 +156,13 @@ struct mtk_pin_reg_calc {
* @number: unique pin number from the global pin number space
* @name: name for this pin
* @drv_n: the index with the driving group
+ * @io_n: the index with the io type
*/
struct mtk_pin_desc {
unsigned int number;
const char *name;
u8 drv_n;
+ u8 io_n;
};
/**
@@ -172,6 +191,21 @@ struct mtk_function_desc {
int num_group_names;
};
+/**
+ * struct mtk_io_type_desc - io class descriptor for specific pins
+ * @name: name of the io class
+ */
+struct mtk_io_type_desc {
+ const char *name;
+#if CONFIG_IS_ENABLED(PINCONF)
+ /* Specific pinconfig operations */
+ int (*bias_set)(struct udevice *dev, u32 pin, bool disable,
+ bool pullup, u32 val);
+ int (*drive_set)(struct udevice *dev, u32 pin, u32 arg);
+ int (*input_enable)(struct udevice *dev, u32 pin, u32 arg);
+#endif
+};
+
/* struct mtk_pin_soc - the structure that holds SoC-specific data */
struct mtk_pinctrl_soc {
const char *name;
@@ -182,6 +216,8 @@ struct mtk_pinctrl_soc {
int ngrps;
const struct mtk_function_desc *funcs;
int nfuncs;
+ const struct mtk_io_type_desc *io_type;
+ u8 ntype;
int gpio_mode;
const char * const *base_names;
unsigned int nbase_names;
--
2.18.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions
2022-04-21 6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
@ 2022-05-05 18:52 ` Tom Rini
0 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2022-05-05 18:52 UTC (permalink / raw)
To: Sam Shih
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, GSS_MTK_Uboot_upstream, u-boot
[-- Attachment #1: Type: text/plain, Size: 729 bytes --]
On Thu, Apr 21, 2022 at 02:23:51PM +0800, Sam Shih wrote:
> There are many pins in a SoCs, and different pin may belong
> to different "io_type", For example: some pins of MT7622 belongs
> to "io_type A", the other belongs to "io_type B", and pinctrl "V0"
> means handle pinconf via "io_type A" or "io_type B", so SoCs that
> contain "io_type A" and "io_type B" pins, use "V0" in pinctrl driver.
>
> This patch separates the implementation of register operations
> (e.g: "bias-pull-up/down", "driving" and "input-enable") into
> different functions, and lets the original V0/V1
> ops to call the new functions.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support
2022-04-21 6:23 ` [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
@ 2022-05-05 18:52 ` Tom Rini
0 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2022-05-05 18:52 UTC (permalink / raw)
To: Sam Shih
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, GSS_MTK_Uboot_upstream, u-boot
[-- Attachment #1: Type: text/plain, Size: 734 bytes --]
On Thu, Apr 21, 2022 at 02:23:52PM +0800, Sam Shih wrote:
> Pinctrl design of some mediatek SoC need to access registers that
> distribute in multiple memory base address. this patch introduce new
> mechanism in mediatek pinctrl driver to support the chips which have
> the new design.
>
> This patch add a member 'base_calc' in pinctrl private data, and changed
> original 'base' private data to an array of *iomem.
>
> When 'base_calc' attribute is set, it will requests multiplue regs base
> from the DT, if 'base_calc' attribute is not set, it only use legacy way
> to request single reg resource from the DT.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins
2022-04-21 6:23 ` [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih
@ 2022-05-05 18:52 ` Tom Rini
0 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2022-05-05 18:52 UTC (permalink / raw)
To: Sam Shih
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, GSS_MTK_Uboot_upstream, u-boot
[-- Attachment #1: Type: text/plain, Size: 501 bytes --]
On Thu, Apr 21, 2022 at 02:23:53PM +0800, Sam Shih wrote:
> There are many pins in an SoC, and register usage may vary by pins.
> This patch introduces a concept of "io type" and "io type group"
> to mediatek pinctrl drivers. This can provide different pinconf
> handlers implementation (eg: "bias-pull-up/down", "driving" and
> "input-enable") for IO pins that belong to different types.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-05-05 18:53 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-21 6:23 [PATCH v4 0/3] Add support for different mediatek pinctrl designs Sam Shih
2022-04-21 6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
2022-05-05 18:52 ` Tom Rini
2022-04-21 6:23 ` [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
2022-05-05 18:52 ` Tom Rini
2022-04-21 6:23 ` [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih
2022-05-05 18:52 ` Tom Rini
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