* [PATCH v2 00/12] i915: Introduce Ponte Vecchio
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a
compute-focused platform, PVC has compute engines and enhanced copy
engines, but no render engine (there is no geometry pipeline) and no
display.
This is just a handful of early enablement patches, including some
initial support for the new copy engines (although we're not yet adding
those to the platform's engine list or exposing them to userspace just
yet).
v2:
- Drop replicated comment from forcewake patch completely and add an
additional commit to provide better documentation for forcewake and
shadowed register tables in a way that's clear for all platforms.
- Move gvt build fix to its own patch.
- Address various minor review feedback from Lucas, Tvrtko, and
Prathap.
Ayaz A Siddiqui (1):
drm/i915/pvc: Define MOCS table for PVC
John Harrison (1):
drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter
engine
Lucas De Marchi (2):
drm/i915/pvc: skip all copy engines from aux table invalidate
drm/i915/pvc: read fuses for link copy engines
Matt Roper (7):
drm/i915/uncore: Reorganize and document shadow and forcewake tables
drm/i915/pvc: Add forcewake support
drm/i915/pvc: Read correct RP_STATE_CAP register
drm/i915/gvt: Use intel_engine_mask_t for ring mask
drm/i915/pvc: Engine definitions for new copy engines
drm/i915/pvc: Interrupt support for new copy engines
drm/i915/pvc: Reset support for new copy engines
Stuart Summers (1):
drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 21 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 93 ++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 +-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 24 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_pci.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +
drivers/gpu/drm/i915/intel_device_info.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 267 +++++++++++++++---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
18 files changed, 483 insertions(+), 87 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 00/12] i915: Introduce Ponte Vecchio
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a
compute-focused platform, PVC has compute engines and enhanced copy
engines, but no render engine (there is no geometry pipeline) and no
display.
This is just a handful of early enablement patches, including some
initial support for the new copy engines (although we're not yet adding
those to the platform's engine list or exposing them to userspace just
yet).
v2:
- Drop replicated comment from forcewake patch completely and add an
additional commit to provide better documentation for forcewake and
shadowed register tables in a way that's clear for all platforms.
- Move gvt build fix to its own patch.
- Address various minor review feedback from Lucas, Tvrtko, and
Prathap.
Ayaz A Siddiqui (1):
drm/i915/pvc: Define MOCS table for PVC
John Harrison (1):
drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter
engine
Lucas De Marchi (2):
drm/i915/pvc: skip all copy engines from aux table invalidate
drm/i915/pvc: read fuses for link copy engines
Matt Roper (7):
drm/i915/uncore: Reorganize and document shadow and forcewake tables
drm/i915/pvc: Add forcewake support
drm/i915/pvc: Read correct RP_STATE_CAP register
drm/i915/gvt: Use intel_engine_mask_t for ring mask
drm/i915/pvc: Engine definitions for new copy engines
drm/i915/pvc: Interrupt support for new copy engines
drm/i915/pvc: Reset support for new copy engines
Stuart Summers (1):
drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 21 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 93 ++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 +-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 24 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_pci.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +
drivers/gpu/drm/i915/intel_device_info.h | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 267 +++++++++++++++---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
18 files changed, 483 insertions(+), 87 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, dri-devel
Let's reorganize some of the forcewake/shadow handling in intel_uncore.c
and consolidate the cargo-cult comments on each table into more general
comments that apply to all tables.
We'll probably move forcewake handling to its own dedicated file in the
near future and further enhance this with true kerneldoc. But this is a
good intermediate step to help clarify the behavior a bit.
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 125 ++++++++++++++++++----------
1 file changed, 80 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 83517a703eb6..095e071e4053 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -938,36 +938,32 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
return entry->domains;
}
-#define GEN_FW_RANGE(s, e, d) \
- { .start = (s), .end = (e), .domains = (d) }
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
-static const struct intel_forcewake_range __vlv_fw_ranges[] = {
- GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
- GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
-};
-
-#define __fwtable_reg_read_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(uncore, offset); \
- __fwd; \
-})
+/*
+ * Shadowed register tables describe special register ranges that i915 is
+ * allowed to write to without acquiring forcewake. If these registers' power
+ * wells are down, the hardware will save values written by i915 to a shadow
+ * copy and automatically transfer them into the real register the next time
+ * the power well is woken up. Shadowing only applies to writes; forcewake
+ * must still be acquired when reading from registers in these ranges.
+ *
+ * The documentation for shadowed registers is somewhat spotty on older
+ * platforms. However missing registers from these lists is non-fatal; it just
+ * means we'll wake up the hardware for some register accesses where we didn't
+ * really need to.
+ *
+ * The ranges listed in these tables must be sorted by offset.
+ *
+ * When adding new tables here, please also add them to
+ * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
-/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const struct i915_range gen8_shadowed_regs[] = {
{ .start = 0x2030, .end = 0x2030 },
{ .start = 0xA008, .end = 0xA00C },
{ .start = 0x12030, .end = 0x12030 },
{ .start = 0x1a030, .end = 0x1a030 },
{ .start = 0x22030, .end = 0x22030 },
- /* TODO: Other registers are not yet used */
};
static const struct i915_range gen11_shadowed_regs[] = {
@@ -1107,11 +1103,71 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
return FORCEWAKE_RENDER;
}
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ if (NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
+ __fwd; \
+})
+
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
+#define GEN_FW_RANGE(s, e, d) \
+ { .start = (s), .end = (e), .domains = (d) }
+
+/*
+ * All platforms' forcewake tables below must be sorted by offset ranges.
+ * Furthermore, new forcewake tables added should be "watertight" and have
+ * no gaps between ranges.
+ *
+ * When there are multiple consecutive ranges listed in the bspec with
+ * the same forcewake domain, it is customary to combine them into a single
+ * row in the tables below to keep the tables small and lookups fast.
+ * Likewise, reserved/unused ranges may be combined with the preceding and/or
+ * following ranges since the driver will never be making MMIO accesses in
+ * those ranges.
+ *
+ * For example, if the bspec were to list:
+ *
+ * ...
+ * 0x1000 - 0x1fff: GT
+ * 0x2000 - 0x2cff: GT
+ * 0x2d00 - 0x2fff: unused/reserved
+ * 0x3000 - 0xffff: GT
+ * ...
+ *
+ * these could all be represented by a single line in the code:
+ *
+ * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
+ *
+ * When adding new forcewake tables here, please also add them to
+ * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
+
static const struct intel_forcewake_range __gen6_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __vlv_fw_ranges[] = {
+ GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
+ GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
+ GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
+};
+
+
static const struct intel_forcewake_range __chv_fw_ranges[] = {
GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
@@ -1131,16 +1187,6 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_write_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- const u32 __offset = (offset); \
- if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
- __fwd = find_fw_domain(uncore, __offset); \
- __fwd; \
-})
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
@@ -1176,7 +1222,6 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
@@ -1215,14 +1260,6 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
};
-/*
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
- *
- * Note that the spec lists several reserved/unused ranges that don't
- * actually contain any registers. In the table below we'll combine those
- * reserved ranges with either the preceding or following range to keep the
- * table small and lookups fast.
- */
static const struct intel_forcewake_range __gen12_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x1fff, 0), /*
0x0 - 0xaff: reserved
@@ -1327,8 +1364,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
/*
* Graphics IP version 12.55 brings a slight change to the 0xd800 range,
* switching it from the GT domain to the render domain.
- *
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
*/
#define XEHP_FWRANGES(FW_RANGE_D800) \
GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Let's reorganize some of the forcewake/shadow handling in intel_uncore.c
and consolidate the cargo-cult comments on each table into more general
comments that apply to all tables.
We'll probably move forcewake handling to its own dedicated file in the
near future and further enhance this with true kerneldoc. But this is a
good intermediate step to help clarify the behavior a bit.
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 125 ++++++++++++++++++----------
1 file changed, 80 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 83517a703eb6..095e071e4053 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -938,36 +938,32 @@ find_fw_domain(struct intel_uncore *uncore, u32 offset)
return entry->domains;
}
-#define GEN_FW_RANGE(s, e, d) \
- { .start = (s), .end = (e), .domains = (d) }
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
-static const struct intel_forcewake_range __vlv_fw_ranges[] = {
- GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
- GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
- GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
- GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
-};
-
-#define __fwtable_reg_read_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- if (NEEDS_FORCE_WAKE((offset))) \
- __fwd = find_fw_domain(uncore, offset); \
- __fwd; \
-})
+/*
+ * Shadowed register tables describe special register ranges that i915 is
+ * allowed to write to without acquiring forcewake. If these registers' power
+ * wells are down, the hardware will save values written by i915 to a shadow
+ * copy and automatically transfer them into the real register the next time
+ * the power well is woken up. Shadowing only applies to writes; forcewake
+ * must still be acquired when reading from registers in these ranges.
+ *
+ * The documentation for shadowed registers is somewhat spotty on older
+ * platforms. However missing registers from these lists is non-fatal; it just
+ * means we'll wake up the hardware for some register accesses where we didn't
+ * really need to.
+ *
+ * The ranges listed in these tables must be sorted by offset.
+ *
+ * When adding new tables here, please also add them to
+ * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
-/* *Must* be sorted by offset! See intel_shadow_table_check(). */
static const struct i915_range gen8_shadowed_regs[] = {
{ .start = 0x2030, .end = 0x2030 },
{ .start = 0xA008, .end = 0xA00C },
{ .start = 0x12030, .end = 0x12030 },
{ .start = 0x1a030, .end = 0x1a030 },
{ .start = 0x22030, .end = 0x22030 },
- /* TODO: Other registers are not yet used */
};
static const struct i915_range gen11_shadowed_regs[] = {
@@ -1107,11 +1103,71 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
return FORCEWAKE_RENDER;
}
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ if (NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
+ __fwd; \
+})
+
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
+
+#define GEN_FW_RANGE(s, e, d) \
+ { .start = (s), .end = (e), .domains = (d) }
+
+/*
+ * All platforms' forcewake tables below must be sorted by offset ranges.
+ * Furthermore, new forcewake tables added should be "watertight" and have
+ * no gaps between ranges.
+ *
+ * When there are multiple consecutive ranges listed in the bspec with
+ * the same forcewake domain, it is customary to combine them into a single
+ * row in the tables below to keep the tables small and lookups fast.
+ * Likewise, reserved/unused ranges may be combined with the preceding and/or
+ * following ranges since the driver will never be making MMIO accesses in
+ * those ranges.
+ *
+ * For example, if the bspec were to list:
+ *
+ * ...
+ * 0x1000 - 0x1fff: GT
+ * 0x2000 - 0x2cff: GT
+ * 0x2d00 - 0x2fff: unused/reserved
+ * 0x3000 - 0xffff: GT
+ * ...
+ *
+ * these could all be represented by a single line in the code:
+ *
+ * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT)
+ *
+ * When adding new forcewake tables here, please also add them to
+ * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be
+ * scanned for obvious mistakes or typos by the selftests.
+ */
+
static const struct intel_forcewake_range __gen6_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __vlv_fw_ranges[] = {
+ GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA),
+ GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA),
+ GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
+};
+
+
static const struct intel_forcewake_range __chv_fw_ranges[] = {
GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA),
@@ -1131,16 +1187,6 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
};
-#define __fwtable_reg_write_fw_domains(uncore, offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- const u32 __offset = (offset); \
- if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
- __fwd = find_fw_domain(uncore, __offset); \
- __fwd; \
-})
-
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT),
GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
@@ -1176,7 +1222,6 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
-/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */
GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
@@ -1215,14 +1260,6 @@ static const struct intel_forcewake_range __gen11_fw_ranges[] = {
GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0)
};
-/*
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
- *
- * Note that the spec lists several reserved/unused ranges that don't
- * actually contain any registers. In the table below we'll combine those
- * reserved ranges with either the preceding or following range to keep the
- * table small and lookups fast.
- */
static const struct intel_forcewake_range __gen12_fw_ranges[] = {
GEN_FW_RANGE(0x0, 0x1fff, 0), /*
0x0 - 0xaff: reserved
@@ -1327,8 +1364,6 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = {
/*
* Graphics IP version 12.55 brings a slight change to the 0xd800 range,
* switching it from the GT domain to the render domain.
- *
- * *Must* be sorted by offset ranges! See intel_fw_table_check().
*/
#define XEHP_FWRANGES(FW_RANGE_D800) \
GEN_FW_RANGE(0x0, 0x1fff, 0), /* \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 02/12] drm/i915/pvc: Add forcewake support
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, Daniele Ceraolo Spurio, dri-devel
Add PVC's forcewake ranges.
v2:
- Drop replicated comment completely; move general cleanup of the
documentation to a separate patch.
Bspec: 67609
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 142 +++++++++++++++++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 143 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 095e071e4053..fac0ff60bfbf 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1076,6 +1076,45 @@ static const struct i915_range dg2_shadowed_regs[] = {
{ .start = 0x1F8510, .end = 0x1F8550 },
};
+static const struct i915_range pvc_shadowed_regs[] = {
+ { .start = 0x2030, .end = 0x2030 },
+ { .start = 0x2510, .end = 0x2550 },
+ { .start = 0xA008, .end = 0xA00C },
+ { .start = 0xA188, .end = 0xA188 },
+ { .start = 0xA278, .end = 0xA278 },
+ { .start = 0xA540, .end = 0xA56C },
+ { .start = 0xC4C8, .end = 0xC4C8 },
+ { .start = 0xC4E0, .end = 0xC4E0 },
+ { .start = 0xC600, .end = 0xC600 },
+ { .start = 0xC658, .end = 0xC658 },
+ { .start = 0x22030, .end = 0x22030 },
+ { .start = 0x22510, .end = 0x22550 },
+ { .start = 0x1C0030, .end = 0x1C0030 },
+ { .start = 0x1C0510, .end = 0x1C0550 },
+ { .start = 0x1C4030, .end = 0x1C4030 },
+ { .start = 0x1C4510, .end = 0x1C4550 },
+ { .start = 0x1C8030, .end = 0x1C8030 },
+ { .start = 0x1C8510, .end = 0x1C8550 },
+ { .start = 0x1D0030, .end = 0x1D0030 },
+ { .start = 0x1D0510, .end = 0x1D0550 },
+ { .start = 0x1D4030, .end = 0x1D4030 },
+ { .start = 0x1D4510, .end = 0x1D4550 },
+ { .start = 0x1D8030, .end = 0x1D8030 },
+ { .start = 0x1D8510, .end = 0x1D8550 },
+ { .start = 0x1E0030, .end = 0x1E0030 },
+ { .start = 0x1E0510, .end = 0x1E0550 },
+ { .start = 0x1E4030, .end = 0x1E4030 },
+ { .start = 0x1E4510, .end = 0x1E4550 },
+ { .start = 0x1E8030, .end = 0x1E8030 },
+ { .start = 0x1E8510, .end = 0x1E8550 },
+ { .start = 0x1F0030, .end = 0x1F0030 },
+ { .start = 0x1F0510, .end = 0x1F0550 },
+ { .start = 0x1F4030, .end = 0x1F4030 },
+ { .start = 0x1F4510, .end = 0x1F4550 },
+ { .start = 0x1F8030, .end = 0x1F8030 },
+ { .start = 0x1F8510, .end = 0x1F8550 },
+};
+
static int mmio_range_cmp(u32 key, const struct i915_range *range)
{
if (key < range->start)
@@ -1525,6 +1564,103 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
+static const struct intel_forcewake_range __pvc_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, 0),
+ GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0xc00, 0xfff, 0),
+ GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
+ 0x4000 - 0x4aff: gt
+ 0x4b00 - 0x4fff: reserved
+ 0x5000 - 0x51ff: gt
+ 0x5200 - 0x52ff: reserved
+ 0x5300 - 0x53ff: gt
+ 0x5400 - 0x7fff: reserved
+ 0x8000 - 0x813f: gt */
+ GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8180, 0x81ff, 0),
+ GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
+ 0x8200 - 0x82ff: gt
+ 0x8300 - 0x84ff: reserved
+ 0x8500 - 0x887f: gt
+ 0x8880 - 0x8a7f: reserved
+ 0x8a80 - 0x8aff: gt
+ 0x8b00 - 0x8fff: reserved
+ 0x9000 - 0x947f: gt
+ 0x9480 - 0x94cf: reserved */
+ GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
+ 0x9600 - 0x967f: reserved */
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
+ 0x9700 - 0x97ff: reserved */
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
+ 0xb500 - 0xbfff: reserved
+ 0xc000 - 0xcfff: gt */
+ GEN_FW_RANGE(0xd000, 0xd3ff, 0),
+ GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
+ 0xde00 - 0xde7f: reserved */
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdeff: render
+ 0xdf00 - 0xe1ff: reserved
+ 0xe200 - 0xe7ff: render
+ 0xe800 - 0xe8ff: reserved */
+ GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
+ 0xea00 - 0xebff: reserved
+ 0xec00 - 0xffff: gt
+ 0x10000 - 0x11fff: reserved */
+ GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
+ 0x12000 - 0x127ff: always on
+ 0x12800 - 0x12fff: reserved */
+ GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
+ 0x13000 - 0x135ff: gt
+ 0x13600 - 0x147ff: reserved
+ 0x14800 - 0x153ff: gt
+ 0x15400 - 0x19fff: reserved
+ 0x1a000 - 0x1ffff: gt
+ 0x20000 - 0x21fff: reserved
+ 0x22000 - 0x23fff: gt */
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 24000 - 0x2407f: always on
+ 24080 - 0x2417f: reserved */
+ GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
+ 0x24200 - 0x251ff: reserved
+ 0x25200 - 0x252ff: gt
+ 0x25300 - 0x25fff: reserved
+ 0x26000 - 0x27fff: gt
+ 0x28000 - 0x2ffff: reserved
+ 0x30000 - 0x3ffff: gt */
+ GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
+ 0x1c2c00 - 0x1c2cff: reserved
+ 0x1c2d00 - 0x1c2dff: VD0
+ 0x1c2e00 - 0x1c3eff: reserved
+ 0x1c3f00 - 0x1c3fff: VD0 */
+ GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6aff: VD1
+ 0x1c6b00 - 0x1c7eff: reserved
+ 0x1c7f00 - 0x1c7fff: VD1
+ 0x1c8000 - 0x1cffff: reserved */
+ GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2aff: VD2
+ 0x1d2b00 - 0x1d3eff: reserved
+ 0x1d3f00 - 0x1d3fff: VD2
+ 0x1d4000 - 0x23ffff: reserved */
+ GEN_FW_RANGE(0x240000, 0x3dffff, 0),
+ GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
+};
+
static void
ilk_dummy_write(struct intel_uncore *uncore)
{
@@ -2160,7 +2296,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
+ ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index cdd196783535..fda9bb79c049 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -69,6 +69,7 @@ static int intel_shadow_table_check(void)
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
+ { pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
};
const struct i915_range *range;
unsigned int i, j;
@@ -115,6 +116,7 @@ int intel_uncore_mock_selftests(void)
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
{ __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
+ { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
};
int err, i;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 02/12] drm/i915/pvc: Add forcewake support
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add PVC's forcewake ranges.
v2:
- Drop replicated comment completely; move general cleanup of the
documentation to a separate patch.
Bspec: 67609
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 142 +++++++++++++++++-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +
2 files changed, 143 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 095e071e4053..fac0ff60bfbf 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1076,6 +1076,45 @@ static const struct i915_range dg2_shadowed_regs[] = {
{ .start = 0x1F8510, .end = 0x1F8550 },
};
+static const struct i915_range pvc_shadowed_regs[] = {
+ { .start = 0x2030, .end = 0x2030 },
+ { .start = 0x2510, .end = 0x2550 },
+ { .start = 0xA008, .end = 0xA00C },
+ { .start = 0xA188, .end = 0xA188 },
+ { .start = 0xA278, .end = 0xA278 },
+ { .start = 0xA540, .end = 0xA56C },
+ { .start = 0xC4C8, .end = 0xC4C8 },
+ { .start = 0xC4E0, .end = 0xC4E0 },
+ { .start = 0xC600, .end = 0xC600 },
+ { .start = 0xC658, .end = 0xC658 },
+ { .start = 0x22030, .end = 0x22030 },
+ { .start = 0x22510, .end = 0x22550 },
+ { .start = 0x1C0030, .end = 0x1C0030 },
+ { .start = 0x1C0510, .end = 0x1C0550 },
+ { .start = 0x1C4030, .end = 0x1C4030 },
+ { .start = 0x1C4510, .end = 0x1C4550 },
+ { .start = 0x1C8030, .end = 0x1C8030 },
+ { .start = 0x1C8510, .end = 0x1C8550 },
+ { .start = 0x1D0030, .end = 0x1D0030 },
+ { .start = 0x1D0510, .end = 0x1D0550 },
+ { .start = 0x1D4030, .end = 0x1D4030 },
+ { .start = 0x1D4510, .end = 0x1D4550 },
+ { .start = 0x1D8030, .end = 0x1D8030 },
+ { .start = 0x1D8510, .end = 0x1D8550 },
+ { .start = 0x1E0030, .end = 0x1E0030 },
+ { .start = 0x1E0510, .end = 0x1E0550 },
+ { .start = 0x1E4030, .end = 0x1E4030 },
+ { .start = 0x1E4510, .end = 0x1E4550 },
+ { .start = 0x1E8030, .end = 0x1E8030 },
+ { .start = 0x1E8510, .end = 0x1E8550 },
+ { .start = 0x1F0030, .end = 0x1F0030 },
+ { .start = 0x1F0510, .end = 0x1F0550 },
+ { .start = 0x1F4030, .end = 0x1F4030 },
+ { .start = 0x1F4510, .end = 0x1F4550 },
+ { .start = 0x1F8030, .end = 0x1F8030 },
+ { .start = 0x1F8510, .end = 0x1F8550 },
+};
+
static int mmio_range_cmp(u32 key, const struct i915_range *range)
{
if (key < range->start)
@@ -1525,6 +1564,103 @@ static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
};
+static const struct intel_forcewake_range __pvc_fw_ranges[] = {
+ GEN_FW_RANGE(0x0, 0xaff, 0),
+ GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0xc00, 0xfff, 0),
+ GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
+ 0x4000 - 0x4aff: gt
+ 0x4b00 - 0x4fff: reserved
+ 0x5000 - 0x51ff: gt
+ 0x5200 - 0x52ff: reserved
+ 0x5300 - 0x53ff: gt
+ 0x5400 - 0x7fff: reserved
+ 0x8000 - 0x813f: gt */
+ GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x8180, 0x81ff, 0),
+ GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
+ 0x8200 - 0x82ff: gt
+ 0x8300 - 0x84ff: reserved
+ 0x8500 - 0x887f: gt
+ 0x8880 - 0x8a7f: reserved
+ 0x8a80 - 0x8aff: gt
+ 0x8b00 - 0x8fff: reserved
+ 0x9000 - 0x947f: gt
+ 0x9480 - 0x94cf: reserved */
+ GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
+ 0x9600 - 0x967f: reserved */
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
+ 0x9700 - 0x97ff: reserved */
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
+ 0xb500 - 0xbfff: reserved
+ 0xc000 - 0xcfff: gt */
+ GEN_FW_RANGE(0xd000, 0xd3ff, 0),
+ GEN_FW_RANGE(0xd400, 0xdbff, FORCEWAKE_GT),
+ GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER),
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
+ 0xde00 - 0xde7f: reserved */
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdeff: render
+ 0xdf00 - 0xe1ff: reserved
+ 0xe200 - 0xe7ff: render
+ 0xe800 - 0xe8ff: reserved */
+ GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
+ 0xea00 - 0xebff: reserved
+ 0xec00 - 0xffff: gt
+ 0x10000 - 0x11fff: reserved */
+ GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
+ 0x12000 - 0x127ff: always on
+ 0x12800 - 0x12fff: reserved */
+ GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
+ 0x13000 - 0x135ff: gt
+ 0x13600 - 0x147ff: reserved
+ 0x14800 - 0x153ff: gt
+ 0x15400 - 0x19fff: reserved
+ 0x1a000 - 0x1ffff: gt
+ 0x20000 - 0x21fff: reserved
+ 0x22000 - 0x23fff: gt */
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 24000 - 0x2407f: always on
+ 24080 - 0x2417f: reserved */
+ GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
+ 0x24200 - 0x251ff: reserved
+ 0x25200 - 0x252ff: gt
+ 0x25300 - 0x25fff: reserved
+ 0x26000 - 0x27fff: gt
+ 0x28000 - 0x2ffff: reserved
+ 0x30000 - 0x3ffff: gt */
+ GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
+ 0x1c2c00 - 0x1c2cff: reserved
+ 0x1c2d00 - 0x1c2dff: VD0
+ 0x1c2e00 - 0x1c3eff: reserved
+ 0x1c3f00 - 0x1c3fff: VD0 */
+ GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6aff: VD1
+ 0x1c6b00 - 0x1c7eff: reserved
+ 0x1c7f00 - 0x1c7fff: VD1
+ 0x1c8000 - 0x1cffff: reserved */
+ GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2aff: VD2
+ 0x1d2b00 - 0x1d3eff: reserved
+ 0x1d3f00 - 0x1d3fff: VD2
+ 0x1d4000 - 0x23ffff: reserved */
+ GEN_FW_RANGE(0x240000, 0x3dffff, 0),
+ GEN_FW_RANGE(0x3e0000, 0x3effff, FORCEWAKE_GT),
+};
+
static void
ilk_dummy_write(struct intel_uncore *uncore)
{
@@ -2160,7 +2296,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60)) {
+ ASSIGN_FW_DOMAINS_TABLE(uncore, __pvc_fw_ranges);
+ ASSIGN_SHADOW_TABLE(uncore, pvc_shadowed_regs);
+ ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index cdd196783535..fda9bb79c049 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -69,6 +69,7 @@ static int intel_shadow_table_check(void)
{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
{ gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
{ dg2_shadowed_regs, ARRAY_SIZE(dg2_shadowed_regs) },
+ { pvc_shadowed_regs, ARRAY_SIZE(pvc_shadowed_regs) },
};
const struct i915_range *range;
unsigned int i, j;
@@ -115,6 +116,7 @@ int intel_uncore_mock_selftests(void)
{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
{ __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
{ __xehp_fw_ranges, ARRAY_SIZE(__xehp_fw_ranges), true },
+ { __pvc_fw_ranges, ARRAY_SIZE(__pvc_fw_ranges), true },
};
int err, i;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Fei Yang, Lucas De Marchi, Ayaz A Siddiqui, dri-devel
From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
v2 (MattR):
- Clarify comment above RING_CMD_CCTL programming.
- Remove bspec reference from field definition. (Lucas)
- Add WARN if we try to use a (presumably uninitialized) wb_index of 0.
On most platforms 0 is an invalid MOCS entry and even on the ones
where it isn't, it isn't the right setting for wb_index. (Lucas)
Bspec: 45101, 72161
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b06611c1d4ad..7853ea194ea6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -221,6 +221,7 @@ struct intel_gt {
struct {
u8 uc_index;
+ u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
} mocs;
struct intel_pxp pxp;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8c..c6ebe2781076 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
unsigned int n_entries;
const struct drm_i915_mocs_entry *table;
u8 uc_index;
+ u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
u8 unused_entries_index;
};
@@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+#define PVC_NUM_MOCS_ENTRIES 3
/* (e)LLC caching options */
/*
@@ -394,6 +396,17 @@ static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
+static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_3_WB),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* WB */
+ MOCS_ENTRY(2, 0, L3_3_WB),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -423,7 +436,14 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_DG2(i915)) {
+ if (IS_PONTEVECCHIO(i915)) {
+ table->size = ARRAY_SIZE(pvc_mocs_table);
+ table->table = pvc_mocs_table;
+ table->n_entries = PVC_NUM_MOCS_ENTRIES;
+ table->uc_index = 1;
+ table->wb_index = 2;
+ table->unused_entries_index = 2;
+ } else if (IS_DG2(i915)) {
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
table->table = dg2_mocs_table_g10_ax;
@@ -622,6 +642,8 @@ void intel_set_mocs_index(struct intel_gt *gt)
get_mocs_settings(gt->i915, &table);
gt->mocs.uc_index = table.uc_index;
+ if (HAS_L3_CCS_READ(gt->i915))
+ gt->mocs.wb_index = table.wb_index;
}
void intel_mocs_init(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a05c4b99b3fb..756807c4b405 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1994,19 +1994,37 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
static void
engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- u8 mocs;
+ u8 mocs_w, mocs_r;
/*
- * RING_CMD_CCTL are need to be programed to un-cached
- * for memory writes and reads outputted by Command
- * Streamers on Gen12 onward platforms.
+ * RING_CMD_CCTL specifies the default MOCS entry that will be used
+ * by the command streamer when executing commands that don't have
+ * a way to explicitly specify a MOCS setting. The default should
+ * usually reference whichever MOCS entry corresponds to uncached
+ * behavior, although use of a WB cached entry is recommended by the
+ * spec in certain circumstances on specific platforms.
*/
if (GRAPHICS_VER(engine->i915) >= 12) {
- mocs = engine->gt->mocs.uc_index;
+ mocs_r = engine->gt->mocs.uc_index;
+ mocs_w = engine->gt->mocs.uc_index;
+
+ if (HAS_L3_CCS_READ(engine->i915) &&
+ engine->class == COMPUTE_CLASS) {
+ mocs_r = engine->gt->mocs.wb_index;
+
+ /*
+ * Even on the few platforms where MOCS 0 is a
+ * legitimate table entry, it's never the correct
+ * setting to use here; we can assume the MOCS init
+ * just forgot to initialize wb_index.
+ */
+ drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
+ }
+
wa_masked_field_set(wal,
RING_CMD_CCTL(engine->mmio_base),
CMD_CCTL_MOCS_MASK,
- CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
+ CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 00d7eeae33bd..b389674b5210 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1370,6 +1370,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
+#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
+
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 498708b33924..07722cdf63ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1076,7 +1076,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
- .dma_mask_size = 52
+ .dma_mask_size = 52, \
+ .has_l3_ccs_read = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e7d2cf7d65c8..09e33296157a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -150,6 +150,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+ func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
v2 (MattR):
- Clarify comment above RING_CMD_CCTL programming.
- Remove bspec reference from field definition. (Lucas)
- Add WARN if we try to use a (presumably uninitialized) wb_index of 0.
On most platforms 0 is an invalid MOCS entry and even on the ones
where it isn't, it isn't the right setting for wb_index. (Lucas)
Bspec: 45101, 72161
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b06611c1d4ad..7853ea194ea6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -221,6 +221,7 @@ struct intel_gt {
struct {
u8 uc_index;
+ u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
} mocs;
struct intel_pxp pxp;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8c..c6ebe2781076 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
unsigned int n_entries;
const struct drm_i915_mocs_entry *table;
u8 uc_index;
+ u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
u8 unused_entries_index;
};
@@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
+#define PVC_NUM_MOCS_ENTRIES 3
/* (e)LLC caching options */
/*
@@ -394,6 +396,17 @@ static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
};
+static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
+ /* Error */
+ MOCS_ENTRY(0, 0, L3_3_WB),
+
+ /* UC */
+ MOCS_ENTRY(1, 0, L3_1_UC),
+
+ /* WB */
+ MOCS_ENTRY(2, 0, L3_3_WB),
+};
+
enum {
HAS_GLOBAL_MOCS = BIT(0),
HAS_ENGINE_MOCS = BIT(1),
@@ -423,7 +436,14 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_DG2(i915)) {
+ if (IS_PONTEVECCHIO(i915)) {
+ table->size = ARRAY_SIZE(pvc_mocs_table);
+ table->table = pvc_mocs_table;
+ table->n_entries = PVC_NUM_MOCS_ENTRIES;
+ table->uc_index = 1;
+ table->wb_index = 2;
+ table->unused_entries_index = 2;
+ } else if (IS_DG2(i915)) {
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
table->table = dg2_mocs_table_g10_ax;
@@ -622,6 +642,8 @@ void intel_set_mocs_index(struct intel_gt *gt)
get_mocs_settings(gt->i915, &table);
gt->mocs.uc_index = table.uc_index;
+ if (HAS_L3_CCS_READ(gt->i915))
+ gt->mocs.wb_index = table.wb_index;
}
void intel_mocs_init(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a05c4b99b3fb..756807c4b405 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1994,19 +1994,37 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
static void
engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- u8 mocs;
+ u8 mocs_w, mocs_r;
/*
- * RING_CMD_CCTL are need to be programed to un-cached
- * for memory writes and reads outputted by Command
- * Streamers on Gen12 onward platforms.
+ * RING_CMD_CCTL specifies the default MOCS entry that will be used
+ * by the command streamer when executing commands that don't have
+ * a way to explicitly specify a MOCS setting. The default should
+ * usually reference whichever MOCS entry corresponds to uncached
+ * behavior, although use of a WB cached entry is recommended by the
+ * spec in certain circumstances on specific platforms.
*/
if (GRAPHICS_VER(engine->i915) >= 12) {
- mocs = engine->gt->mocs.uc_index;
+ mocs_r = engine->gt->mocs.uc_index;
+ mocs_w = engine->gt->mocs.uc_index;
+
+ if (HAS_L3_CCS_READ(engine->i915) &&
+ engine->class == COMPUTE_CLASS) {
+ mocs_r = engine->gt->mocs.wb_index;
+
+ /*
+ * Even on the few platforms where MOCS 0 is a
+ * legitimate table entry, it's never the correct
+ * setting to use here; we can assume the MOCS init
+ * just forgot to initialize wb_index.
+ */
+ drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
+ }
+
wa_masked_field_set(wal,
RING_CMD_CCTL(engine->mmio_base),
CMD_CCTL_MOCS_MASK,
- CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
+ CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 00d7eeae33bd..b389674b5210 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1370,6 +1370,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
+#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
+
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 498708b33924..07722cdf63ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1076,7 +1076,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
- .dma_mask_size = 52
+ .dma_mask_size = 52, \
+ .has_l3_ccs_read = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e7d2cf7d65c8..09e33296157a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -150,6 +150,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+ func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
The SoC registers, including RP_STATE_CAP, have moved to a new location
in GTTMMADR on Ponte Vecchio. We need to update the register offset
accordingly.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3476a11f294c..3bd8415a0f1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1075,7 +1075,9 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
- if (IS_XEHPSDV(i915))
+ if (IS_PONTEVECCHIO(i915))
+ return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
+ else if (IS_XEHPSDV(i915))
return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
else if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ccb67eec1bd..4a3d7b96ef43 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1846,6 +1846,7 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
+#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
The SoC registers, including RP_STATE_CAP, have moved to a new location
in GTTMMADR on Ponte Vecchio. We need to update the register offset
accordingly.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3476a11f294c..3bd8415a0f1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1075,7 +1075,9 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps)
struct drm_i915_private *i915 = rps_to_i915(rps);
struct intel_uncore *uncore = rps_to_uncore(rps);
- if (IS_XEHPSDV(i915))
+ if (IS_PONTEVECCHIO(i915))
+ return intel_uncore_read(uncore, PVC_RP_STATE_CAP);
+ else if (IS_XEHPSDV(i915))
return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);
else if (IS_GEN9_LP(i915))
return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ccb67eec1bd..4a3d7b96ef43 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1846,6 +1846,7 @@
#define BXT_RP_STATE_CAP _MMIO(0x138170)
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
+#define PVC_RP_STATE_CAP _MMIO(0x281014)
#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, dri-devel
From: Stuart Summers <stuart.summers@intel.com>
Although we already strip 3D-specific flags from PIPE_CONTROL
instructions when submitting to a compute engine, there are some
additional flags that need to be removed when the platform as a whole
lacks a 3D pipeline. Add those restrictions here.
Bspec: 47112
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
5 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3e13960615bd..11c72792573d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
- if (engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
@@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
- if (engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
if (!HAS_FLAT_CCS(rq->engine->i915))
count = 8 + 4;
@@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
- if (rq->engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(rq->engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (rq->engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
cs = gen12_emit_ggtt_write_rcs(cs,
rq->fence.seqno,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be804..900755f4b787 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -288,8 +288,8 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
-/* 3D-related flags can't be set on compute engine */
-#define PIPE_CONTROL_3D_FLAGS (\
+/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
PIPE_CONTROL_TILE_CACHE_FLUSH | \
@@ -300,6 +300,14 @@
PIPE_CONTROL_VF_CACHE_INVALIDATE | \
PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
+ PIPE_CONTROL_3D_ENGINE_FLAGS | \
+ PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
+ PIPE_CONTROL_FLUSH_ENABLE | \
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+ PIPE_CONTROL_DC_FLUSH_ENABLE)
+
#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
/* Opcodes for MI_MATH_INSTR */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b389674b5210..1e153cefc92e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 07722cdf63ac..14e0e8225324 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .lacks_3d_pipeline = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 09e33296157a..972084676984 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -165,7 +165,8 @@ enum intel_ppgtt_type {
func(has_snoop); \
func(has_coherent_ggtt); \
func(unfenced_needs_alignment); \
- func(hws_needs_physical);
+ func(hws_needs_physical); \
+ func(lacks_3d_pipeline);
#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
/* Keep in alphabetical order */ \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Stuart Summers <stuart.summers@intel.com>
Although we already strip 3D-specific flags from PIPE_CONTROL
instructions when submitting to a compute engine, there are some
additional flags that need to be removed when the platform as a whole
lacks a 3D pipeline. Add those restrictions here.
Bspec: 47112
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
5 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3e13960615bd..11c72792573d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
- if (engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
cs = intel_ring_begin(rq, 6);
if (IS_ERR(cs))
@@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
flags |= PIPE_CONTROL_CS_STALL;
- if (engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
if (!HAS_FLAT_CCS(rq->engine->i915))
count = 8 + 4;
@@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
- if (rq->engine->class == COMPUTE_CLASS)
- flags &= ~PIPE_CONTROL_3D_FLAGS;
+ if (LACKS_3D_PIPELINE(rq->engine->i915))
+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
+ else if (rq->engine->class == COMPUTE_CLASS)
+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
cs = gen12_emit_ggtt_write_rcs(cs,
rq->fence.seqno,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be804..900755f4b787 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -288,8 +288,8 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
-/* 3D-related flags can't be set on compute engine */
-#define PIPE_CONTROL_3D_FLAGS (\
+/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
PIPE_CONTROL_TILE_CACHE_FLUSH | \
@@ -300,6 +300,14 @@
PIPE_CONTROL_VF_CACHE_INVALIDATE | \
PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
+ PIPE_CONTROL_3D_ENGINE_FLAGS | \
+ PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
+ PIPE_CONTROL_FLUSH_ENABLE | \
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
+ PIPE_CONTROL_DC_FLUSH_ENABLE)
+
#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
/* Opcodes for MI_MATH_INSTR */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b389674b5210..1e153cefc92e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 07722cdf63ac..14e0e8225324 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .lacks_3d_pipeline = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 09e33296157a..972084676984 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -165,7 +165,8 @@ enum intel_ppgtt_type {
func(has_snoop); \
func(has_coherent_ggtt); \
func(unfenced_needs_alignment); \
- func(hws_needs_physical);
+ func(hws_needs_physical); \
+ func(lacks_3d_pipeline);
#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
/* Keep in alphabetical order */ \
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx
Cc: José Roberto de Souza, Tvrtko Ursulin, John Harrison, dri-devel
From: John Harrison <John.C.Harrison@Intel.com>
PVC adds extra blitter engines (in the following patch). The reset
selftest has a local array on the stack which is sized by the number
of engines. The increase pushes the size of this array to the point
where it trips the 'stack too large' compile warning. This patch takes
the allocation of the stack and makes it dynamic instead.
v2 (MattR):
- Minor cosmetic changes: re-sort definition and allocate using
kmalloc_array(). (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 83ff4c2e57c5..6493265d5f64 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -976,6 +976,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
{
struct i915_gpu_error *global = >->i915->gpu_error;
struct intel_engine_cs *engine, *other;
+ struct active_engine *threads;
enum intel_engine_id id, tmp;
struct hang h;
int err = 0;
@@ -996,8 +997,11 @@ static int __igt_reset_engines(struct intel_gt *gt,
h.ctx->sched.priority = 1024;
}
+ threads = kmalloc_array(I915_NUM_ENGINES, sizeof(*threads), GFP_KERNEL);
+ if (!threads)
+ return -ENOMEM;
+
for_each_engine(engine, gt, id) {
- struct active_engine threads[I915_NUM_ENGINES] = {};
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
bool using_guc = intel_engine_uses_guc(engine);
@@ -1016,7 +1020,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
break;
}
- memset(threads, 0, sizeof(threads));
+ memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
for_each_engine(other, gt, tmp) {
struct task_struct *tsk;
@@ -1236,6 +1240,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
break;
}
}
+ kfree(threads);
if (intel_gt_is_wedged(gt))
err = -EIO;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: John Harrison <John.C.Harrison@Intel.com>
PVC adds extra blitter engines (in the following patch). The reset
selftest has a local array on the stack which is sized by the number
of engines. The increase pushes the size of this array to the point
where it trips the 'stack too large' compile warning. This patch takes
the allocation of the stack and makes it dynamic instead.
v2 (MattR):
- Minor cosmetic changes: re-sort definition and allocate using
kmalloc_array(). (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 83ff4c2e57c5..6493265d5f64 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -976,6 +976,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
{
struct i915_gpu_error *global = >->i915->gpu_error;
struct intel_engine_cs *engine, *other;
+ struct active_engine *threads;
enum intel_engine_id id, tmp;
struct hang h;
int err = 0;
@@ -996,8 +997,11 @@ static int __igt_reset_engines(struct intel_gt *gt,
h.ctx->sched.priority = 1024;
}
+ threads = kmalloc_array(I915_NUM_ENGINES, sizeof(*threads), GFP_KERNEL);
+ if (!threads)
+ return -ENOMEM;
+
for_each_engine(engine, gt, id) {
- struct active_engine threads[I915_NUM_ENGINES] = {};
unsigned long device = i915_reset_count(global);
unsigned long count = 0, reported;
bool using_guc = intel_engine_uses_guc(engine);
@@ -1016,7 +1020,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
break;
}
- memset(threads, 0, sizeof(threads));
+ memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES);
for_each_engine(other, gt, tmp) {
struct task_struct *tsk;
@@ -1236,6 +1240,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
break;
}
}
+ kfree(threads);
if (intel_gt_is_wedged(gt))
err = -EIO;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, Zhi Wang, dri-devel
When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b9eb75a2b400..0ba2a3455d99 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -428,7 +428,7 @@ struct cmd_info {
#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
- u16 rings;
+ intel_engine_mask_t rings;
/* devices that support this cmd: SNB/IVB/HSW/... */
u16 devices;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index b9eb75a2b400..0ba2a3455d99 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -428,7 +428,7 @@ struct cmd_info {
#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
- u16 rings;
+ intel_engine_mask_t rings;
/* devices that support this cmd: SNB/IVB/HSW/... */
u16 devices;
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx
Cc: José Roberto de Souza, Tvrtko Ursulin, Prathap Kumar Valsan,
dri-devel
This patch adds the basic definitions needed to support
new copy engines. Also updating the cmd_info to accommodate
new engines, as the engine id's of legacy engines have been
changed.
v2:
- Add _BCS(n) definition, similar to other engines. (Tvrtko)
- Add I915_MAX_BCS definition, similar to other engnes. (Prathap)
- Move GVT change to avoid u16 overflow to its own patch. (Tvrtko)
Original-author: CQ Tang
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 56 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 ++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++
drivers/gpu/drm/i915/i915_reg.h | 8 +++
4 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 14c6ddbbfde8..4532c3ea9ace 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -71,6 +71,62 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 6, .base = BLT_RING_BASE }
},
},
+ [BCS1] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 1,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
+ },
+ },
+ [BCS2] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 2,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
+ },
+ },
+ [BCS3] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 3,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
+ },
+ },
+ [BCS4] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 4,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
+ },
+ },
+ [BCS5] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 5,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
+ },
+ },
+ [BCS6] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 6,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
+ },
+ },
+ [BCS7] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 7,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
+ },
+ },
+ [BCS8] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 8,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
+ },
+ },
[VCS0] = {
.class = VIDEO_DECODE_CLASS,
.instance = 0,
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 298f2cc7a879..2286f96f5f87 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -35,7 +35,7 @@
#define OTHER_CLASS 4
#define COMPUTE_CLASS 5
#define MAX_ENGINE_CLASS 5
-#define MAX_ENGINE_INSTANCE 7
+#define MAX_ENGINE_INSTANCE 8
#define I915_MAX_SLICES 3
#define I915_MAX_SUBSLICES 8
@@ -99,6 +99,7 @@ struct i915_ctx_workarounds {
#define I915_MAX_SFC (I915_MAX_VCS / 2)
#define I915_MAX_CCS 4
#define I915_MAX_RCS 1
+#define I915_MAX_BCS 9
/*
* Engine IDs definitions.
@@ -107,6 +108,15 @@ struct i915_ctx_workarounds {
enum intel_engine_id {
RCS0 = 0,
BCS0,
+ BCS1,
+ BCS2,
+ BCS3,
+ BCS4,
+ BCS5,
+ BCS6,
+ BCS7,
+ BCS8,
+#define _BCS(n) (BCS0 + (n))
VCS0,
VCS1,
VCS2,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a0a49c16babd..aa2c0974b02c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1476,6 +1476,14 @@
#define GEN11_KCR (19)
#define GEN11_GTPM (16)
#define GEN11_BCS (15)
+#define XEHPC_BCS1 (14)
+#define XEHPC_BCS2 (13)
+#define XEHPC_BCS3 (12)
+#define XEHPC_BCS4 (11)
+#define XEHPC_BCS5 (10)
+#define XEHPC_BCS6 (9)
+#define XEHPC_BCS7 (8)
+#define XEHPC_BCS8 (23)
#define GEN12_CCS3 (7)
#define GEN12_CCS2 (6)
#define GEN12_CCS1 (5)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a3d7b96ef43..ab64ab4317b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -976,6 +976,14 @@
#define GEN12_COMPUTE2_RING_BASE 0x1e000
#define GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
+#define XEHPC_BCS1_RING_BASE 0x3e0000
+#define XEHPC_BCS2_RING_BASE 0x3e2000
+#define XEHPC_BCS3_RING_BASE 0x3e4000
+#define XEHPC_BCS4_RING_BASE 0x3e6000
+#define XEHPC_BCS5_RING_BASE 0x3e8000
+#define XEHPC_BCS6_RING_BASE 0x3ea000
+#define XEHPC_BCS7_RING_BASE 0x3ec000
+#define XEHPC_BCS8_RING_BASE 0x3ee000
#define DG1_GSC_HECI1_BASE 0x00258000
#define DG1_GSC_HECI2_BASE 0x00259000
#define DG2_GSC_HECI1_BASE 0x00373000
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This patch adds the basic definitions needed to support
new copy engines. Also updating the cmd_info to accommodate
new engines, as the engine id's of legacy engines have been
changed.
v2:
- Add _BCS(n) definition, similar to other engines. (Tvrtko)
- Add I915_MAX_BCS definition, similar to other engnes. (Prathap)
- Move GVT change to avoid u16 overflow to its own patch. (Tvrtko)
Original-author: CQ Tang
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 56 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 12 ++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +++
drivers/gpu/drm/i915/i915_reg.h | 8 +++
4 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 14c6ddbbfde8..4532c3ea9ace 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -71,6 +71,62 @@ static const struct engine_info intel_engines[] = {
{ .graphics_ver = 6, .base = BLT_RING_BASE }
},
},
+ [BCS1] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 1,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
+ },
+ },
+ [BCS2] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 2,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
+ },
+ },
+ [BCS3] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 3,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
+ },
+ },
+ [BCS4] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 4,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
+ },
+ },
+ [BCS5] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 5,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
+ },
+ },
+ [BCS6] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 6,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
+ },
+ },
+ [BCS7] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 7,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
+ },
+ },
+ [BCS8] = {
+ .class = COPY_ENGINE_CLASS,
+ .instance = 8,
+ .mmio_bases = {
+ { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
+ },
+ },
[VCS0] = {
.class = VIDEO_DECODE_CLASS,
.instance = 0,
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 298f2cc7a879..2286f96f5f87 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -35,7 +35,7 @@
#define OTHER_CLASS 4
#define COMPUTE_CLASS 5
#define MAX_ENGINE_CLASS 5
-#define MAX_ENGINE_INSTANCE 7
+#define MAX_ENGINE_INSTANCE 8
#define I915_MAX_SLICES 3
#define I915_MAX_SUBSLICES 8
@@ -99,6 +99,7 @@ struct i915_ctx_workarounds {
#define I915_MAX_SFC (I915_MAX_VCS / 2)
#define I915_MAX_CCS 4
#define I915_MAX_RCS 1
+#define I915_MAX_BCS 9
/*
* Engine IDs definitions.
@@ -107,6 +108,15 @@ struct i915_ctx_workarounds {
enum intel_engine_id {
RCS0 = 0,
BCS0,
+ BCS1,
+ BCS2,
+ BCS3,
+ BCS4,
+ BCS5,
+ BCS6,
+ BCS7,
+ BCS8,
+#define _BCS(n) (BCS0 + (n))
VCS0,
VCS1,
VCS2,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index a0a49c16babd..aa2c0974b02c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1476,6 +1476,14 @@
#define GEN11_KCR (19)
#define GEN11_GTPM (16)
#define GEN11_BCS (15)
+#define XEHPC_BCS1 (14)
+#define XEHPC_BCS2 (13)
+#define XEHPC_BCS3 (12)
+#define XEHPC_BCS4 (11)
+#define XEHPC_BCS5 (10)
+#define XEHPC_BCS6 (9)
+#define XEHPC_BCS7 (8)
+#define XEHPC_BCS8 (23)
#define GEN12_CCS3 (7)
#define GEN12_CCS2 (6)
#define GEN12_CCS1 (5)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4a3d7b96ef43..ab64ab4317b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -976,6 +976,14 @@
#define GEN12_COMPUTE2_RING_BASE 0x1e000
#define GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
+#define XEHPC_BCS1_RING_BASE 0x3e0000
+#define XEHPC_BCS2_RING_BASE 0x3e2000
+#define XEHPC_BCS3_RING_BASE 0x3e4000
+#define XEHPC_BCS4_RING_BASE 0x3e6000
+#define XEHPC_BCS5_RING_BASE 0x3e8000
+#define XEHPC_BCS6_RING_BASE 0x3ea000
+#define XEHPC_BCS7_RING_BASE 0x3ec000
+#define XEHPC_BCS8_RING_BASE 0x3ee000
#define DG1_GSC_HECI1_BASE 0x00258000
#define DG1_GSC_HECI2_BASE 0x00259000
#define DG2_GSC_HECI1_BASE 0x00373000
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 09/12] drm/i915/pvc: Interrupt support for new copy engines
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, dri-devel
Add the interrupt handler support for new copy engines.
Bspec: 54030
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 88b4becfcb17..3a72d4fd0214 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+ intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+ intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+ intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+ intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
@@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
+ if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+ intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+ intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+ intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+ intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index aa2c0974b02c..fe09288a3145 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1529,6 +1529,10 @@
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 09/12] drm/i915/pvc: Interrupt support for new copy engines
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add the interrupt handler support for new copy engines.
Bspec: 54030
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 88b4becfcb17..3a72d4fd0214 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+ intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+ intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+ intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
+ if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+ intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~0);
if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
@@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
+ if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+ intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+ intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+ intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+ if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+ intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index aa2c0974b02c..fe09288a3145 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1529,6 +1529,10 @@
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100)
#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c)
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 10/12] drm/i915/pvc: Reset support for new copy engines
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Stuart Summers, José Roberto de Souza, dri-devel
Add the reset support for new copy engines in PVC.
Bspec: 52549
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 44 +++++++++++++----------
2 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4532c3ea9ace..c6e93db134b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -390,6 +390,14 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
static const u32 engine_reset_domains[] = {
[RCS0] = GEN11_GRDOM_RENDER,
[BCS0] = GEN11_GRDOM_BLT,
+ [BCS1] = XEHPC_GRDOM_BLT1,
+ [BCS2] = XEHPC_GRDOM_BLT2,
+ [BCS3] = XEHPC_GRDOM_BLT3,
+ [BCS4] = XEHPC_GRDOM_BLT4,
+ [BCS5] = XEHPC_GRDOM_BLT5,
+ [BCS6] = XEHPC_GRDOM_BLT6,
+ [BCS7] = XEHPC_GRDOM_BLT7,
+ [BCS8] = XEHPC_GRDOM_BLT8,
[VCS0] = GEN11_GRDOM_MEDIA,
[VCS1] = GEN11_GRDOM_MEDIA2,
[VCS2] = GEN11_GRDOM_MEDIA3,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fe09288a3145..98ede9c93f00 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -597,24 +597,32 @@
/* GEN11 changed all bit defs except for FULL & RENDER */
#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
-#define GEN11_GRDOM_BLT (1 << 2)
-#define GEN11_GRDOM_GUC (1 << 3)
-#define GEN11_GRDOM_MEDIA (1 << 5)
-#define GEN11_GRDOM_MEDIA2 (1 << 6)
-#define GEN11_GRDOM_MEDIA3 (1 << 7)
-#define GEN11_GRDOM_MEDIA4 (1 << 8)
-#define GEN11_GRDOM_MEDIA5 (1 << 9)
-#define GEN11_GRDOM_MEDIA6 (1 << 10)
-#define GEN11_GRDOM_MEDIA7 (1 << 11)
-#define GEN11_GRDOM_MEDIA8 (1 << 12)
-#define GEN11_GRDOM_VECS (1 << 13)
-#define GEN11_GRDOM_VECS2 (1 << 14)
-#define GEN11_GRDOM_VECS3 (1 << 15)
-#define GEN11_GRDOM_VECS4 (1 << 16)
-#define GEN11_GRDOM_SFC0 (1 << 17)
-#define GEN11_GRDOM_SFC1 (1 << 18)
-#define GEN11_GRDOM_SFC2 (1 << 19)
-#define GEN11_GRDOM_SFC3 (1 << 20)
+#define XEHPC_GRDOM_BLT8 REG_BIT(31)
+#define XEHPC_GRDOM_BLT7 REG_BIT(30)
+#define XEHPC_GRDOM_BLT6 REG_BIT(29)
+#define XEHPC_GRDOM_BLT5 REG_BIT(28)
+#define XEHPC_GRDOM_BLT4 REG_BIT(27)
+#define XEHPC_GRDOM_BLT3 REG_BIT(26)
+#define XEHPC_GRDOM_BLT2 REG_BIT(25)
+#define XEHPC_GRDOM_BLT1 REG_BIT(24)
+#define GEN11_GRDOM_SFC3 REG_BIT(20)
+#define GEN11_GRDOM_SFC2 REG_BIT(19)
+#define GEN11_GRDOM_SFC1 REG_BIT(18)
+#define GEN11_GRDOM_SFC0 REG_BIT(17)
+#define GEN11_GRDOM_VECS4 REG_BIT(16)
+#define GEN11_GRDOM_VECS3 REG_BIT(15)
+#define GEN11_GRDOM_VECS2 REG_BIT(14)
+#define GEN11_GRDOM_VECS REG_BIT(13)
+#define GEN11_GRDOM_MEDIA8 REG_BIT(12)
+#define GEN11_GRDOM_MEDIA7 REG_BIT(11)
+#define GEN11_GRDOM_MEDIA6 REG_BIT(10)
+#define GEN11_GRDOM_MEDIA5 REG_BIT(9)
+#define GEN11_GRDOM_MEDIA4 REG_BIT(8)
+#define GEN11_GRDOM_MEDIA3 REG_BIT(7)
+#define GEN11_GRDOM_MEDIA2 REG_BIT(6)
+#define GEN11_GRDOM_MEDIA REG_BIT(5)
+#define GEN11_GRDOM_GUC REG_BIT(3)
+#define GEN11_GRDOM_BLT REG_BIT(2)
#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 10/12] drm/i915/pvc: Reset support for new copy engines
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add the reset support for new copy engines in PVC.
Bspec: 52549
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 44 +++++++++++++----------
2 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 4532c3ea9ace..c6e93db134b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -390,6 +390,14 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
static const u32 engine_reset_domains[] = {
[RCS0] = GEN11_GRDOM_RENDER,
[BCS0] = GEN11_GRDOM_BLT,
+ [BCS1] = XEHPC_GRDOM_BLT1,
+ [BCS2] = XEHPC_GRDOM_BLT2,
+ [BCS3] = XEHPC_GRDOM_BLT3,
+ [BCS4] = XEHPC_GRDOM_BLT4,
+ [BCS5] = XEHPC_GRDOM_BLT5,
+ [BCS6] = XEHPC_GRDOM_BLT6,
+ [BCS7] = XEHPC_GRDOM_BLT7,
+ [BCS8] = XEHPC_GRDOM_BLT8,
[VCS0] = GEN11_GRDOM_MEDIA,
[VCS1] = GEN11_GRDOM_MEDIA2,
[VCS2] = GEN11_GRDOM_MEDIA3,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fe09288a3145..98ede9c93f00 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -597,24 +597,32 @@
/* GEN11 changed all bit defs except for FULL & RENDER */
#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL
#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER
-#define GEN11_GRDOM_BLT (1 << 2)
-#define GEN11_GRDOM_GUC (1 << 3)
-#define GEN11_GRDOM_MEDIA (1 << 5)
-#define GEN11_GRDOM_MEDIA2 (1 << 6)
-#define GEN11_GRDOM_MEDIA3 (1 << 7)
-#define GEN11_GRDOM_MEDIA4 (1 << 8)
-#define GEN11_GRDOM_MEDIA5 (1 << 9)
-#define GEN11_GRDOM_MEDIA6 (1 << 10)
-#define GEN11_GRDOM_MEDIA7 (1 << 11)
-#define GEN11_GRDOM_MEDIA8 (1 << 12)
-#define GEN11_GRDOM_VECS (1 << 13)
-#define GEN11_GRDOM_VECS2 (1 << 14)
-#define GEN11_GRDOM_VECS3 (1 << 15)
-#define GEN11_GRDOM_VECS4 (1 << 16)
-#define GEN11_GRDOM_SFC0 (1 << 17)
-#define GEN11_GRDOM_SFC1 (1 << 18)
-#define GEN11_GRDOM_SFC2 (1 << 19)
-#define GEN11_GRDOM_SFC3 (1 << 20)
+#define XEHPC_GRDOM_BLT8 REG_BIT(31)
+#define XEHPC_GRDOM_BLT7 REG_BIT(30)
+#define XEHPC_GRDOM_BLT6 REG_BIT(29)
+#define XEHPC_GRDOM_BLT5 REG_BIT(28)
+#define XEHPC_GRDOM_BLT4 REG_BIT(27)
+#define XEHPC_GRDOM_BLT3 REG_BIT(26)
+#define XEHPC_GRDOM_BLT2 REG_BIT(25)
+#define XEHPC_GRDOM_BLT1 REG_BIT(24)
+#define GEN11_GRDOM_SFC3 REG_BIT(20)
+#define GEN11_GRDOM_SFC2 REG_BIT(19)
+#define GEN11_GRDOM_SFC1 REG_BIT(18)
+#define GEN11_GRDOM_SFC0 REG_BIT(17)
+#define GEN11_GRDOM_VECS4 REG_BIT(16)
+#define GEN11_GRDOM_VECS3 REG_BIT(15)
+#define GEN11_GRDOM_VECS2 REG_BIT(14)
+#define GEN11_GRDOM_VECS REG_BIT(13)
+#define GEN11_GRDOM_MEDIA8 REG_BIT(12)
+#define GEN11_GRDOM_MEDIA7 REG_BIT(11)
+#define GEN11_GRDOM_MEDIA6 REG_BIT(10)
+#define GEN11_GRDOM_MEDIA5 REG_BIT(9)
+#define GEN11_GRDOM_MEDIA4 REG_BIT(8)
+#define GEN11_GRDOM_MEDIA3 REG_BIT(7)
+#define GEN11_GRDOM_MEDIA2 REG_BIT(6)
+#define GEN11_GRDOM_MEDIA REG_BIT(5)
+#define GEN11_GRDOM_GUC REG_BIT(3)
+#define GEN11_GRDOM_BLT REG_BIT(2)
#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1))
#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx
Cc: José Roberto de Souza, Lucas De Marchi,
Prathap Kumar Valsan, dri-devel
From: Lucas De Marchi <lucas.demarchi@intel.com>
As we have more copy engines now, mask all of them from aux table
invalidate.
v2 (MattR):
- Use I915_MAX_BCS to determine mask rather than hardcoding BCS8.
(Prathap)
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 11c72792573d..0f5ab2c99ffc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -276,7 +276,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (!HAS_FLAT_CCS(rq->engine->i915) &&
(rq->engine->class == VIDEO_DECODE_CLASS ||
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
- aux_inv = rq->engine->mask & ~BIT(BCS0);
+ aux_inv = rq->engine->mask &
+ ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
if (aux_inv)
cmd += 4;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
From: Lucas De Marchi <lucas.demarchi@intel.com>
As we have more copy engines now, mask all of them from aux table
invalidate.
v2 (MattR):
- Use I915_MAX_BCS to determine mask rather than hardcoding BCS8.
(Prathap)
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 11c72792573d..0f5ab2c99ffc 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -276,7 +276,8 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (!HAS_FLAT_CCS(rq->engine->i915) &&
(rq->engine->class == VIDEO_DECODE_CLASS ||
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
- aux_inv = rq->engine->mask & ~BIT(BCS0);
+ aux_inv = rq->engine->mask &
+ ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
if (aux_inv)
cmd += 4;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 21:38 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx
Cc: Lucas De Marchi, José Roberto de Souza, dri-devel, Tvrtko Ursulin
From: Lucas De Marchi <lucas.demarchi@intel.com>
The new Link Copy engines in PVC may be fused off according to the
mslice_mask. Each bit of the MEML3_EN_MASK we read from the
GEN10_MIRROR_FUSE3 register disables a pair of link copy engines.
v2 (Tvrtko):
- Minor cosmetic changes: s/u8/unsigned long/, use instance local
variable. (Tvrtko)
Bspec: 44483
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c6e93db134b1..1adbf34c3632 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -686,6 +686,34 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
}
}
+static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_gt_info *info = >->info;
+ unsigned long meml3_mask;
+ unsigned long quad;
+
+ meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
+ meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
+
+ /*
+ * Link Copy engines may be fused off according to meml3_mask. Each
+ * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
+ */
+ for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
+ unsigned int instance = quad * 2 + 1;
+ intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
+ _BCS(instance));
+
+ if (mask & info->engine_mask) {
+ drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
+ drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
+
+ info->engine_mask &= ~mask;
+ }
+ }
+}
+
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -768,6 +796,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
engine_mask_apply_compute_fuses(gt);
+ engine_mask_apply_copy_fuses(gt);
return info->engine_mask;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines
@ 2022-05-05 21:38 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-05 21:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
From: Lucas De Marchi <lucas.demarchi@intel.com>
The new Link Copy engines in PVC may be fused off according to the
mslice_mask. Each bit of the MEML3_EN_MASK we read from the
GEN10_MIRROR_FUSE3 register disables a pair of link copy engines.
v2 (Tvrtko):
- Minor cosmetic changes: s/u8/unsigned long/, use instance local
variable. (Tvrtko)
Bspec: 44483
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index c6e93db134b1..1adbf34c3632 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -686,6 +686,34 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
}
}
+static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_gt_info *info = >->info;
+ unsigned long meml3_mask;
+ unsigned long quad;
+
+ meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
+ meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
+
+ /*
+ * Link Copy engines may be fused off according to meml3_mask. Each
+ * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
+ */
+ for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
+ unsigned int instance = quad * 2 + 1;
+ intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
+ _BCS(instance));
+
+ if (mask & info->engine_mask) {
+ drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
+ drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
+
+ info->engine_mask &= ~mask;
+ }
+ }
+}
+
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -768,6 +796,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
engine_mask_apply_compute_fuses(gt);
+ engine_mask_apply_copy_fuses(gt);
return info->engine_mask;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev2)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (12 preceding siblings ...)
(?)
@ 2022-05-05 22:32 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-05 22:32 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev2)
URL : https://patchwork.freedesktop.org/series/103443/
State : warning
== Summary ==
Error: dim checkpatch failed
3ff8d05befaf drm/i915/uncore: Reorganize and document shadow and forcewake tables
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/intel_uncore.c:1106:
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ if (NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
+ __fwd; \
+})
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/intel_uncore.c:1114:
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
-:147: CHECK:LINE_SPACING: Please don't use multiple blank lines
#147: FILE: drivers/gpu/drm/i915/intel_uncore.c:1170:
+
+
total: 0 errors, 0 warnings, 3 checks, 172 lines checked
519b8cb4c285 drm/i915/pvc: Add forcewake support
-:80: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#80: FILE: drivers/gpu/drm/i915/intel_uncore.c:1576:
+ GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
+ 0x4000 - 0x4aff: gt
-:86: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#86: FILE: drivers/gpu/drm/i915/intel_uncore.c:1582:
+ 0x8000 - 0x813f: gt */
-:90: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#90: FILE: drivers/gpu/drm/i915/intel_uncore.c:1586:
+ GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
+ 0x8200 - 0x82ff: gt
-:97: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#97: FILE: drivers/gpu/drm/i915/intel_uncore.c:1593:
+ 0x9480 - 0x94cf: reserved */
-:100: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#100: FILE: drivers/gpu/drm/i915/intel_uncore.c:1596:
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
-:101: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#101: FILE: drivers/gpu/drm/i915/intel_uncore.c:1597:
+ 0x9600 - 0x967f: reserved */
-:103: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#103: FILE: drivers/gpu/drm/i915/intel_uncore.c:1599:
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
-:104: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#104: FILE: drivers/gpu/drm/i915/intel_uncore.c:1600:
+ 0x9700 - 0x97ff: reserved */
-:106: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#106: FILE: drivers/gpu/drm/i915/intel_uncore.c:1602:
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
-:108: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#108: FILE: drivers/gpu/drm/i915/intel_uncore.c:1604:
+ 0xc000 - 0xcfff: gt */
-:113: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#113: FILE: drivers/gpu/drm/i915/intel_uncore.c:1609:
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
-:114: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#114: FILE: drivers/gpu/drm/i915/intel_uncore.c:1610:
+ 0xde00 - 0xde7f: reserved */
-:116: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#116: FILE: drivers/gpu/drm/i915/intel_uncore.c:1612:
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdeff: render
-:119: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#119: FILE: drivers/gpu/drm/i915/intel_uncore.c:1615:
+ 0xe800 - 0xe8ff: reserved */
-:121: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#121: FILE: drivers/gpu/drm/i915/intel_uncore.c:1617:
+ GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
-:124: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#124: FILE: drivers/gpu/drm/i915/intel_uncore.c:1620:
+ 0x10000 - 0x11fff: reserved */
-:126: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#126: FILE: drivers/gpu/drm/i915/intel_uncore.c:1622:
+ GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
+ 0x12000 - 0x127ff: always on
-:127: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#127: FILE: drivers/gpu/drm/i915/intel_uncore.c:1623:
+ 0x12800 - 0x12fff: reserved */
-:129: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#129: FILE: drivers/gpu/drm/i915/intel_uncore.c:1625:
+ GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
+ 0x13000 - 0x135ff: gt
-:135: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#135: FILE: drivers/gpu/drm/i915/intel_uncore.c:1631:
+ 0x22000 - 0x23fff: gt */
-:137: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#137: FILE: drivers/gpu/drm/i915/intel_uncore.c:1633:
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 24000 - 0x2407f: always on
-:138: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#138: FILE: drivers/gpu/drm/i915/intel_uncore.c:1634:
+ 24080 - 0x2417f: reserved */
-:140: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#140: FILE: drivers/gpu/drm/i915/intel_uncore.c:1636:
+ GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
-:146: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#146: FILE: drivers/gpu/drm/i915/intel_uncore.c:1642:
+ 0x30000 - 0x3ffff: gt */
-:149: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#149: FILE: drivers/gpu/drm/i915/intel_uncore.c:1645:
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
-:153: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#153: FILE: drivers/gpu/drm/i915/intel_uncore.c:1649:
+ 0x1c3f00 - 0x1c3fff: VD0 */
-:155: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#155: FILE: drivers/gpu/drm/i915/intel_uncore.c:1651:
+ GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6aff: VD1
-:158: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#158: FILE: drivers/gpu/drm/i915/intel_uncore.c:1654:
+ 0x1c8000 - 0x1cffff: reserved */
-:160: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#160: FILE: drivers/gpu/drm/i915/intel_uncore.c:1656:
+ GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2aff: VD2
-:163: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#163: FILE: drivers/gpu/drm/i915/intel_uncore.c:1659:
+ 0x1d4000 - 0x23ffff: reserved */
total: 0 errors, 30 warnings, 0 checks, 174 lines checked
61557cc984d0 drm/i915/pvc: Define MOCS table for PVC
0532ac252bc5 drm/i915/pvc: Read correct RP_STATE_CAP register
6dee00e8d754 drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
-:69: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#69: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:292:
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
PIPE_CONTROL_TILE_CACHE_FLUSH | \
total: 1 errors, 0 warnings, 0 checks, 86 lines checked
5f7383b1f126 drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
9e83c2525e20 drm/i915/gvt: Use intel_engine_mask_t for ring mask
5a91f56350be drm/i915/pvc: Engine definitions for new copy engines
29090aee5850 drm/i915/pvc: Interrupt support for new copy engines
9183527af3de drm/i915/pvc: Reset support for new copy engines
9d968f976dd3 drm/i915/pvc: skip all copy engines from aux table invalidate
c38332de24fb drm/i915/pvc: read fuses for link copy engines
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Introduce Ponte Vecchio (rev2)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (13 preceding siblings ...)
(?)
@ 2022-05-05 22:32 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-05 22:32 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev2)
URL : https://patchwork.freedesktop.org/series/103443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Introduce Ponte Vecchio (rev2)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (14 preceding siblings ...)
(?)
@ 2022-05-05 22:58 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-05 22:58 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5767 bytes --]
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev2)
URL : https://patchwork.freedesktop.org/series/103443/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11612 -> Patchwork_103443v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103443v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103443v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): bat-adlm-1
Missing (2): fi-rkl-11600 fi-bsw-cyan
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103443v2:
### IGT changes ###
#### Possible regressions ####
* igt@gem_sync@basic-each:
- fi-hsw-g3258: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/fi-hsw-g3258/igt@gem_sync@basic-each.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/fi-hsw-g3258/igt@gem_sync@basic-each.html
#### Warnings ####
* igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-soraka: [SKIP][3] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/fi-kbl-soraka/igt@kms_chamelium@dp-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/fi-kbl-soraka/igt@kms_chamelium@dp-hpd-fast.html
Known issues
------------
Here are the changes found in Patchwork_103443v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [DMESG-FAIL][7] ([i915#3987]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][9] ([i915#3921] / [i915#5153]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: [DMESG-WARN][11] ([i915#3576]) -> [PASS][12] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11612/bat-adlp-4/igt@kms_busy@basic@modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/bat-adlp-4/igt@kms_busy@basic@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
Build changes
-------------
* Linux: CI_DRM_11612 -> Patchwork_103443v2
CI-20190529: 20190529
CI_DRM_11612: 9f6ebefdd3fadb37d1e284e7f0bf0cfcd2fef75b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103443v2: 9f6ebefdd3fadb37d1e284e7f0bf0cfcd2fef75b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f41752acf146 drm/i915/pvc: read fuses for link copy engines
130d53a5578d drm/i915/pvc: skip all copy engines from aux table invalidate
d608ac99fab2 drm/i915/pvc: Reset support for new copy engines
2b1639d2aa3e drm/i915/pvc: Interrupt support for new copy engines
d4064df82c11 drm/i915/pvc: Engine definitions for new copy engines
0d90a6d4e6a2 drm/i915/gvt: Use intel_engine_mask_t for ring mask
69140f89ec0d drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
9782f9902d63 drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
332fe30ef673 drm/i915/pvc: Read correct RP_STATE_CAP register
b8a70a3201f1 drm/i915/pvc: Define MOCS table for PVC
a15e27c9fa27 drm/i915/pvc: Add forcewake support
24bbf8bbee2c drm/i915/uncore: Reorganize and document shadow and forcewake tables
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v2/index.html
[-- Attachment #2: Type: text/html, Size: 6046 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev3)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (15 preceding siblings ...)
(?)
@ 2022-05-06 0:35 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-06 0:35 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev3)
URL : https://patchwork.freedesktop.org/series/103443/
State : warning
== Summary ==
Error: dim checkpatch failed
d831d43de27e drm/i915/uncore: Reorganize and document shadow and forcewake tables
-:82: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'offset' - possible side-effects?
#82: FILE: drivers/gpu/drm/i915/intel_uncore.c:1106:
+#define __fwtable_reg_read_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ if (NEEDS_FORCE_WAKE((offset))) \
+ __fwd = find_fw_domain(uncore, offset); \
+ __fwd; \
+})
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'uncore' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/intel_uncore.c:1114:
+#define __fwtable_reg_write_fw_domains(uncore, offset) \
+({ \
+ enum forcewake_domains __fwd = 0; \
+ const u32 __offset = (offset); \
+ if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \
+ __fwd = find_fw_domain(uncore, __offset); \
+ __fwd; \
+})
-:147: CHECK:LINE_SPACING: Please don't use multiple blank lines
#147: FILE: drivers/gpu/drm/i915/intel_uncore.c:1170:
+
+
total: 0 errors, 0 warnings, 3 checks, 172 lines checked
50c88acae6ba drm/i915/pvc: Add forcewake support
-:80: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#80: FILE: drivers/gpu/drm/i915/intel_uncore.c:1576:
+ GEN_FW_RANGE(0x4000, 0x813f, FORCEWAKE_GT), /*
+ 0x4000 - 0x4aff: gt
-:86: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#86: FILE: drivers/gpu/drm/i915/intel_uncore.c:1582:
+ 0x8000 - 0x813f: gt */
-:90: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#90: FILE: drivers/gpu/drm/i915/intel_uncore.c:1586:
+ GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /*
+ 0x8200 - 0x82ff: gt
-:97: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#97: FILE: drivers/gpu/drm/i915/intel_uncore.c:1593:
+ 0x9480 - 0x94cf: reserved */
-:100: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#100: FILE: drivers/gpu/drm/i915/intel_uncore.c:1596:
+ GEN_FW_RANGE(0x9560, 0x967f, 0), /*
+ 0x9560 - 0x95ff: always on
-:101: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#101: FILE: drivers/gpu/drm/i915/intel_uncore.c:1597:
+ 0x9600 - 0x967f: reserved */
-:103: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#103: FILE: drivers/gpu/drm/i915/intel_uncore.c:1599:
+ GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /*
+ 0x9680 - 0x96ff: render
-:104: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#104: FILE: drivers/gpu/drm/i915/intel_uncore.c:1600:
+ 0x9700 - 0x97ff: reserved */
-:106: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#106: FILE: drivers/gpu/drm/i915/intel_uncore.c:1602:
+ GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /*
+ 0x9800 - 0xb4ff: gt
-:108: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#108: FILE: drivers/gpu/drm/i915/intel_uncore.c:1604:
+ 0xc000 - 0xcfff: gt */
-:113: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#113: FILE: drivers/gpu/drm/i915/intel_uncore.c:1609:
+ GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /*
+ 0xdd00 - 0xddff: gt
-:114: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#114: FILE: drivers/gpu/drm/i915/intel_uncore.c:1610:
+ 0xde00 - 0xde7f: reserved */
-:116: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#116: FILE: drivers/gpu/drm/i915/intel_uncore.c:1612:
+ GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /*
+ 0xde80 - 0xdeff: render
-:119: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#119: FILE: drivers/gpu/drm/i915/intel_uncore.c:1615:
+ 0xe800 - 0xe8ff: reserved */
-:121: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#121: FILE: drivers/gpu/drm/i915/intel_uncore.c:1617:
+ GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), /*
+ 0xe900 - 0xe9ff: gt
-:124: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#124: FILE: drivers/gpu/drm/i915/intel_uncore.c:1620:
+ 0x10000 - 0x11fff: reserved */
-:126: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#126: FILE: drivers/gpu/drm/i915/intel_uncore.c:1622:
+ GEN_FW_RANGE(0x12000, 0x12fff, 0), /*
+ 0x12000 - 0x127ff: always on
-:127: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#127: FILE: drivers/gpu/drm/i915/intel_uncore.c:1623:
+ 0x12800 - 0x12fff: reserved */
-:129: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#129: FILE: drivers/gpu/drm/i915/intel_uncore.c:1625:
+ GEN_FW_RANGE(0x13000, 0x23fff, FORCEWAKE_GT), /*
+ 0x13000 - 0x135ff: gt
-:135: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#135: FILE: drivers/gpu/drm/i915/intel_uncore.c:1631:
+ 0x22000 - 0x23fff: gt */
-:137: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#137: FILE: drivers/gpu/drm/i915/intel_uncore.c:1633:
+ GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
+ 24000 - 0x2407f: always on
-:138: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#138: FILE: drivers/gpu/drm/i915/intel_uncore.c:1634:
+ 24080 - 0x2417f: reserved */
-:140: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#140: FILE: drivers/gpu/drm/i915/intel_uncore.c:1636:
+ GEN_FW_RANGE(0x24180, 0x3ffff, FORCEWAKE_GT), /*
+ 0x24180 - 0x241ff: gt
-:146: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#146: FILE: drivers/gpu/drm/i915/intel_uncore.c:1642:
+ 0x30000 - 0x3ffff: gt */
-:149: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#149: FILE: drivers/gpu/drm/i915/intel_uncore.c:1645:
+ GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /*
+ 0x1c0000 - 0x1c2bff: VD0
-:153: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#153: FILE: drivers/gpu/drm/i915/intel_uncore.c:1649:
+ 0x1c3f00 - 0x1c3fff: VD0 */
-:155: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#155: FILE: drivers/gpu/drm/i915/intel_uncore.c:1651:
+ GEN_FW_RANGE(0x1c4000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX1), /*
+ 0x1c4000 - 0x1c6aff: VD1
-:158: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#158: FILE: drivers/gpu/drm/i915/intel_uncore.c:1654:
+ 0x1c8000 - 0x1cffff: reserved */
-:160: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#160: FILE: drivers/gpu/drm/i915/intel_uncore.c:1656:
+ GEN_FW_RANGE(0x1d0000, 0x23ffff, FORCEWAKE_MEDIA_VDBOX2), /*
+ 0x1d0000 - 0x1d2aff: VD2
-:163: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#163: FILE: drivers/gpu/drm/i915/intel_uncore.c:1659:
+ 0x1d4000 - 0x23ffff: reserved */
total: 0 errors, 30 warnings, 0 checks, 174 lines checked
40c3eaf4f764 drm/i915/pvc: Define MOCS table for PVC
ade610619555 drm/i915/pvc: Read correct RP_STATE_CAP register
188a768080c9 drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
-:69: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#69: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:292:
+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
PIPE_CONTROL_TILE_CACHE_FLUSH | \
total: 1 errors, 0 warnings, 0 checks, 86 lines checked
7e31d86b188b drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
c500a6bf46a8 drm/i915/gvt: Use intel_engine_mask_t for ring mask
ec0b13cb48ee drm/i915/pvc: Engine definitions for new copy engines
6c3af6101f6e drm/i915/pvc: Interrupt support for new copy engines
556728d14e82 drm/i915/pvc: Reset support for new copy engines
6a175c5f9c71 drm/i915/pvc: skip all copy engines from aux table invalidate
9685f669e4b4 drm/i915/pvc: read fuses for link copy engines
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Introduce Ponte Vecchio (rev3)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (16 preceding siblings ...)
(?)
@ 2022-05-06 0:35 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-06 0:35 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev3)
URL : https://patchwork.freedesktop.org/series/103443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Introduce Ponte Vecchio (rev3)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (17 preceding siblings ...)
(?)
@ 2022-05-06 1:00 ` Patchwork
-1 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2022-05-06 1:00 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6772 bytes --]
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev3)
URL : https://patchwork.freedesktop.org/series/103443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11613 -> Patchwork_103443v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/index.html
Participating hosts (41 -> 39)
------------------------------
Additional (1): bat-adlm-1
Missing (3): bat-rpls-1 bat-jsl-2 fi-icl-u2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103443v3:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/bat-adlm-1/igt@i915_selftest@live@requests.html
New tests
---------
New tests have been introduced between CI_DRM_11613 and Patchwork_103443v3:
### New IGT tests (1) ###
* igt@i915_selftest@live@c-hdmi-a2:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_103443v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][2] -> [INCOMPLETE][3] ([i915#3921])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- fi-bdw-5557u: [PASS][4] -> [INCOMPLETE][5] ([i915#5704])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/fi-bdw-5557u/igt@i915_selftest@live@mman.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-bdw-5557u/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@vma:
- fi-bdw-5557u: [PASS][6] -> [INCOMPLETE][7] ([i915#5681])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/fi-bdw-5557u/igt@i915_selftest@live@vma.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-bdw-5557u/igt@i915_selftest@live@vma.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-n3050: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-bsw-n3050/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [PASS][9] -> [DMESG-WARN][10] ([i915#3576]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bsw-n3050: NOTRUN -> [SKIP][11] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-bsw-n3050/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][12] ([i915#5801] / [i915#5847]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5681]: https://gitlab.freedesktop.org/drm/intel/issues/5681
[i915#5704]: https://gitlab.freedesktop.org/drm/intel/issues/5704
[i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
Build changes
-------------
* Linux: CI_DRM_11613 -> Patchwork_103443v3
CI-20190529: 20190529
CI_DRM_11613: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103443v3: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
fb1c4ae10793 drm/i915/pvc: read fuses for link copy engines
70ed2954563f drm/i915/pvc: skip all copy engines from aux table invalidate
18349345c49b drm/i915/pvc: Reset support for new copy engines
80e83bfb8eaa drm/i915/pvc: Interrupt support for new copy engines
f3ea8fb09b36 drm/i915/pvc: Engine definitions for new copy engines
a069c02af8b2 drm/i915/gvt: Use intel_engine_mask_t for ring mask
73d44e19d0fa drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine
2b354113b47d drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
a87d44bf8ce7 drm/i915/pvc: Read correct RP_STATE_CAP register
28ba9245f7bd drm/i915/pvc: Define MOCS table for PVC
f552f6c6fed8 drm/i915/pvc: Add forcewake support
aa69b8416413 drm/i915/uncore: Reorganize and document shadow and forcewake tables
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/index.html
[-- Attachment #2: Type: text/html, Size: 7160 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio (rev3)
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
` (18 preceding siblings ...)
(?)
@ 2022-05-06 4:29 ` Patchwork
2022-05-10 22:43 ` Matt Roper
-1 siblings, 1 reply; 42+ messages in thread
From: Patchwork @ 2022-05-06 4:29 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 46762 bytes --]
== Series Details ==
Series: i915: Introduce Ponte Vecchio (rev3)
URL : https://patchwork.freedesktop.org/series/103443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11613_full -> Patchwork_103443v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 12)
------------------------------
Additional (2): shard-rkl shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103443v3_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_scaling@downscale-with-modifier-factor-0-25}:
- {shard-rkl}: NOTRUN -> [SKIP][1] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-rkl-2/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25.html
Known issues
------------
Here are the changes found in Patchwork_103443v3_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-apl: ([PASS][2], [FAIL][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#4386]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: NOTRUN -> [TIMEOUT][52] ([i915#3070])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][53] -> [FAIL][54] ([i915#2846])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][55] ([i915#2842])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: NOTRUN -> [FAIL][58] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][61] -> [FAIL][62] ([i915#2849])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-snb: [PASS][63] -> [SKIP][64] ([fdo#109271]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-snb5/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][65] -> [SKIP][66] ([i915#2190])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb5/igt@gem_huc_copy@huc-copy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#4613])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@gem_lmem_swapping@random.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#768])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_softpin@evict-single-offset:
- shard-kbl: NOTRUN -> [FAIL][72] ([i915#4171])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_softpin@evict-single-offset.html
* igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109312])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_softpin@evict-snoop.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [PASS][74] -> [DMESG-WARN][75] ([i915#180]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gen3_render_linear_blits:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109289])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][77] -> [DMESG-WARN][78] ([i915#5566] / [i915#716])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2856]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#1937])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: NOTRUN -> [WARN][81] ([i915#2684])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#5286])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][83] ([fdo#110725] / [fdo#111614])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][84] ([i915#3763])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109278] / [i915#3886]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3886]) +6 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +6 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [fdo#111827]) +5 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +6 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109284] / [fdo#111827]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][93] ([i915#2105])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109278] / [fdo#109279]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278]) +8 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +101 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109274] / [fdo#109278])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#533]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
- shard-skl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled:
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#5287])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][101] -> [FAIL][102] ([i915#4767])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274]) +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][104] -> [FAIL][105] ([i915#2122])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271]) +40 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109280]) +8 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#1839])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][109] -> [DMESG-WARN][110] ([i915#180]) +4 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-kbl: [PASS][111] -> [INCOMPLETE][112] ([i915#3614])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][114] -> [FAIL][115] ([fdo#108145] / [i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-d-tiling-yf:
- shard-skl: NOTRUN -> [SKIP][116] ([fdo#109271]) +89 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_plane_lowres@pipe-d-tiling-yf.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][117] -> [SKIP][118] ([i915#5235]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: NOTRUN -> [SKIP][120] ([i915#658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#658])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][122] -> [SKIP][123] ([fdo#109642] / [fdo#111068] / [i915#658])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][124] -> [SKIP][125] ([fdo#109441]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr@psr2_dpms.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr@psr2_dpms.html
* igt@kms_vrr@flipline:
- shard-iclb: NOTRUN -> [SKIP][126] ([i915#3555])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_vrr@flipline.html
* igt@nouveau_crc@pipe-d-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][127] ([fdo#109278] / [i915#2530])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@nouveau_crc@pipe-d-source-outp-complete.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][128] -> [FAIL][129] ([i915#1722])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl6/igt@perf@polling-small-buf.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl1/igt@perf@polling-small-buf.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#2994]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][131] ([i915#658]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb3/igt@feature_discovery@psr2.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [FAIL][133] ([i915#2842]) -> [PASS][134] +3 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_flush@basic-wb-set-default:
- shard-snb: [SKIP][135] ([fdo#109271]) -> [PASS][136] +3 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-snb6/igt@gem_exec_flush@basic-wb-set-default.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-snb4/igt@gem_exec_flush@basic-wb-set-default.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-glk: [DMESG-WARN][137] ([i915#118]) -> [PASS][138] +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][139] ([i915#180]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [FAIL][141] ([i915#2346]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [INCOMPLETE][143] ([i915#4939]) -> [PASS][144] +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][145] ([i915#180]) -> [PASS][146] +2 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [FAIL][147] ([i915#2122]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-tglb: [DMESG-WARN][149] ([i915#2411]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb5/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][151] ([fdo#109441]) -> [PASS][152] +2 similar issues
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][153] ([i915#4525]) -> [DMESG-WARN][154] ([i915#5614])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][155] ([i915#5614]) -> [SKIP][156] ([i915#4525])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_plane_cursor@pipe-d-overlay-size-256:
- shard-skl: [SKIP][157] ([fdo#109271]) -> [SKIP][158] ([fdo#109271] / [i915#1888])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_plane_cursor@pipe-d-overlay-size-256.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_plane_cursor@pipe-d-overlay-size-256.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-y:
- shard-skl: [SKIP][159] ([fdo#109271] / [i915#1888]) -> [SKIP][160] ([fdo#109271])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_plane_multiple@atomic-pipe-d-tiling-y.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_plane_multiple@atomic-pipe-d-tiling-y.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][161] ([i915#2920]) -> [SKIP][162] ([fdo#111068] / [i915#658])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][163] ([fdo#111068] / [i915#658]) -> [SKIP][164] ([i915#2920])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/igt@runner@aborted.html
- shard-kbl: ([FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl4/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl3/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl6/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl3/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl6/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl7/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl7/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
Build changes
-------------
* Linux: CI_DRM_11613 -> Patchwork_103443v3
CI-20190529: 20190529
CI_DRM_11613: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103443v3: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/index.html
[-- Attachment #2: Type: text/html, Size: 47783 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
(?)
@ 2022-05-06 17:08 ` Lucas De Marchi
-1 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2022-05-06 17:08 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Thu, May 05, 2022 at 02:38:03PM -0700, Matt Roper wrote:
>From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>
>v2 (MattR):
> - Clarify comment above RING_CMD_CCTL programming.
> - Remove bspec reference from field definition. (Lucas)
> - Add WARN if we try to use a (presumably uninitialized) wb_index of 0.
> On most platforms 0 is an invalid MOCS entry and even on the ones
> where it isn't, it isn't the right setting for wb_index. (Lucas)
>
>Bspec: 45101, 72161
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>Signed-off-by: Fei Yang <fei.yang@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
> drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 30 ++++++++++++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 6 files changed, 53 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>index b06611c1d4ad..7853ea194ea6 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>@@ -221,6 +221,7 @@ struct intel_gt {
>
> struct {
> u8 uc_index;
>+ u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
doesn't correspond to changelog
other than that, Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> } mocs;
>
> struct intel_pxp pxp;
>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>index c4c37585ae8c..c6ebe2781076 100644
>--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>@@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
> unsigned int n_entries;
> const struct drm_i915_mocs_entry *table;
> u8 uc_index;
>+ u8 wb_index; /* Only used on HAS_L3_CCS_READ() platforms */
> u8 unused_entries_index;
> };
>
>@@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
>
> /* Helper defines */
> #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>+#define PVC_NUM_MOCS_ENTRIES 3
>
> /* (e)LLC caching options */
> /*
>@@ -394,6 +396,17 @@ static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = {
> MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
> };
>
>+static const struct drm_i915_mocs_entry pvc_mocs_table[] = {
>+ /* Error */
>+ MOCS_ENTRY(0, 0, L3_3_WB),
>+
>+ /* UC */
>+ MOCS_ENTRY(1, 0, L3_1_UC),
>+
>+ /* WB */
>+ MOCS_ENTRY(2, 0, L3_3_WB),
>+};
>+
> enum {
> HAS_GLOBAL_MOCS = BIT(0),
> HAS_ENGINE_MOCS = BIT(1),
>@@ -423,7 +436,14 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> memset(table, 0, sizeof(struct drm_i915_mocs_table));
>
> table->unused_entries_index = I915_MOCS_PTE;
>- if (IS_DG2(i915)) {
>+ if (IS_PONTEVECCHIO(i915)) {
>+ table->size = ARRAY_SIZE(pvc_mocs_table);
>+ table->table = pvc_mocs_table;
>+ table->n_entries = PVC_NUM_MOCS_ENTRIES;
>+ table->uc_index = 1;
>+ table->wb_index = 2;
>+ table->unused_entries_index = 2;
>+ } else if (IS_DG2(i915)) {
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
> table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax);
> table->table = dg2_mocs_table_g10_ax;
>@@ -622,6 +642,8 @@ void intel_set_mocs_index(struct intel_gt *gt)
>
> get_mocs_settings(gt->i915, &table);
> gt->mocs.uc_index = table.uc_index;
>+ if (HAS_L3_CCS_READ(gt->i915))
>+ gt->mocs.wb_index = table.wb_index;
> }
>
> void intel_mocs_init(struct intel_gt *gt)
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index a05c4b99b3fb..756807c4b405 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -1994,19 +1994,37 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> static void
> engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
>- u8 mocs;
>+ u8 mocs_w, mocs_r;
>
> /*
>- * RING_CMD_CCTL are need to be programed to un-cached
>- * for memory writes and reads outputted by Command
>- * Streamers on Gen12 onward platforms.
>+ * RING_CMD_CCTL specifies the default MOCS entry that will be used
>+ * by the command streamer when executing commands that don't have
>+ * a way to explicitly specify a MOCS setting. The default should
>+ * usually reference whichever MOCS entry corresponds to uncached
>+ * behavior, although use of a WB cached entry is recommended by the
>+ * spec in certain circumstances on specific platforms.
> */
> if (GRAPHICS_VER(engine->i915) >= 12) {
>- mocs = engine->gt->mocs.uc_index;
>+ mocs_r = engine->gt->mocs.uc_index;
>+ mocs_w = engine->gt->mocs.uc_index;
>+
>+ if (HAS_L3_CCS_READ(engine->i915) &&
>+ engine->class == COMPUTE_CLASS) {
>+ mocs_r = engine->gt->mocs.wb_index;
>+
>+ /*
>+ * Even on the few platforms where MOCS 0 is a
>+ * legitimate table entry, it's never the correct
>+ * setting to use here; we can assume the MOCS init
>+ * just forgot to initialize wb_index.
>+ */
>+ drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
>+ }
>+
> wa_masked_field_set(wal,
> RING_CMD_CCTL(engine->mmio_base),
> CMD_CCTL_MOCS_MASK,
>- CMD_CCTL_MOCS_OVERRIDE(mocs, mocs));
>+ CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
> }
> }
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 00d7eeae33bd..b389674b5210 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1370,6 +1370,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
>+#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>+
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 498708b33924..07722cdf63ac 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -1076,7 +1076,8 @@ static const struct intel_device_info ats_m_info = {
>
> #define XE_HPC_FEATURES \
> XE_HP_FEATURES, \
>- .dma_mask_size = 52
>+ .dma_mask_size = 52, \
>+ .has_l3_ccs_read = 1
>
> __maybe_unused
> static const struct intel_device_info pvc_info = {
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index e7d2cf7d65c8..09e33296157a 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -150,6 +150,7 @@ enum intel_ppgtt_type {
> func(has_heci_pxp); \
> func(has_heci_gscfi); \
> func(has_guc_deprivilege); \
>+ func(has_l3_ccs_read); \
> func(has_l3_dpf); \
> func(has_llc); \
> func(has_logical_ring_contexts); \
>--
>2.35.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
@ 2022-05-06 17:23 ` Lucas De Marchi
-1 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2022-05-06 17:23 UTC (permalink / raw)
To: Matt Roper; +Cc: Stuart Summers, intel-gfx, dri-devel
On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
>From: Stuart Summers <stuart.summers@intel.com>
>
>Although we already strip 3D-specific flags from PIPE_CONTROL
>instructions when submitting to a compute engine, there are some
>additional flags that need to be removed when the platform as a whole
>lacks a 3D pipeline. Add those restrictions here.
>
>Bspec: 47112
>Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> 5 files changed, 28 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>index 3e13960615bd..11c72792573d 100644
>--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>@@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> flags |= PIPE_CONTROL_CS_STALL;
>
>- if (engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> cs = intel_ring_begin(rq, 6);
> if (IS_ERR(cs))
>@@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> flags |= PIPE_CONTROL_CS_STALL;
>
>- if (engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> if (!HAS_FLAT_CCS(rq->engine->i915))
> count = 8 + 4;
>@@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
>- if (rq->engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(rq->engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (rq->engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> cs = gen12_emit_ggtt_write_rcs(cs,
> rq->fence.seqno,
>diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>index 556bca3be804..900755f4b787 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>@@ -288,8 +288,8 @@
> #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>
>-/* 3D-related flags can't be set on compute engine */
>-#define PIPE_CONTROL_3D_FLAGS (\
>+/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
>+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> PIPE_CONTROL_TILE_CACHE_FLUSH | \
>@@ -300,6 +300,14 @@
> PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
>
>+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
>+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
names and comments here I think are confusing. In the code we do:
if (LACKS_3D_PIPELINE(engine->i915))
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
coments give the _engines_ that lack a 3D pipeline doens't seem accurate
as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
And LACKS_3D_PIPELINE... may be better to invert the condition to follow
the other macros: HAS_3D_PIPELINE.
>+ PIPE_CONTROL_3D_ENGINE_FLAGS | \
>+ PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
>+ PIPE_CONTROL_FLUSH_ENABLE | \
>+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
>+ PIPE_CONTROL_DC_FLUSH_ENABLE)
>+
> #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> /* Opcodes for MI_MATH_INSTR */
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index b389674b5210..1e153cefc92e 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
>
>+#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
>+
> /* i915_gem.c */
> void i915_gem_init_early(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 07722cdf63ac..14e0e8225324 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> #define XE_HPC_FEATURES \
> XE_HP_FEATURES, \
> .dma_mask_size = 52, \
>- .has_l3_ccs_read = 1
>+ .has_l3_ccs_read = 1, \
>+ .lacks_3d_pipeline = 1
isn't the absence of RCS sufficient so this could be done only in the
macro rather than adding a flag here?
Lucas De Marchi
>
> __maybe_unused
> static const struct intel_device_info pvc_info = {
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 09e33296157a..972084676984 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> func(has_snoop); \
> func(has_coherent_ggtt); \
> func(unfenced_needs_alignment); \
>- func(hws_needs_physical);
>+ func(hws_needs_physical); \
>+ func(lacks_3d_pipeline);
>
> #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> /* Keep in alphabetical order */ \
>--
>2.35.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
@ 2022-05-06 17:23 ` Lucas De Marchi
0 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2022-05-06 17:23 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
>From: Stuart Summers <stuart.summers@intel.com>
>
>Although we already strip 3D-specific flags from PIPE_CONTROL
>instructions when submitting to a compute engine, there are some
>additional flags that need to be removed when the platform as a whole
>lacks a 3D pipeline. Add those restrictions here.
>
>Bspec: 47112
>Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> 5 files changed, 28 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>index 3e13960615bd..11c72792573d 100644
>--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>@@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> flags |= PIPE_CONTROL_CS_STALL;
>
>- if (engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> cs = intel_ring_begin(rq, 6);
> if (IS_ERR(cs))
>@@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> flags |= PIPE_CONTROL_CS_STALL;
>
>- if (engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> if (!HAS_FLAT_CCS(rq->engine->i915))
> count = 8 + 4;
>@@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
>- if (rq->engine->class == COMPUTE_CLASS)
>- flags &= ~PIPE_CONTROL_3D_FLAGS;
>+ if (LACKS_3D_PIPELINE(rq->engine->i915))
>+ flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>+ else if (rq->engine->class == COMPUTE_CLASS)
>+ flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> cs = gen12_emit_ggtt_write_rcs(cs,
> rq->fence.seqno,
>diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>index 556bca3be804..900755f4b787 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>@@ -288,8 +288,8 @@
> #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
>
>-/* 3D-related flags can't be set on compute engine */
>-#define PIPE_CONTROL_3D_FLAGS (\
>+/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
>+#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> PIPE_CONTROL_TILE_CACHE_FLUSH | \
>@@ -300,6 +300,14 @@
> PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
>
>+/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
>+#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
names and comments here I think are confusing. In the code we do:
if (LACKS_3D_PIPELINE(engine->i915))
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
coments give the _engines_ that lack a 3D pipeline doens't seem accurate
as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
And LACKS_3D_PIPELINE... may be better to invert the condition to follow
the other macros: HAS_3D_PIPELINE.
>+ PIPE_CONTROL_3D_ENGINE_FLAGS | \
>+ PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
>+ PIPE_CONTROL_FLUSH_ENABLE | \
>+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
>+ PIPE_CONTROL_DC_FLUSH_ENABLE)
>+
> #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> /* Opcodes for MI_MATH_INSTR */
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index b389674b5210..1e153cefc92e 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
>
>+#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
>+
> /* i915_gem.c */
> void i915_gem_init_early(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
>diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>index 07722cdf63ac..14e0e8225324 100644
>--- a/drivers/gpu/drm/i915/i915_pci.c
>+++ b/drivers/gpu/drm/i915/i915_pci.c
>@@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> #define XE_HPC_FEATURES \
> XE_HP_FEATURES, \
> .dma_mask_size = 52, \
>- .has_l3_ccs_read = 1
>+ .has_l3_ccs_read = 1, \
>+ .lacks_3d_pipeline = 1
isn't the absence of RCS sufficient so this could be done only in the
macro rather than adding a flag here?
Lucas De Marchi
>
> __maybe_unused
> static const struct intel_device_info pvc_info = {
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index 09e33296157a..972084676984 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> func(has_snoop); \
> func(has_coherent_ggtt); \
> func(unfenced_needs_alignment); \
>- func(hws_needs_physical);
>+ func(hws_needs_physical); \
>+ func(lacks_3d_pipeline);
>
> #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> /* Keep in alphabetical order */ \
>--
>2.35.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
2022-05-06 17:23 ` [Intel-gfx] " Lucas De Marchi
@ 2022-05-06 17:32 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-06 17:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Stuart Summers, intel-gfx, dri-devel
On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote:
> On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Although we already strip 3D-specific flags from PIPE_CONTROL
> > instructions when submitting to a compute engine, there are some
> > additional flags that need to be removed when the platform as a whole
> > lacks a 3D pipeline. Add those restrictions here.
> >
> > Bspec: 47112
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> > drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> > 5 files changed, 28 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3e13960615bd..11c72792573d 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = intel_ring_begin(rq, 6);
> > if (IS_ERR(cs))
> > @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > if (!HAS_FLAT_CCS(rq->engine->i915))
> > count = 8 + 4;
> > @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > /* Wa_1409600907 */
> > flags |= PIPE_CONTROL_DEPTH_STALL;
> >
> > - if (rq->engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(rq->engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (rq->engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = gen12_emit_ggtt_write_rcs(cs,
> > rq->fence.seqno,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 556bca3be804..900755f4b787 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -288,8 +288,8 @@
> > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> >
> > -/* 3D-related flags can't be set on compute engine */
> > -#define PIPE_CONTROL_3D_FLAGS (\
> > +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> > PIPE_CONTROL_TILE_CACHE_FLUSH | \
> > @@ -300,6 +300,14 @@
> > PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> > PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> >
> > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
>
> names and comments here I think are confusing. In the code we do:
>
> if (LACKS_3D_PIPELINE(engine->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> coments give the _engines_ that lack a 3D pipeline doens't seem accurate
> as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
> flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
>
> And LACKS_3D_PIPELINE... may be better to invert the condition to follow
> the other macros: HAS_3D_PIPELINE.
>
> > + PIPE_CONTROL_3D_ENGINE_FLAGS | \
> > + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> > + PIPE_CONTROL_FLUSH_ENABLE | \
> > + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> > + PIPE_CONTROL_DC_FLUSH_ENABLE)
> > +
> > #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> > #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> > /* Opcodes for MI_MATH_INSTR */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b389674b5210..1e153cefc92e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
> >
> > +#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
> > +
> > /* i915_gem.c */
> > void i915_gem_init_early(struct drm_i915_private *dev_priv);
> > void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 07722cdf63ac..14e0e8225324 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> > #define XE_HPC_FEATURES \
> > XE_HP_FEATURES, \
> > .dma_mask_size = 52, \
> > - .has_l3_ccs_read = 1
> > + .has_l3_ccs_read = 1, \
> > + .lacks_3d_pipeline = 1
>
> isn't the absence of RCS sufficient so this could be done only in the
> macro rather than adding a flag here?
No, lacking an RCS is different than lacking a 3D pipeline. That's the
main point of this patch. Platforms like XEHPSDV don't have an RCS
engine (although it looks like we're still missing the patch that
removes it from the engine list...I need to send that) but
architecturally still have bits of a vestigial 3D pipeline somewhere
under the hood. Xe_HPC truly doesn't have the pipeline at all so the
rules are different, even for the CCS engines that wouldn't do 3D
anyway.
Matt
>
> Lucas De Marchi
>
> >
> > __maybe_unused
> > static const struct intel_device_info pvc_info = {
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 09e33296157a..972084676984 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> > func(has_snoop); \
> > func(has_coherent_ggtt); \
> > func(unfenced_needs_alignment); \
> > - func(hws_needs_physical);
> > + func(hws_needs_physical); \
> > + func(lacks_3d_pipeline);
> >
> > #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> > /* Keep in alphabetical order */ \
> > --
> > 2.35.1
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
@ 2022-05-06 17:32 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-06 17:32 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote:
> On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Although we already strip 3D-specific flags from PIPE_CONTROL
> > instructions when submitting to a compute engine, there are some
> > additional flags that need to be removed when the platform as a whole
> > lacks a 3D pipeline. Add those restrictions here.
> >
> > Bspec: 47112
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> > drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> > 5 files changed, 28 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3e13960615bd..11c72792573d 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = intel_ring_begin(rq, 6);
> > if (IS_ERR(cs))
> > @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > if (!HAS_FLAT_CCS(rq->engine->i915))
> > count = 8 + 4;
> > @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > /* Wa_1409600907 */
> > flags |= PIPE_CONTROL_DEPTH_STALL;
> >
> > - if (rq->engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(rq->engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (rq->engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = gen12_emit_ggtt_write_rcs(cs,
> > rq->fence.seqno,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 556bca3be804..900755f4b787 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -288,8 +288,8 @@
> > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> >
> > -/* 3D-related flags can't be set on compute engine */
> > -#define PIPE_CONTROL_3D_FLAGS (\
> > +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> > PIPE_CONTROL_TILE_CACHE_FLUSH | \
> > @@ -300,6 +300,14 @@
> > PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> > PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> >
> > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
>
> names and comments here I think are confusing. In the code we do:
>
> if (LACKS_3D_PIPELINE(engine->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> coments give the _engines_ that lack a 3D pipeline doens't seem accurate
> as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
> flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
>
> And LACKS_3D_PIPELINE... may be better to invert the condition to follow
> the other macros: HAS_3D_PIPELINE.
>
> > + PIPE_CONTROL_3D_ENGINE_FLAGS | \
> > + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> > + PIPE_CONTROL_FLUSH_ENABLE | \
> > + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> > + PIPE_CONTROL_DC_FLUSH_ENABLE)
> > +
> > #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> > #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> > /* Opcodes for MI_MATH_INSTR */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b389674b5210..1e153cefc92e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
> >
> > +#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
> > +
> > /* i915_gem.c */
> > void i915_gem_init_early(struct drm_i915_private *dev_priv);
> > void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 07722cdf63ac..14e0e8225324 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> > #define XE_HPC_FEATURES \
> > XE_HP_FEATURES, \
> > .dma_mask_size = 52, \
> > - .has_l3_ccs_read = 1
> > + .has_l3_ccs_read = 1, \
> > + .lacks_3d_pipeline = 1
>
> isn't the absence of RCS sufficient so this could be done only in the
> macro rather than adding a flag here?
No, lacking an RCS is different than lacking a 3D pipeline. That's the
main point of this patch. Platforms like XEHPSDV don't have an RCS
engine (although it looks like we're still missing the patch that
removes it from the engine list...I need to send that) but
architecturally still have bits of a vestigial 3D pipeline somewhere
under the hood. Xe_HPC truly doesn't have the pipeline at all so the
rules are different, even for the CCS engines that wouldn't do 3D
anyway.
Matt
>
> Lucas De Marchi
>
> >
> > __maybe_unused
> > static const struct intel_device_info pvc_info = {
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 09e33296157a..972084676984 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> > func(has_snoop); \
> > func(has_coherent_ggtt); \
> > func(unfenced_needs_alignment); \
> > - func(hws_needs_physical);
> > + func(hws_needs_physical); \
> > + func(lacks_3d_pipeline);
> >
> > #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> > /* Keep in alphabetical order */ \
> > --
> > 2.35.1
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
(?)
@ 2022-05-10 6:05 ` Lucas De Marchi
-1 siblings, 0 replies; 42+ messages in thread
From: Lucas De Marchi @ 2022-05-10 6:05 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Thu, May 05, 2022 at 02:38:07PM -0700, Matt Roper wrote:
>When i915 adds additional PVC blitter instances (in an upcoming patch),
>the definition of VECS0 will change from bit(10) to bit(18), causing
>GVT's R_ALL mask to overflow the u16 storage that's currently used.
>Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
>this.
>
>Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>Cc: Zhi Wang <zhi.a.wang@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Introduce Ponte Vecchio (rev3)
2022-05-06 4:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-05-10 22:43 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-10 22:43 UTC (permalink / raw)
To: intel-gfx
On Fri, May 06, 2022 at 04:29:37AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Introduce Ponte Vecchio (rev3)
> URL : https://patchwork.freedesktop.org/series/103443/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11613_full -> Patchwork_103443v3_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Pushed the reviewed patches (all except the two forcewake patches and
the PIPE_CONTROL patch) to drm-intel-gt-next.
Thanks for the reviews.
Matt
>
>
>
> Participating hosts (10 -> 12)
> ------------------------------
>
> Additional (2): shard-rkl shard-tglu
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103443v3_full:
>
> ### IGT changes ###
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@kms_plane_scaling@downscale-with-modifier-factor-0-25}:
> - {shard-rkl}: NOTRUN -> [SKIP][1] +4 similar issues
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-rkl-2/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103443v3_full that come from known issues:
>
> ### CI changes ###
>
> #### Possible fixes ####
>
> * boot:
> - shard-apl: ([PASS][2], [FAIL][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#4386]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/boot.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/boot.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/boot.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl4/boot.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/boot.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/boot.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/boot.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/boot.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/boot.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/boot.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/boot.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/boot.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/boot.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/boot.html
>
>
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_eio@unwedge-stress:
> - shard-iclb: NOTRUN -> [TIMEOUT][52] ([i915#3070])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_fair@basic-deadline:
> - shard-glk: [PASS][53] -> [FAIL][54] ([i915#2846])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk4/igt@gem_exec_fair@basic-deadline.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk4/igt@gem_exec_fair@basic-deadline.html
>
> * igt@gem_exec_fair@basic-none@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][55] ([i915#2842])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-apl: [PASS][56] -> [FAIL][57] ([i915#2842])
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-kbl: NOTRUN -> [FAIL][58] ([i915#2842])
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
>
> * igt@gem_exec_fair@basic-pace@vecs0:
> - shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842])
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-iclb: [PASS][61] -> [FAIL][62] ([i915#2849])
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
>
> * igt@gem_exec_flush@basic-batch-kernel-default-uc:
> - shard-snb: [PASS][63] -> [SKIP][64] ([fdo#109271]) +2 similar issues
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-snb5/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [PASS][65] -> [SKIP][66] ([i915#2190])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb5/igt@gem_huc_copy@huc-copy.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb7/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@parallel-random:
> - shard-iclb: NOTRUN -> [SKIP][67] ([i915#4613])
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_lmem_swapping@parallel-random.html
>
> * igt@gem_lmem_swapping@parallel-random-verify-ccs:
> - shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
>
> * igt@gem_lmem_swapping@random:
> - shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613])
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@gem_lmem_swapping@random.html
>
> * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
> - shard-iclb: NOTRUN -> [SKIP][70] ([i915#4270])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
>
> * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
> - shard-iclb: NOTRUN -> [SKIP][71] ([i915#768])
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
>
> * igt@gem_softpin@evict-single-offset:
> - shard-kbl: NOTRUN -> [FAIL][72] ([i915#4171])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_softpin@evict-single-offset.html
>
> * igt@gem_softpin@evict-snoop:
> - shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109312])
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_softpin@evict-snoop.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-kbl: [PASS][74] -> [DMESG-WARN][75] ([i915#180]) +1 similar issue
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@gen3_render_linear_blits:
> - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109289])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gen3_render_linear_blits.html
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-glk: [PASS][77] -> [DMESG-WARN][78] ([i915#5566] / [i915#716])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk1/igt@gen9_exec_parse@allowed-single.html
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk4/igt@gen9_exec_parse@allowed-single.html
>
> * igt@gen9_exec_parse@basic-rejected:
> - shard-iclb: NOTRUN -> [SKIP][79] ([i915#2856]) +1 similar issue
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gen9_exec_parse@basic-rejected.html
>
> * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
> - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#1937])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
>
> * igt@i915_pm_rc6_residency@rc6-fence:
> - shard-iclb: NOTRUN -> [WARN][81] ([i915#2684])
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
>
> * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
> - shard-iclb: NOTRUN -> [SKIP][82] ([i915#5286])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
>
> * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
> - shard-iclb: NOTRUN -> [SKIP][83] ([fdo#110725] / [fdo#111614])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
>
> * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
> - shard-skl: NOTRUN -> [FAIL][84] ([i915#3763])
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
>
> * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
> - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109278] / [i915#3886]) +2 similar issues
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
> - shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3886]) +6 similar issues
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
> - shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +1 similar issue
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
> - shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +6 similar issues
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_chamelium@dp-hpd-storm-disable:
> - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [fdo#111827]) +5 similar issues
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_chamelium@dp-hpd-storm-disable.html
>
> * igt@kms_chamelium@hdmi-hpd-storm-disable:
> - shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +6 similar issues
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_chamelium@hdmi-hpd-storm-disable.html
>
> * igt@kms_color_chamelium@pipe-b-ctm-0-5:
> - shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827])
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
>
> * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
> - shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109284] / [fdo#111827]) +1 similar issue
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
>
> * igt@kms_content_protection@uevent:
> - shard-kbl: NOTRUN -> [FAIL][93] ([i915#2105])
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_content_protection@uevent.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
> - shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109278] / [fdo#109279]) +2 similar issues
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen:
> - shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278]) +8 similar issues
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-32x10-onscreen.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
> - shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +101 similar issues
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
> - shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109274] / [fdo#109278])
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
>
> * igt@kms_cursor_legacy@pipe-d-torture-bo:
> - shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#533]) +1 similar issue
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
> - shard-skl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533])
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_cursor_legacy@pipe-d-torture-bo.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled:
> - shard-iclb: NOTRUN -> [SKIP][100] ([i915#5287])
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-4tiled.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-apl: [PASS][101] -> [FAIL][102] ([i915#4767])
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
> - shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274]) +2 similar issues
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
> - shard-skl: [PASS][104] -> [FAIL][105] ([i915#2122])
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc:
> - shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271]) +40 similar issues
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
> - shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109280]) +8 similar issues
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
> - shard-iclb: NOTRUN -> [SKIP][108] ([i915#1839])
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
> - shard-apl: [PASS][109] -> [DMESG-WARN][110] ([i915#180]) +4 similar issues
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
> - shard-kbl: [PASS][111] -> [INCOMPLETE][112] ([i915#3614])
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
> - shard-skl: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265]) +1 similar issue
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][114] -> [FAIL][115] ([fdo#108145] / [i915#265])
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-d-tiling-yf:
> - shard-skl: NOTRUN -> [SKIP][116] ([fdo#109271]) +89 similar issues
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_plane_lowres@pipe-d-tiling-yf.html
>
> * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
> - shard-iclb: [PASS][117] -> [SKIP][118] ([i915#5235]) +2 similar issues
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
>
> * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
> - shard-skl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658])
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
>
> * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
> - shard-iclb: NOTRUN -> [SKIP][120] ([i915#658])
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
>
> * igt@kms_psr2_sf@plane-move-sf-dmg-area:
> - shard-kbl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#658])
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
>
> * igt@kms_psr2_su@frontbuffer-xrgb8888:
> - shard-iclb: [PASS][122] -> [SKIP][123] ([fdo#109642] / [fdo#111068] / [i915#658])
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr2_su@frontbuffer-xrgb8888.html
>
> * igt@kms_psr@psr2_dpms:
> - shard-iclb: [PASS][124] -> [SKIP][125] ([fdo#109441]) +1 similar issue
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr@psr2_dpms.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr@psr2_dpms.html
>
> * igt@kms_vrr@flipline:
> - shard-iclb: NOTRUN -> [SKIP][126] ([i915#3555])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@kms_vrr@flipline.html
>
> * igt@nouveau_crc@pipe-d-source-outp-complete:
> - shard-iclb: NOTRUN -> [SKIP][127] ([fdo#109278] / [i915#2530])
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@nouveau_crc@pipe-d-source-outp-complete.html
>
> * igt@perf@polling-small-buf:
> - shard-skl: [PASS][128] -> [FAIL][129] ([i915#1722])
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl6/igt@perf@polling-small-buf.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl1/igt@perf@polling-small-buf.html
>
> * igt@sysfs_clients@recycle-many:
> - shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#2994]) +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl8/igt@sysfs_clients@recycle-many.html
>
>
> #### Possible fixes ####
>
> * igt@feature_discovery@psr2:
> - shard-iclb: [SKIP][131] ([i915#658]) -> [PASS][132]
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb3/igt@feature_discovery@psr2.html
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@feature_discovery@psr2.html
>
> * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl: [FAIL][133] ([i915#2842]) -> [PASS][134] +3 similar issues
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
>
> * igt@gem_exec_flush@basic-wb-set-default:
> - shard-snb: [SKIP][135] ([fdo#109271]) -> [PASS][136] +3 similar issues
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-snb6/igt@gem_exec_flush@basic-wb-set-default.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-snb4/igt@gem_exec_flush@basic-wb-set-default.html
>
> * igt@gem_exec_whisper@basic-contexts-priority:
> - shard-glk: [DMESG-WARN][137] ([i915#118]) -> [PASS][138] +2 similar issues
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-glk6/igt@gem_exec_whisper@basic-contexts-priority.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][139] ([i915#180]) -> [PASS][140]
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
> - shard-iclb: [FAIL][141] ([i915#2346]) -> [PASS][142]
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
> - shard-skl: [INCOMPLETE][143] ([i915#4939]) -> [PASS][144] +1 similar issue
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@a-dp1:
> - shard-apl: [DMESG-WARN][145] ([i915#180]) -> [PASS][146] +2 similar issues
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
>
> * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
> - shard-skl: [FAIL][147] ([i915#2122]) -> [PASS][148]
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
> [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
>
> * igt@kms_frontbuffer_tracking@psr-suspend:
> - shard-tglb: [DMESG-WARN][149] ([i915#2411]) -> [PASS][150]
> [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-tglb3/igt@kms_frontbuffer_tracking@psr-suspend.html
> [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-tglb5/igt@kms_frontbuffer_tracking@psr-suspend.html
>
> * igt@kms_psr@psr2_cursor_mmap_cpu:
> - shard-iclb: [SKIP][151] ([fdo#109441]) -> [PASS][152] +2 similar issues
> [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
> [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
>
>
> #### Warnings ####
>
> * igt@gem_exec_balancer@parallel-contexts:
> - shard-iclb: [SKIP][153] ([i915#4525]) -> [DMESG-WARN][154] ([i915#5614])
> [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html
> [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
>
> * igt@gem_exec_balancer@parallel-ordering:
> - shard-iclb: [DMESG-FAIL][155] ([i915#5614]) -> [SKIP][156] ([i915#4525])
> [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
> [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
>
> * igt@kms_plane_cursor@pipe-d-overlay-size-256:
> - shard-skl: [SKIP][157] ([fdo#109271]) -> [SKIP][158] ([fdo#109271] / [i915#1888])
> [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_plane_cursor@pipe-d-overlay-size-256.html
> [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_plane_cursor@pipe-d-overlay-size-256.html
>
> * igt@kms_plane_multiple@atomic-pipe-d-tiling-y:
> - shard-skl: [SKIP][159] ([fdo#109271] / [i915#1888]) -> [SKIP][160] ([fdo#109271])
> [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-skl9/igt@kms_plane_multiple@atomic-pipe-d-tiling-y.html
> [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-skl7/igt@kms_plane_multiple@atomic-pipe-d-tiling-y.html
>
> * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
> - shard-iclb: [SKIP][161] ([i915#2920]) -> [SKIP][162] ([fdo#111068] / [i915#658])
> [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
> [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-iclb: [SKIP][163] ([fdo#111068] / [i915#658]) -> [SKIP][164] ([i915#2920])
> [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
> [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
> [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl2/igt@runner@aborted.html
> [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl6/igt@runner@aborted.html
> [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl8/igt@runner@aborted.html
> [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/igt@runner@aborted.html
> [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl7/igt@runner@aborted.html
> [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-apl1/igt@runner@aborted.html
> [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/igt@runner@aborted.html
> [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl1/igt@runner@aborted.html
> [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@runner@aborted.html
> [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@runner@aborted.html
> [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl4/igt@runner@aborted.html
> [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl3/igt@runner@aborted.html
> [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl2/igt@runner@aborted.html
> [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-apl6/igt@runner@aborted.html
> - shard-kbl: ([FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
> [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@runner@aborted.html
> [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
> [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
> [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl7/igt@runner@aborted.html
> [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
> [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl4/igt@runner@aborted.html
> [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
> [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
> [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl3/igt@runner@aborted.html
> [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
> [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl6/igt@runner@aborted.html
> [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11613/shard-kbl1/igt@runner@aborted.html
> [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
> [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
> [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl6/igt@runner@aborted.html
> [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
> [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl3/igt@runner@aborted.html
> [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl6/igt@runner@aborted.html
> [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl1/igt@runner@aborted.html
> [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl7/igt@runner@aborted.html
> [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
> [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl7/igt@runner@aborted.html
> [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
> [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/shard-kbl4/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
> [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
> [fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
> [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
> [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
> [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
> [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
> [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
> [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
> [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
> [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
> [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
> [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
> [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
> [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
> [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
> [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
> [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
> [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
> [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
> [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
> [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
> [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
> [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
> [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
> [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
> [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
> [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
> [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
> [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> [i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
> [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
> [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
> [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
> [i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
> [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
> [i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
> [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
> [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
> [i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
> [i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
> [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
> [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
> [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
> [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
> [i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
> [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
> [i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
> [i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
> [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
> [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
> [i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
> [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11613 -> Patchwork_103443v3
>
> CI-20190529: 20190529
> CI_DRM_11613: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6467: 929abc51cdd48d673efa03e025b1f31b557972ed @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103443v3: ad303c70b93ba69fa8eb8cd90411b64830857f7b @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103443v3/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
2022-05-06 17:23 ` [Intel-gfx] " Lucas De Marchi
@ 2022-05-11 5:45 ` Matt Roper
-1 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-11 5:45 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Stuart Summers, intel-gfx, dri-devel
On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote:
> On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Although we already strip 3D-specific flags from PIPE_CONTROL
> > instructions when submitting to a compute engine, there are some
> > additional flags that need to be removed when the platform as a whole
> > lacks a 3D pipeline. Add those restrictions here.
> >
> > Bspec: 47112
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> > drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> > 5 files changed, 28 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3e13960615bd..11c72792573d 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = intel_ring_begin(rq, 6);
> > if (IS_ERR(cs))
> > @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > if (!HAS_FLAT_CCS(rq->engine->i915))
> > count = 8 + 4;
> > @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > /* Wa_1409600907 */
> > flags |= PIPE_CONTROL_DEPTH_STALL;
> >
> > - if (rq->engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(rq->engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (rq->engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = gen12_emit_ggtt_write_rcs(cs,
> > rq->fence.seqno,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 556bca3be804..900755f4b787 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -288,8 +288,8 @@
> > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> >
> > -/* 3D-related flags can't be set on compute engine */
> > -#define PIPE_CONTROL_3D_FLAGS (\
> > +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> > PIPE_CONTROL_TILE_CACHE_FLUSH | \
> > @@ -300,6 +300,14 @@
> > PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> > PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> >
> > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
>
> names and comments here I think are confusing. In the code we do:
>
> if (LACKS_3D_PIPELINE(engine->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> coments give the _engines_ that lack a 3D pipeline doens't seem accurate
> as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
> flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
No, that's what we're trying to avoid here. Presence/absence of the 3D
pipeline is a characteristic of the platform, not of the engine. A CCS
engine doesn't have access to the 3D pipeline on any platform (that's
what makes it different from an RCS), but we still wind up needing to
program the PIPE_CONTROL flags for a CCS engine differently on a
platform like PVC (which doesn't have a 3D pipeline at all) vs Xe_HP SDV
(which does have a vestigial 3D pipeline, even though it isn't directly
usable).
Basically:
RCS:
All flags used
CCS on Xe_HP SDV or DG2:
Strip out flags specific to RCS engines
CCS on PVC:
Strip out flags that only exist on platforms with an
architectural 3D pipeline *and* strip out flags specific to
RCS engines
>
> And LACKS_3D_PIPELINE... may be better to invert the condition to follow
> the other macros: HAS_3D_PIPELINE.
I think the code was written that way originally, but we flipped it
because adding the flag to every single platform from gen2 onward
obfuscated the fact that the absence of a standard hardware block was a
notable characteristic our code needs to look for, rather than the
presence of something. The conditions in the code will always be
written in the inverted form "!HAS_3D_PIPELINE" so reversing it and
making it a positive "LACKS" seemed more natural. But I can switch it
back and we can see how that looks.
>
> > + PIPE_CONTROL_3D_ENGINE_FLAGS | \
> > + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> > + PIPE_CONTROL_FLUSH_ENABLE | \
> > + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> > + PIPE_CONTROL_DC_FLUSH_ENABLE)
> > +
> > #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> > #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> > /* Opcodes for MI_MATH_INSTR */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b389674b5210..1e153cefc92e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
> >
> > +#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
> > +
> > /* i915_gem.c */
> > void i915_gem_init_early(struct drm_i915_private *dev_priv);
> > void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 07722cdf63ac..14e0e8225324 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> > #define XE_HPC_FEATURES \
> > XE_HP_FEATURES, \
> > .dma_mask_size = 52, \
> > - .has_l3_ccs_read = 1
> > + .has_l3_ccs_read = 1, \
> > + .lacks_3d_pipeline = 1
>
> isn't the absence of RCS sufficient so this could be done only in the
> macro rather than adding a flag here?
No, absence of RCS does not imply absence of the 3D pipeline, just that
there's no engine that can use it. Xe_HP SDV is still based on an
architecture with a 3D pipeline, even though it doesn't have an RCS
engine to access it, so its CCS engines have different PIPE_CONTROL
requirements than PVC's CCS engines.
Matt
>
> Lucas De Marchi
>
> >
> > __maybe_unused
> > static const struct intel_device_info pvc_info = {
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 09e33296157a..972084676984 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> > func(has_snoop); \
> > func(has_coherent_ggtt); \
> > func(unfenced_needs_alignment); \
> > - func(hws_needs_physical);
> > + func(hws_needs_physical); \
> > + func(lacks_3d_pipeline);
> >
> > #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> > /* Keep in alphabetical order */ \
> > --
> > 2.35.1
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Intel-gfx] [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL
@ 2022-05-11 5:45 ` Matt Roper
0 siblings, 0 replies; 42+ messages in thread
From: Matt Roper @ 2022-05-11 5:45 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Fri, May 06, 2022 at 10:23:41AM -0700, Lucas De Marchi wrote:
> On Thu, May 05, 2022 at 02:38:05PM -0700, Matt Roper wrote:
> > From: Stuart Summers <stuart.summers@intel.com>
> >
> > Although we already strip 3D-specific flags from PIPE_CONTROL
> > instructions when submitting to a compute engine, there are some
> > additional flags that need to be removed when the platform as a whole
> > lacks a 3D pipeline. Add those restrictions here.
> >
> > Bspec: 47112
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 ++++++++++++------
> > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 ++++++++++--
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> > drivers/gpu/drm/i915/intel_device_info.h | 3 ++-
> > 5 files changed, 28 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3e13960615bd..11c72792573d 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -197,8 +197,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = intel_ring_begin(rq, 6);
> > if (IS_ERR(cs))
> > @@ -227,8 +229,10 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> >
> > flags |= PIPE_CONTROL_CS_STALL;
> >
> > - if (engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > if (!HAS_FLAT_CCS(rq->engine->i915))
> > count = 8 + 4;
> > @@ -716,8 +720,10 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > /* Wa_1409600907 */
> > flags |= PIPE_CONTROL_DEPTH_STALL;
> >
> > - if (rq->engine->class == COMPUTE_CLASS)
> > - flags &= ~PIPE_CONTROL_3D_FLAGS;
> > + if (LACKS_3D_PIPELINE(rq->engine->i915))
> > + flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> > + else if (rq->engine->class == COMPUTE_CLASS)
> > + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> >
> > cs = gen12_emit_ggtt_write_rcs(cs,
> > rq->fence.seqno,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 556bca3be804..900755f4b787 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -288,8 +288,8 @@
> > #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
> > #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
> >
> > -/* 3D-related flags can't be set on compute engine */
> > -#define PIPE_CONTROL_3D_FLAGS (\
> > +/* 3D-related flags that can't be set on _engines_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
> > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
> > PIPE_CONTROL_TILE_CACHE_FLUSH | \
> > @@ -300,6 +300,14 @@
> > PIPE_CONTROL_VF_CACHE_INVALIDATE | \
> > PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
> >
> > +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
> > +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
>
> names and comments here I think are confusing. In the code we do:
>
> if (LACKS_3D_PIPELINE(engine->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> coments give the _engines_ that lack a 3D pipeline doens't seem accurate
> as bcs, vcs, vecs also lack a 3d pipeline. Maybe be explicit about the
> flags being set on compute engine: PIPE_CONTROL_COMPUTE_ENGINE_FLAGS
No, that's what we're trying to avoid here. Presence/absence of the 3D
pipeline is a characteristic of the platform, not of the engine. A CCS
engine doesn't have access to the 3D pipeline on any platform (that's
what makes it different from an RCS), but we still wind up needing to
program the PIPE_CONTROL flags for a CCS engine differently on a
platform like PVC (which doesn't have a 3D pipeline at all) vs Xe_HP SDV
(which does have a vestigial 3D pipeline, even though it isn't directly
usable).
Basically:
RCS:
All flags used
CCS on Xe_HP SDV or DG2:
Strip out flags specific to RCS engines
CCS on PVC:
Strip out flags that only exist on platforms with an
architectural 3D pipeline *and* strip out flags specific to
RCS engines
>
> And LACKS_3D_PIPELINE... may be better to invert the condition to follow
> the other macros: HAS_3D_PIPELINE.
I think the code was written that way originally, but we flipped it
because adding the flag to every single platform from gen2 onward
obfuscated the fact that the absence of a standard hardware block was a
notable characteristic our code needs to look for, rather than the
presence of something. The conditions in the code will always be
written in the inverted form "!HAS_3D_PIPELINE" so reversing it and
making it a positive "LACKS" seemed more natural. But I can switch it
back and we can see how that looks.
>
> > + PIPE_CONTROL_3D_ENGINE_FLAGS | \
> > + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
> > + PIPE_CONTROL_FLUSH_ENABLE | \
> > + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
> > + PIPE_CONTROL_DC_FLUSH_ENABLE)
> > +
> > #define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> > #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> > /* Opcodes for MI_MATH_INSTR */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b389674b5210..1e153cefc92e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1403,6 +1403,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
> >
> > +#define LACKS_3D_PIPELINE(i915) (INTEL_INFO(i915)->lacks_3d_pipeline)
> > +
> > /* i915_gem.c */
> > void i915_gem_init_early(struct drm_i915_private *dev_priv);
> > void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 07722cdf63ac..14e0e8225324 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1077,7 +1077,8 @@ static const struct intel_device_info ats_m_info = {
> > #define XE_HPC_FEATURES \
> > XE_HP_FEATURES, \
> > .dma_mask_size = 52, \
> > - .has_l3_ccs_read = 1
> > + .has_l3_ccs_read = 1, \
> > + .lacks_3d_pipeline = 1
>
> isn't the absence of RCS sufficient so this could be done only in the
> macro rather than adding a flag here?
No, absence of RCS does not imply absence of the 3D pipeline, just that
there's no engine that can use it. Xe_HP SDV is still based on an
architecture with a 3D pipeline, even though it doesn't have an RCS
engine to access it, so its CCS engines have different PIPE_CONTROL
requirements than PVC's CCS engines.
Matt
>
> Lucas De Marchi
>
> >
> > __maybe_unused
> > static const struct intel_device_info pvc_info = {
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index 09e33296157a..972084676984 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -165,7 +165,8 @@ enum intel_ppgtt_type {
> > func(has_snoop); \
> > func(has_coherent_ggtt); \
> > func(unfenced_needs_alignment); \
> > - func(hws_needs_physical);
> > + func(hws_needs_physical); \
> > + func(lacks_3d_pipeline);
> >
> > #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
> > /* Keep in alphabetical order */ \
> > --
> > 2.35.1
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2022-05-11 5:45 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-05 21:38 [PATCH v2 00/12] i915: Introduce Ponte Vecchio Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 01/12] drm/i915/uncore: Reorganize and document shadow and forcewake tables Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 02/12] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 03/12] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-06 17:08 ` Lucas De Marchi
2022-05-05 21:38 ` [PATCH v2 04/12] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 05/12] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-06 17:23 ` Lucas De Marchi
2022-05-06 17:23 ` [Intel-gfx] " Lucas De Marchi
2022-05-06 17:32 ` Matt Roper
2022-05-06 17:32 ` [Intel-gfx] " Matt Roper
2022-05-11 5:45 ` Matt Roper
2022-05-11 5:45 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 06/12] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 07/12] drm/i915/gvt: Use intel_engine_mask_t for ring mask Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-10 6:05 ` Lucas De Marchi
2022-05-05 21:38 ` [PATCH v2 08/12] drm/i915/pvc: Engine definitions for new copy engines Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 09/12] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 10/12] drm/i915/pvc: Reset " Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 11/12] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 21:38 ` [PATCH v2 12/12] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-05 21:38 ` [Intel-gfx] " Matt Roper
2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev2) Patchwork
2022-05-05 22:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05 22:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-06 0:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Ponte Vecchio (rev3) Patchwork
2022-05-06 0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-06 1:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-06 4:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-10 22:43 ` Matt Roper
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