From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 437DCC433EF for ; Thu, 5 May 2022 23:58:21 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 0704660BCA; Thu, 5 May 2022 23:58:21 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q8jKZWyQNf7x; Thu, 5 May 2022 23:58:20 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [IPv6:2605:bc80:3010:104::8cd3:938]) by smtp3.osuosl.org (Postfix) with ESMTPS id D890C610F7; Thu, 5 May 2022 23:58:19 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id ADD20C0032; Thu, 5 May 2022 23:58:19 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists.linuxfoundation.org (Postfix) with ESMTP id 1A263C002D for ; Thu, 5 May 2022 23:58:16 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 9328660B6A for ; Thu, 5 May 2022 23:57:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cCWQjAMGf5eg for ; Thu, 5 May 2022 23:57:58 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.8.0 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp3.osuosl.org (Postfix) with ESMTPS id E994A60BC6 for ; Thu, 5 May 2022 23:57:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651795077; x=1683331077; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+ZwU4efMPyk6LipSXhNxIogBqScj1OvsPJuz+1wxs4g=; b=XWzfbWgkh/hzFukcf8m3Hjpyv0kVUzJStlF+L1DK5AuRvZpSS34B20t5 4ELKi199M5Zr7/FRMs4N3RFtdj81Nfpn1kvK5Nu/VHexpj+24+NzSIDMM +sb3NMS5DWw+A5EnNe1/UdWygjJKp5MTVz2sOw+/YPUdOi3UdAOj3TdqQ hVJJZzktEY/pVN5rnGfWRuFL1VuIPJKOxzSHfsq5dakefSRNKopYw7ai1 Fku9RgVHQsgdTD8teCHh9ev+02sVHbfAAvJMnHEPf5Qw40D76JWp9FXL3 tOU5KRaw+DTtIuqVFJ2+4slCGD09OfaK9Vv+wVNhzNRaXi2abBdt2SIdv g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="293496382" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="293496382" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 16:57:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="694914459" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga004.jf.intel.com with ESMTP; 05 May 2022 16:57:57 -0700 From: Ricardo Neri To: Thomas Gleixner , x86@kernel.org Subject: [PATCH v6 29/29] x86/tsc: Switch to perf-based hardlockup detector if TSC become unstable Date: Thu, 5 May 2022 17:00:08 -0700 Message-Id: <20220506000008.30892-30-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> Cc: "Ravi V. Shankar" , Andi Kleen , linuxppc-dev@lists.ozlabs.org, Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Tony Luck , Nicholas Piggin , Ricardo Neri , Andrew Morton , David Woodhouse X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. In such case, permanently stop the HPET-based hardlockup detector and start the perf-based detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v5: * Relocated the delcaration of hardlockup_detector_switch_to_perf() to x86/nmi.h It does not depend on HPET. * Removed function stub. The shim hardlockup detector is always for x86. Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 6 ++++++ arch/x86/kernel/tsc.c | 2 ++ arch/x86/kernel/watchdog_hld.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 4a0d5b562c91..47752ff67d8b 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -63,4 +63,10 @@ void stop_nmi(void); void restart_nmi(void); void local_touch_nmi(void); +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR +void hardlockup_detector_switch_to_perf(void); +#else +static inline void hardlockup_detector_switch_to_perf(void) { } +#endif + #endif /* _ASM_X86_NMI_H */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index cc1843044d88..74772ffc79d1 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1176,6 +1176,8 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + hardlockup_detector_switch_to_perf(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index ef11f0af4ef5..7940977c6312 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -83,3 +83,9 @@ void watchdog_nmi_start(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_start(); } + +void hardlockup_detector_switch_to_perf(void) +{ + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + lockup_detector_reconfigure(); +} -- 2.17.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4469C433EF for ; Fri, 6 May 2022 00:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387353AbiEFAEp (ORCPT ); Thu, 5 May 2022 20:04:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1387094AbiEFACl (ORCPT ); Thu, 5 May 2022 20:02:41 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3CE061637 for ; Thu, 5 May 2022 16:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651795084; x=1683331084; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+ZwU4efMPyk6LipSXhNxIogBqScj1OvsPJuz+1wxs4g=; b=VChzPwj/PQuOBhNK/FhVuRBaTubzzNmtuuak/CGOyFEvkjt7BZoOEWZa ijOyLePElG0OcXdLw/IIx6loKGRAUzCGGfZRZV+rCWRt3XDjeskroXOHA T5CMd3tkGN+Dzo4y/SG2WWQ0U+Ejk17gp6lVQqQYVfSPg+9hAeSC1O0Jj gbRIdghndZqTnub6wxM1ZlEjGRJHfCXLp2LRt7rONW3hM15to1aCTuLu3 C4FS79WxFJ+ZX2YYaAsW4YpMqDUUBpXVjVbIiMu5hjzB2RtFGFKOVc53K s/72sSx48eFdh6AWNq6CVjBwK0IKKgYszvwGUEYxDdHtEIu+EWIyyZbor w==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="250283666" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="250283666" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 16:57:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="694914459" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga004.jf.intel.com with ESMTP; 05 May 2022 16:57:57 -0700 From: Ricardo Neri To: Thomas Gleixner , x86@kernel.org Cc: Tony Luck , Andi Kleen , Stephane Eranian , Andrew Morton , Joerg Roedel , Suravee Suthikulpanit , David Woodhouse , Lu Baolu , Nicholas Piggin , "Ravi V. Shankar" , Ricardo Neri , iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH v6 29/29] x86/tsc: Switch to perf-based hardlockup detector if TSC become unstable Date: Thu, 5 May 2022 17:00:08 -0700 Message-Id: <20220506000008.30892-30-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. In such case, permanently stop the HPET-based hardlockup detector and start the perf-based detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v5: * Relocated the delcaration of hardlockup_detector_switch_to_perf() to x86/nmi.h It does not depend on HPET. * Removed function stub. The shim hardlockup detector is always for x86. Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 6 ++++++ arch/x86/kernel/tsc.c | 2 ++ arch/x86/kernel/watchdog_hld.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 4a0d5b562c91..47752ff67d8b 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -63,4 +63,10 @@ void stop_nmi(void); void restart_nmi(void); void local_touch_nmi(void); +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR +void hardlockup_detector_switch_to_perf(void); +#else +static inline void hardlockup_detector_switch_to_perf(void) { } +#endif + #endif /* _ASM_X86_NMI_H */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index cc1843044d88..74772ffc79d1 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1176,6 +1176,8 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + hardlockup_detector_switch_to_perf(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index ef11f0af4ef5..7940977c6312 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -83,3 +83,9 @@ void watchdog_nmi_start(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_start(); } + +void hardlockup_detector_switch_to_perf(void) +{ + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + lockup_detector_reconfigure(); +} -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB6D3C433F5 for ; Fri, 6 May 2022 00:17:27 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KvWNQ1ZyFz3cfr for ; Fri, 6 May 2022 10:17:26 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=nIKjOUHY; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=ricardo.neri-calderon@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=nIKjOUHY; dkim-atps=neutral Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KvVzb2lK7z3cFT for ; Fri, 6 May 2022 09:59:23 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651795163; x=1683331163; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+ZwU4efMPyk6LipSXhNxIogBqScj1OvsPJuz+1wxs4g=; b=nIKjOUHYDAyOBmV5TnWm5UThdbP/o2ewIQcxfp9jIwUTdowZOkDIlgyT aUhE+5dJFNyetNUVQZBqprNxpUnwCfj744WOlHcx8HjL0TB6tte49Br2J UgEgqjhz9fBbrcHgRJG8MRo3ws8Yq8tyL+Bt8Se7EywnEW6vZLGPhXnV/ BoxPp+/zuCB48oMQsuuJvSrKyovzvhftM4gN8uHZ+VCmhJaUJNJU13fuz w3jqJbd/UxLDhBFXZNEpaKjMaUVi/yP9fCndjXlW3Z97jfTY31xT/8adL QE0P70DLGf6Qy/WwBmsyoE1ghf/+0C/CFr45E0OawDqzBIsXJvGZy4bFk g==; X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="268437346" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="268437346" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 16:57:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="694914459" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga004.jf.intel.com with ESMTP; 05 May 2022 16:57:57 -0700 From: Ricardo Neri To: Thomas Gleixner , x86@kernel.org Subject: [PATCH v6 29/29] x86/tsc: Switch to perf-based hardlockup detector if TSC become unstable Date: Thu, 5 May 2022 17:00:08 -0700 Message-Id: <20220506000008.30892-30-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Ravi V. Shankar" , Andi Kleen , linuxppc-dev@lists.ozlabs.org, Joerg Roedel , Ricardo Neri , Stephane Eranian , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Tony Luck , Nicholas Piggin , Suravee Suthikulpanit , Ricardo Neri , Andrew Morton , David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" The HPET-based hardlockup detector relies on the TSC to determine if an observed NMI interrupt was originated by HPET timer. Hence, this detector can no longer be used with an unstable TSC. In such case, permanently stop the HPET-based hardlockup detector and start the perf-based detector. Cc: Andi Kleen Cc: Stephane Eranian Cc: "Ravi V. Shankar" Cc: iommu@lists.linux-foundation.org Cc: linuxppc-dev@lists.ozlabs.org Cc: x86@kernel.org Suggested-by: Thomas Gleixner Reviewed-by: Tony Luck Signed-off-by: Ricardo Neri --- Changes since v5: * Relocated the delcaration of hardlockup_detector_switch_to_perf() to x86/nmi.h It does not depend on HPET. * Removed function stub. The shim hardlockup detector is always for x86. Changes since v4: * Added a stub version of hardlockup_detector_switch_to_perf() for !CONFIG_HPET_TIMER. (lkp) * Reconfigure the whole lockup detector instead of unconditionally starting the perf-based hardlockup detector. Changes since v3: * None Changes since v2: * Introduced this patch. Changes since v1: * N/A --- arch/x86/include/asm/nmi.h | 6 ++++++ arch/x86/kernel/tsc.c | 2 ++ arch/x86/kernel/watchdog_hld.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index 4a0d5b562c91..47752ff67d8b 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h @@ -63,4 +63,10 @@ void stop_nmi(void); void restart_nmi(void); void local_touch_nmi(void); +#ifdef CONFIG_X86_HARDLOCKUP_DETECTOR +void hardlockup_detector_switch_to_perf(void); +#else +static inline void hardlockup_detector_switch_to_perf(void) { } +#endif + #endif /* _ASM_X86_NMI_H */ diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index cc1843044d88..74772ffc79d1 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1176,6 +1176,8 @@ void mark_tsc_unstable(char *reason) clocksource_mark_unstable(&clocksource_tsc_early); clocksource_mark_unstable(&clocksource_tsc); + + hardlockup_detector_switch_to_perf(); } EXPORT_SYMBOL_GPL(mark_tsc_unstable); diff --git a/arch/x86/kernel/watchdog_hld.c b/arch/x86/kernel/watchdog_hld.c index ef11f0af4ef5..7940977c6312 100644 --- a/arch/x86/kernel/watchdog_hld.c +++ b/arch/x86/kernel/watchdog_hld.c @@ -83,3 +83,9 @@ void watchdog_nmi_start(void) if (detector_type == X86_HARDLOCKUP_DETECTOR_HPET) hardlockup_detector_hpet_start(); } + +void hardlockup_detector_switch_to_perf(void) +{ + detector_type = X86_HARDLOCKUP_DETECTOR_PERF; + lockup_detector_reconfigure(); +} -- 2.17.1