From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36B84C433F5 for ; Fri, 6 May 2022 09:40:22 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1F48881D8C; Fri, 6 May 2022 11:40:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="fFNOyHEK"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id BFF2F81DE9; Fri, 6 May 2022 11:40:17 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4C4CF80112 for ; Fri, 6 May 2022 11:40:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A573861FA1; Fri, 6 May 2022 09:40:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7A52C385A8; Fri, 6 May 2022 09:40:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651830012; bh=s/Qfj/wEJBr6LMl/f+kORCYAoBufy4scXx3azQC+sHA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fFNOyHEKsHeMQa3soPE5Cx9ABu2rPUR8nthTxFDrHIFof6t/VvpxZP0XPOSLbsm7X w3qtHg4v429WkFIQ6IuOh2gaw4WL20Qgoikz8AG2TnaHQ5Y+7ebWfi1K+mIxCKcvDj rBG1obPpWZezgjw9xMp+vcGHq2T5xtUq3VIL5j3rD/P7L+6tOBisaypmoMOpsy2EPx wjGFs4Zp0GtekpvPxqtO+/GkbQi2ASZcq70pa6PL/9YjPMb2rzQG/FcHtGtt7MGL+v Wpae12Y0D+Je4DHuqSVeMptm7Qg+ne7n1PIm514Sec8ossmsuopDoZhvj90nn13GCv p7t3ZVtEyG2kQ== Received: by pali.im (Postfix) id 1209B1141; Fri, 6 May 2022 11:40:08 +0200 (CEST) Date: Fri, 6 May 2022 11:40:08 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Jaehoon Chung Cc: Peng Fan , Priyanka Jain , Sinan Akman , u-boot@lists.denx.de Subject: Re: [PATCH] mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error Message-ID: <20220506094008.o3whbg3k2okao3dn@pali> References: <20220429182734.4281-1-pali@kernel.org> <9dba491c-e098-0ae8-d757-6aa34b6951e0@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9dba491c-e098-0ae8-d757-6aa34b6951e0@samsung.com> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Friday 06 May 2022 18:32:18 Jaehoon Chung wrote: > On 4/30/22 03:27, Pali Rohár wrote: > > Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until > > flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for > > fixed amount of time like it was before commit 6f883e501b65 ("mmc: > > fsl_esdhc: Add emmc hs200 support"). > > > > This change fixes error 'Internal clock never stabilised.' which is printed > > on P2020 board at every access to SD card. > > > > Fixes: 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support") > > Signed-off-by: Pali Rohár > > Reviewed-by: Jaehoon Chung > > Just add minor question. > > > --- > > drivers/mmc/fsl_esdhc.c | 17 +++++++++++++++++ > > 1 file changed, 17 insertions(+) > > > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > > index fdf2cc290e06..3b3587bd8d72 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -503,6 +503,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) > > u32 time_out; > > u32 value; > > uint clk; > > + u32 hostver; > > > > if (clock < mmc->cfg->f_min) > > clock = mmc->cfg->f_min; > > @@ -543,6 +544,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) > > > > esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); > > > > + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ > > + hostver = esdhc_read32(&priv->esdhc_regs->hostver); > > + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { > > + udelay(10000); > > Is there any reason to use 10000? Hello! I really do not know. This value was there before commit 6f883e501b65. This is probably question for Freescale/NXP people. > Best Regards, > Jaehoon Chung > > > + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); > > + return; > > + } > > + > > time_out = 20; > > value = PRSSTAT_SDSTB; > > while (!(esdhc_read32(®s->prsstat) & value)) { > > @@ -562,6 +571,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) > > struct fsl_esdhc *regs = priv->esdhc_regs; > > u32 value; > > u32 time_out; > > + u32 hostver; > > > > value = esdhc_read32(®s->sysctl); > > > > @@ -572,6 +582,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) > > > > esdhc_write32(®s->sysctl, value); > > > > + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ > > + hostver = esdhc_read32(&priv->esdhc_regs->hostver); > > + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { > > + udelay(10000); > > + return; > > + } > > + > > time_out = 20; > > value = PRSSTAT_SDSTB; > > while (!(esdhc_read32(®s->prsstat) & value)) { >