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* drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'
@ 2022-05-08  2:42 kernel test robot
  0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2022-05-08  2:42 UTC (permalink / raw)
  To: kbuild

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CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
CC: linux-kernel(a)vger.kernel.org
TO: Linus Walleij <linus.walleij@linaro.org>
CC: Stephen Boyd <sboyd@kernel.org>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   30c8e80f79329617012f07b09b70114592092ea4
commit: b14cbdfd467d1e505ad8e03f94e18b3cffc37043 clk: ux500: Add driver for the reset portions of PRCC
date:   6 months ago
:::::: branch date: 9 hours ago
:::::: commit date: 6 months ago
config: arm-randconfig-m031-20220427 (https://download.01.org/0day-ci/archive/20220508/202205081001.wwUGeBwJ-lkp(a)intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'

vim +/rstc +548 drivers/clk/ux500/u8500_of_clk.c

b4bdc81b5b234be Lee Jones     2013-07-22   48  
269f1aac1410d27 Arnd Bergmann 2016-06-20   49  static void u8500_clk_init(struct device_node *np)
82b0f4b7c576d22 Lee Jones     2013-09-17   50  {
82b0f4b7c576d22 Lee Jones     2013-09-17   51  	struct prcmu_fw_version *fw_version;
dec759d8ef01b3e Lee Jones     2013-09-17   52  	struct device_node *child = NULL;
82b0f4b7c576d22 Lee Jones     2013-09-17   53  	const char *sgaclk_parent = NULL;
4e33466095e0455 Lee Jones     2013-09-17   54  	struct clk *clk, *rtc_clk, *twd_clk;
5dc0fe199b35896 Linus Walleij 2015-07-30   55  	u32 bases[CLKRST_MAX];
b14cbdfd467d1e5 Linus Walleij 2021-09-21   56  	struct u8500_prcc_reset *rstc;
5dc0fe199b35896 Linus Walleij 2015-07-30   57  	int i;
82b0f4b7c576d22 Lee Jones     2013-09-17   58  
b14cbdfd467d1e5 Linus Walleij 2021-09-21   59  	/*
b14cbdfd467d1e5 Linus Walleij 2021-09-21   60  	 * We allocate the reset controller here so that we can fill in the
b14cbdfd467d1e5 Linus Walleij 2021-09-21   61  	 * base addresses properly and pass to the reset controller init
b14cbdfd467d1e5 Linus Walleij 2021-09-21   62  	 * function later on.
b14cbdfd467d1e5 Linus Walleij 2021-09-21   63  	 */
b14cbdfd467d1e5 Linus Walleij 2021-09-21   64  	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
b14cbdfd467d1e5 Linus Walleij 2021-09-21   65  	if (!rstc)
b14cbdfd467d1e5 Linus Walleij 2021-09-21   66  		return;
b14cbdfd467d1e5 Linus Walleij 2021-09-21   67  
5dc0fe199b35896 Linus Walleij 2015-07-30   68  	for (i = 0; i < ARRAY_SIZE(bases); i++) {
5dc0fe199b35896 Linus Walleij 2015-07-30   69  		struct resource r;
5dc0fe199b35896 Linus Walleij 2015-07-30   70  
5dc0fe199b35896 Linus Walleij 2015-07-30   71  		if (of_address_to_resource(np, i, &r))
5dc0fe199b35896 Linus Walleij 2015-07-30   72  			/* Not much choice but to continue */
5dc0fe199b35896 Linus Walleij 2015-07-30   73  			pr_err("failed to get CLKRST %d base address\n",
5dc0fe199b35896 Linus Walleij 2015-07-30   74  			       i + 1);
5dc0fe199b35896 Linus Walleij 2015-07-30   75  		bases[i] = r.start;
b14cbdfd467d1e5 Linus Walleij 2021-09-21   76  		rstc->phy_base[i] = r.start;
5dc0fe199b35896 Linus Walleij 2015-07-30   77  	}
dec759d8ef01b3e Lee Jones     2013-09-17   78  
82b0f4b7c576d22 Lee Jones     2013-09-17   79  	/* Clock sources */
82b0f4b7c576d22 Lee Jones     2013-09-17   80  	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01   81  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17   82  	prcmu_clk[PRCMU_PLLSOC0] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17   83  
82b0f4b7c576d22 Lee Jones     2013-09-17   84  	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01   85  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17   86  	prcmu_clk[PRCMU_PLLSOC1] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17   87  
82b0f4b7c576d22 Lee Jones     2013-09-17   88  	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01   89  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17   90  	prcmu_clk[PRCMU_PLLDDR] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17   91  
82b0f4b7c576d22 Lee Jones     2013-09-17   92  	/* FIXME: Add sys, ulp and int clocks here. */
82b0f4b7c576d22 Lee Jones     2013-09-17   93  
d625a730675decc Lee Jones     2013-09-17   94  	rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
66f4ae777d0c2c2 Stephen Boyd  2016-03-01   95  				CLK_IGNORE_UNUSED,
82b0f4b7c576d22 Lee Jones     2013-09-17   96  				32768);
82b0f4b7c576d22 Lee Jones     2013-09-17   97  
82b0f4b7c576d22 Lee Jones     2013-09-17   98  	/* PRCMU clocks */
82b0f4b7c576d22 Lee Jones     2013-09-17   99  	fw_version = prcmu_get_fw_version();
82b0f4b7c576d22 Lee Jones     2013-09-17  100  	if (fw_version != NULL) {
82b0f4b7c576d22 Lee Jones     2013-09-17  101  		switch (fw_version->project) {
82b0f4b7c576d22 Lee Jones     2013-09-17  102  		case PRCMU_FW_PROJECT_U8500_C2:
9050ad816f5205c Linus Walleij 2021-08-02  103  		case PRCMU_FW_PROJECT_U8500_SSG1:
82b0f4b7c576d22 Lee Jones     2013-09-17  104  		case PRCMU_FW_PROJECT_U8520:
82b0f4b7c576d22 Lee Jones     2013-09-17  105  		case PRCMU_FW_PROJECT_U8420:
248fdcc77a35dfe Linus Walleij 2019-12-17  106  		case PRCMU_FW_PROJECT_U8420_SYSCLK:
9050ad816f5205c Linus Walleij 2021-08-02  107  		case PRCMU_FW_PROJECT_U8500_SSG2:
82b0f4b7c576d22 Lee Jones     2013-09-17  108  			sgaclk_parent = "soc0_pll";
82b0f4b7c576d22 Lee Jones     2013-09-17  109  			break;
82b0f4b7c576d22 Lee Jones     2013-09-17  110  		default:
82b0f4b7c576d22 Lee Jones     2013-09-17  111  			break;
82b0f4b7c576d22 Lee Jones     2013-09-17  112  		}
82b0f4b7c576d22 Lee Jones     2013-09-17  113  	}
82b0f4b7c576d22 Lee Jones     2013-09-17  114  
82b0f4b7c576d22 Lee Jones     2013-09-17  115  	if (sgaclk_parent)
82b0f4b7c576d22 Lee Jones     2013-09-17  116  		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
82b0f4b7c576d22 Lee Jones     2013-09-17  117  					PRCMU_SGACLK, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  118  	else
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  119  		clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  120  	prcmu_clk[PRCMU_SGACLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  121  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  122  	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  123  	prcmu_clk[PRCMU_UARTCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  124  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  125  	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  126  	prcmu_clk[PRCMU_MSP02CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  127  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  128  	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  129  	prcmu_clk[PRCMU_MSP1CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  130  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  131  	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  132  	prcmu_clk[PRCMU_I2CCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  133  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  134  	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  135  	prcmu_clk[PRCMU_SLIMCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  136  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  137  	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  138  	prcmu_clk[PRCMU_PER1CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  139  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  140  	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  141  	prcmu_clk[PRCMU_PER2CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  142  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  143  	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  144  	prcmu_clk[PRCMU_PER3CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  145  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  146  	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  147  	prcmu_clk[PRCMU_PER5CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  148  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  149  	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  150  	prcmu_clk[PRCMU_PER6CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  151  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  152  	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  153  	prcmu_clk[PRCMU_PER7CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  154  
82b0f4b7c576d22 Lee Jones     2013-09-17  155  	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  156  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  157  	prcmu_clk[PRCMU_LCDCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  158  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  159  	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  160  	prcmu_clk[PRCMU_BMLCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  161  
82b0f4b7c576d22 Lee Jones     2013-09-17  162  	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  163  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  164  	prcmu_clk[PRCMU_HSITXCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  165  
82b0f4b7c576d22 Lee Jones     2013-09-17  166  	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  167  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  168  	prcmu_clk[PRCMU_HSIRXCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  169  
82b0f4b7c576d22 Lee Jones     2013-09-17  170  	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  171  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  172  	prcmu_clk[PRCMU_HDMICLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  173  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  174  	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  175  	prcmu_clk[PRCMU_APEATCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  176  
a6ae41b54cb0772 Linus Walleij 2015-04-20  177  	clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  178  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  179  	prcmu_clk[PRCMU_APETRACECLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  180  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  181  	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  182  	prcmu_clk[PRCMU_MCDECLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  183  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  184  	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  185  	prcmu_clk[PRCMU_IPI2CCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  186  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  187  	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  188  	prcmu_clk[PRCMU_DSIALTCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  189  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  190  	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  191  	prcmu_clk[PRCMU_DMACLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  192  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  193  	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  194  	prcmu_clk[PRCMU_B2R2CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  195  
82b0f4b7c576d22 Lee Jones     2013-09-17  196  	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  197  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  198  	prcmu_clk[PRCMU_TVCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  199  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  200  	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  201  	prcmu_clk[PRCMU_SSPCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  202  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  203  	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  204  	prcmu_clk[PRCMU_RNGCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  205  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  206  	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  207  	prcmu_clk[PRCMU_UICCCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  208  
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  209  	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  210  	prcmu_clk[PRCMU_TIMCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  211  
689a318c166774f Linus Walleij 2017-01-13  212  	clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
689a318c166774f Linus Walleij 2017-01-13  213  	prcmu_clk[PRCMU_SYSCLK] = clk;
689a318c166774f Linus Walleij 2017-01-13  214  
82b0f4b7c576d22 Lee Jones     2013-09-17  215  	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  216  					100000000, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  217  	prcmu_clk[PRCMU_SDMMCCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  218  
82b0f4b7c576d22 Lee Jones     2013-09-17  219  	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
82b0f4b7c576d22 Lee Jones     2013-09-17  220  				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  221  	prcmu_clk[PRCMU_PLLDSI] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  222  
82b0f4b7c576d22 Lee Jones     2013-09-17  223  	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
82b0f4b7c576d22 Lee Jones     2013-09-17  224  				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  225  	prcmu_clk[PRCMU_DSI0CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  226  
82b0f4b7c576d22 Lee Jones     2013-09-17  227  	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
82b0f4b7c576d22 Lee Jones     2013-09-17  228  				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  229  	prcmu_clk[PRCMU_DSI1CLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  230  
82b0f4b7c576d22 Lee Jones     2013-09-17  231  	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
82b0f4b7c576d22 Lee Jones     2013-09-17  232  				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  233  	prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  234  
82b0f4b7c576d22 Lee Jones     2013-09-17  235  	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
82b0f4b7c576d22 Lee Jones     2013-09-17  236  				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  237  	prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  238  
82b0f4b7c576d22 Lee Jones     2013-09-17  239  	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
82b0f4b7c576d22 Lee Jones     2013-09-17  240  				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c7 Lee Jones     2013-09-17  241  	prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  242  
82b0f4b7c576d22 Lee Jones     2013-09-17  243  	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
66f4ae777d0c2c2 Stephen Boyd  2016-03-01  244  				PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
257015a20c92a41 Lee Jones     2013-09-18  245  	prcmu_clk[PRCMU_ARMSS] = clk;
82b0f4b7c576d22 Lee Jones     2013-09-17  246  
4e33466095e0455 Lee Jones     2013-09-17  247  	twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
82b0f4b7c576d22 Lee Jones     2013-09-17  248  				CLK_IGNORE_UNUSED, 1, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  249  
82b0f4b7c576d22 Lee Jones     2013-09-17  250  	/*
82b0f4b7c576d22 Lee Jones     2013-09-17  251  	 * FIXME: Add special handled PRCMU clocks here:
82b0f4b7c576d22 Lee Jones     2013-09-17  252  	 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
82b0f4b7c576d22 Lee Jones     2013-09-17  253  	 * 2. ab9540_clkout1yuv, see clkout0yuv
82b0f4b7c576d22 Lee Jones     2013-09-17  254  	 */
82b0f4b7c576d22 Lee Jones     2013-09-17  255  
82b0f4b7c576d22 Lee Jones     2013-09-17  256  	/* PRCC P-clocks */
5dc0fe199b35896 Linus Walleij 2015-07-30  257  	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  258  				BIT(0), 0);
2d0803001f0736c Lee Jones     2013-09-17  259  	PRCC_PCLK_STORE(clk, 1, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  260  
5dc0fe199b35896 Linus Walleij 2015-07-30  261  	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  262  				BIT(1), 0);
2d0803001f0736c Lee Jones     2013-09-17  263  	PRCC_PCLK_STORE(clk, 1, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  264  
5dc0fe199b35896 Linus Walleij 2015-07-30  265  	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  266  				BIT(2), 0);
2d0803001f0736c Lee Jones     2013-09-17  267  	PRCC_PCLK_STORE(clk, 1, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  268  
5dc0fe199b35896 Linus Walleij 2015-07-30  269  	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  270  				BIT(3), 0);
2d0803001f0736c Lee Jones     2013-09-17  271  	PRCC_PCLK_STORE(clk, 1, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  272  
5dc0fe199b35896 Linus Walleij 2015-07-30  273  	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  274  				BIT(4), 0);
2d0803001f0736c Lee Jones     2013-09-17  275  	PRCC_PCLK_STORE(clk, 1, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  276  
5dc0fe199b35896 Linus Walleij 2015-07-30  277  	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  278  				BIT(5), 0);
2d0803001f0736c Lee Jones     2013-09-17  279  	PRCC_PCLK_STORE(clk, 1, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  280  
5dc0fe199b35896 Linus Walleij 2015-07-30  281  	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  282  				BIT(6), 0);
2d0803001f0736c Lee Jones     2013-09-17  283  	PRCC_PCLK_STORE(clk, 1, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  284  
5dc0fe199b35896 Linus Walleij 2015-07-30  285  	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  286  				BIT(7), 0);
2d0803001f0736c Lee Jones     2013-09-17  287  	PRCC_PCLK_STORE(clk, 1, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  288  
5dc0fe199b35896 Linus Walleij 2015-07-30  289  	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  290  				BIT(8), 0);
2d0803001f0736c Lee Jones     2013-09-17  291  	PRCC_PCLK_STORE(clk, 1, 8);
82b0f4b7c576d22 Lee Jones     2013-09-17  292  
5dc0fe199b35896 Linus Walleij 2015-07-30  293  	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  294  				BIT(9), 0);
2d0803001f0736c Lee Jones     2013-09-17  295  	PRCC_PCLK_STORE(clk, 1, 9);
82b0f4b7c576d22 Lee Jones     2013-09-17  296  
5dc0fe199b35896 Linus Walleij 2015-07-30  297  	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  298  				BIT(10), 0);
2d0803001f0736c Lee Jones     2013-09-17  299  	PRCC_PCLK_STORE(clk, 1, 10);
82b0f4b7c576d22 Lee Jones     2013-09-17  300  
5dc0fe199b35896 Linus Walleij 2015-07-30  301  	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  302  				BIT(11), 0);
2d0803001f0736c Lee Jones     2013-09-17  303  	PRCC_PCLK_STORE(clk, 1, 11);
82b0f4b7c576d22 Lee Jones     2013-09-17  304  
5dc0fe199b35896 Linus Walleij 2015-07-30  305  	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  306  				BIT(0), 0);
2d0803001f0736c Lee Jones     2013-09-17  307  	PRCC_PCLK_STORE(clk, 2, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  308  
5dc0fe199b35896 Linus Walleij 2015-07-30  309  	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  310  				BIT(1), 0);
2d0803001f0736c Lee Jones     2013-09-17  311  	PRCC_PCLK_STORE(clk, 2, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  312  
5dc0fe199b35896 Linus Walleij 2015-07-30  313  	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  314  				BIT(2), 0);
2d0803001f0736c Lee Jones     2013-09-17  315  	PRCC_PCLK_STORE(clk, 2, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  316  
5dc0fe199b35896 Linus Walleij 2015-07-30  317  	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  318  				BIT(3), 0);
2d0803001f0736c Lee Jones     2013-09-17  319  	PRCC_PCLK_STORE(clk, 2, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  320  
5dc0fe199b35896 Linus Walleij 2015-07-30  321  	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  322  				BIT(4), 0);
2d0803001f0736c Lee Jones     2013-09-17  323  	PRCC_PCLK_STORE(clk, 2, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  324  
5dc0fe199b35896 Linus Walleij 2015-07-30  325  	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  326  				BIT(5), 0);
2d0803001f0736c Lee Jones     2013-09-17  327  	PRCC_PCLK_STORE(clk, 2, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  328  
5dc0fe199b35896 Linus Walleij 2015-07-30  329  	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  330  				BIT(6), 0);
2d0803001f0736c Lee Jones     2013-09-17  331  	PRCC_PCLK_STORE(clk, 2, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  332  
5dc0fe199b35896 Linus Walleij 2015-07-30  333  	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  334  				BIT(7), 0);
2d0803001f0736c Lee Jones     2013-09-17  335  	PRCC_PCLK_STORE(clk, 2, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  336  
5dc0fe199b35896 Linus Walleij 2015-07-30  337  	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  338  				BIT(8), 0);
2d0803001f0736c Lee Jones     2013-09-17  339  	PRCC_PCLK_STORE(clk, 2, 8);
82b0f4b7c576d22 Lee Jones     2013-09-17  340  
5dc0fe199b35896 Linus Walleij 2015-07-30  341  	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  342  				BIT(9), 0);
2d0803001f0736c Lee Jones     2013-09-17  343  	PRCC_PCLK_STORE(clk, 2, 9);
82b0f4b7c576d22 Lee Jones     2013-09-17  344  
5dc0fe199b35896 Linus Walleij 2015-07-30  345  	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  346  				BIT(10), 0);
2d0803001f0736c Lee Jones     2013-09-17  347  	PRCC_PCLK_STORE(clk, 2, 10);
82b0f4b7c576d22 Lee Jones     2013-09-17  348  
5dc0fe199b35896 Linus Walleij 2015-07-30  349  	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  350  				BIT(11), 0);
f5ff9a115ec6338 Linus Walleij 2013-10-18  351  	PRCC_PCLK_STORE(clk, 2, 11);
82b0f4b7c576d22 Lee Jones     2013-09-17  352  
5dc0fe199b35896 Linus Walleij 2015-07-30  353  	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  354  				BIT(12), 0);
2d0803001f0736c Lee Jones     2013-09-17  355  	PRCC_PCLK_STORE(clk, 2, 12);
82b0f4b7c576d22 Lee Jones     2013-09-17  356  
5dc0fe199b35896 Linus Walleij 2015-07-30  357  	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  358  				BIT(0), 0);
2d0803001f0736c Lee Jones     2013-09-17  359  	PRCC_PCLK_STORE(clk, 3, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  360  
5dc0fe199b35896 Linus Walleij 2015-07-30  361  	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  362  				BIT(1), 0);
2d0803001f0736c Lee Jones     2013-09-17  363  	PRCC_PCLK_STORE(clk, 3, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  364  
5dc0fe199b35896 Linus Walleij 2015-07-30  365  	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  366  				BIT(2), 0);
2d0803001f0736c Lee Jones     2013-09-17  367  	PRCC_PCLK_STORE(clk, 3, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  368  
5dc0fe199b35896 Linus Walleij 2015-07-30  369  	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  370  				BIT(3), 0);
2d0803001f0736c Lee Jones     2013-09-17  371  	PRCC_PCLK_STORE(clk, 3, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  372  
5dc0fe199b35896 Linus Walleij 2015-07-30  373  	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  374  				BIT(4), 0);
2d0803001f0736c Lee Jones     2013-09-17  375  	PRCC_PCLK_STORE(clk, 3, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  376  
5dc0fe199b35896 Linus Walleij 2015-07-30  377  	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  378  				BIT(5), 0);
2d0803001f0736c Lee Jones     2013-09-17  379  	PRCC_PCLK_STORE(clk, 3, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  380  
5dc0fe199b35896 Linus Walleij 2015-07-30  381  	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  382  				BIT(6), 0);
2d0803001f0736c Lee Jones     2013-09-17  383  	PRCC_PCLK_STORE(clk, 3, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  384  
5dc0fe199b35896 Linus Walleij 2015-07-30  385  	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  386  				BIT(7), 0);
2d0803001f0736c Lee Jones     2013-09-17  387  	PRCC_PCLK_STORE(clk, 3, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  388  
5dc0fe199b35896 Linus Walleij 2015-07-30  389  	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  390  				BIT(8), 0);
2d0803001f0736c Lee Jones     2013-09-17  391  	PRCC_PCLK_STORE(clk, 3, 8);
82b0f4b7c576d22 Lee Jones     2013-09-17  392  
5dc0fe199b35896 Linus Walleij 2015-07-30  393  	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  394  				BIT(0), 0);
2d0803001f0736c Lee Jones     2013-09-17  395  	PRCC_PCLK_STORE(clk, 5, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  396  
5dc0fe199b35896 Linus Walleij 2015-07-30  397  	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  398  				BIT(1), 0);
2d0803001f0736c Lee Jones     2013-09-17  399  	PRCC_PCLK_STORE(clk, 5, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  400  
5dc0fe199b35896 Linus Walleij 2015-07-30  401  	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  402  				BIT(0), 0);
2d0803001f0736c Lee Jones     2013-09-17  403  	PRCC_PCLK_STORE(clk, 6, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  404  
5dc0fe199b35896 Linus Walleij 2015-07-30  405  	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  406  				BIT(1), 0);
2d0803001f0736c Lee Jones     2013-09-17  407  	PRCC_PCLK_STORE(clk, 6, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  408  
5dc0fe199b35896 Linus Walleij 2015-07-30  409  	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  410  				BIT(2), 0);
2d0803001f0736c Lee Jones     2013-09-17  411  	PRCC_PCLK_STORE(clk, 6, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  412  
5dc0fe199b35896 Linus Walleij 2015-07-30  413  	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  414  				BIT(3), 0);
2d0803001f0736c Lee Jones     2013-09-17  415  	PRCC_PCLK_STORE(clk, 6, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  416  
5dc0fe199b35896 Linus Walleij 2015-07-30  417  	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  418  				BIT(4), 0);
2d0803001f0736c Lee Jones     2013-09-17  419  	PRCC_PCLK_STORE(clk, 6, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  420  
5dc0fe199b35896 Linus Walleij 2015-07-30  421  	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  422  				BIT(5), 0);
2d0803001f0736c Lee Jones     2013-09-17  423  	PRCC_PCLK_STORE(clk, 6, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  424  
5dc0fe199b35896 Linus Walleij 2015-07-30  425  	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  426  				BIT(6), 0);
2d0803001f0736c Lee Jones     2013-09-17  427  	PRCC_PCLK_STORE(clk, 6, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  428  
5dc0fe199b35896 Linus Walleij 2015-07-30  429  	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d22 Lee Jones     2013-09-17  430  				BIT(7), 0);
2d0803001f0736c Lee Jones     2013-09-17  431  	PRCC_PCLK_STORE(clk, 6, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  432  
82b0f4b7c576d22 Lee Jones     2013-09-17  433  	/* PRCC K-clocks
82b0f4b7c576d22 Lee Jones     2013-09-17  434  	 *
82b0f4b7c576d22 Lee Jones     2013-09-17  435  	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
82b0f4b7c576d22 Lee Jones     2013-09-17  436  	 * by enabling just the K-clock, even if it is not a valid parent to
82b0f4b7c576d22 Lee Jones     2013-09-17  437  	 * the K-clock. Until drivers get fixed we might need some kind of
82b0f4b7c576d22 Lee Jones     2013-09-17  438  	 * "parent muxed join".
82b0f4b7c576d22 Lee Jones     2013-09-17  439  	 */
82b0f4b7c576d22 Lee Jones     2013-09-17  440  
82b0f4b7c576d22 Lee Jones     2013-09-17  441  	/* Periph1 */
82b0f4b7c576d22 Lee Jones     2013-09-17  442  	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  443  			bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  444  	PRCC_KCLK_STORE(clk, 1, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  445  
82b0f4b7c576d22 Lee Jones     2013-09-17  446  	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  447  			bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  448  	PRCC_KCLK_STORE(clk, 1, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  449  
82b0f4b7c576d22 Lee Jones     2013-09-17  450  	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  451  			bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  452  	PRCC_KCLK_STORE(clk, 1, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  453  
82b0f4b7c576d22 Lee Jones     2013-09-17  454  	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
5dc0fe199b35896 Linus Walleij 2015-07-30  455  			bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  456  	PRCC_KCLK_STORE(clk, 1, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  457  
82b0f4b7c576d22 Lee Jones     2013-09-17  458  	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
5dc0fe199b35896 Linus Walleij 2015-07-30  459  			bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  460  	PRCC_KCLK_STORE(clk, 1, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  461  
82b0f4b7c576d22 Lee Jones     2013-09-17  462  	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  463  			bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  464  	PRCC_KCLK_STORE(clk, 1, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  465  
82b0f4b7c576d22 Lee Jones     2013-09-17  466  	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  467  			bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  468  	PRCC_KCLK_STORE(clk, 1, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  469  
82b0f4b7c576d22 Lee Jones     2013-09-17  470  	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  471  			bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  472  	PRCC_KCLK_STORE(clk, 1, 8);
82b0f4b7c576d22 Lee Jones     2013-09-17  473  
82b0f4b7c576d22 Lee Jones     2013-09-17  474  	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  475  			bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  476  	PRCC_KCLK_STORE(clk, 1, 9);
82b0f4b7c576d22 Lee Jones     2013-09-17  477  
82b0f4b7c576d22 Lee Jones     2013-09-17  478  	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
5dc0fe199b35896 Linus Walleij 2015-07-30  479  			bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  480  	PRCC_KCLK_STORE(clk, 1, 10);
82b0f4b7c576d22 Lee Jones     2013-09-17  481  
82b0f4b7c576d22 Lee Jones     2013-09-17  482  	/* Periph2 */
82b0f4b7c576d22 Lee Jones     2013-09-17  483  	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  484  			bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  485  	PRCC_KCLK_STORE(clk, 2, 0);
82b0f4b7c576d22 Lee Jones     2013-09-17  486  
82b0f4b7c576d22 Lee Jones     2013-09-17  487  	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  488  			bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  489  	PRCC_KCLK_STORE(clk, 2, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  490  
82b0f4b7c576d22 Lee Jones     2013-09-17  491  	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
5dc0fe199b35896 Linus Walleij 2015-07-30  492  			bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  493  	PRCC_KCLK_STORE(clk, 2, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  494  
82b0f4b7c576d22 Lee Jones     2013-09-17  495  	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  496  			bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  497  	PRCC_KCLK_STORE(clk, 2, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  498  
82b0f4b7c576d22 Lee Jones     2013-09-17  499  	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  500  			bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  501  	PRCC_KCLK_STORE(clk, 2, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  502  
82b0f4b7c576d22 Lee Jones     2013-09-17  503  	/* Note that rate is received from parent. */
82b0f4b7c576d22 Lee Jones     2013-09-17  504  	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  505  			bases[CLKRST2_INDEX], BIT(6),
82b0f4b7c576d22 Lee Jones     2013-09-17  506  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc7 Lee Jones     2013-09-17  507  	PRCC_KCLK_STORE(clk, 2, 6);
89da2dfafc9ffc7 Lee Jones     2013-09-17  508  
82b0f4b7c576d22 Lee Jones     2013-09-17  509  	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  510  			bases[CLKRST2_INDEX], BIT(7),
82b0f4b7c576d22 Lee Jones     2013-09-17  511  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc7 Lee Jones     2013-09-17  512  	PRCC_KCLK_STORE(clk, 2, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  513  
82b0f4b7c576d22 Lee Jones     2013-09-17  514  	/* Periph3 */
82b0f4b7c576d22 Lee Jones     2013-09-17  515  	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  516  			bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  517  	PRCC_KCLK_STORE(clk, 3, 1);
82b0f4b7c576d22 Lee Jones     2013-09-17  518  
82b0f4b7c576d22 Lee Jones     2013-09-17  519  	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  520  			bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  521  	PRCC_KCLK_STORE(clk, 3, 2);
82b0f4b7c576d22 Lee Jones     2013-09-17  522  
82b0f4b7c576d22 Lee Jones     2013-09-17  523  	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  524  			bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  525  	PRCC_KCLK_STORE(clk, 3, 3);
82b0f4b7c576d22 Lee Jones     2013-09-17  526  
82b0f4b7c576d22 Lee Jones     2013-09-17  527  	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  528  			bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  529  	PRCC_KCLK_STORE(clk, 3, 4);
82b0f4b7c576d22 Lee Jones     2013-09-17  530  
82b0f4b7c576d22 Lee Jones     2013-09-17  531  	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
5dc0fe199b35896 Linus Walleij 2015-07-30  532  			bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  533  	PRCC_KCLK_STORE(clk, 3, 5);
82b0f4b7c576d22 Lee Jones     2013-09-17  534  
82b0f4b7c576d22 Lee Jones     2013-09-17  535  	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  536  			bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  537  	PRCC_KCLK_STORE(clk, 3, 6);
82b0f4b7c576d22 Lee Jones     2013-09-17  538  
82b0f4b7c576d22 Lee Jones     2013-09-17  539  	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  540  			bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  541  	PRCC_KCLK_STORE(clk, 3, 7);
82b0f4b7c576d22 Lee Jones     2013-09-17  542  
82b0f4b7c576d22 Lee Jones     2013-09-17  543  	/* Periph6 */
82b0f4b7c576d22 Lee Jones     2013-09-17  544  	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
5dc0fe199b35896 Linus Walleij 2015-07-30  545  			bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc7 Lee Jones     2013-09-17  546  	PRCC_KCLK_STORE(clk, 6, 0);
dec759d8ef01b3e Lee Jones     2013-09-17  547  
dec759d8ef01b3e Lee Jones     2013-09-17 @548  	for_each_child_of_node(np, child) {

:::::: The code at line 548 was first introduced by commit
:::::: dec759d8ef01b3edd5ceb9832ce2338c6c396d11 clk: ux500: Provide u8500_clk with skeleton Device Tree support

:::::: TO: Lee Jones <lee.jones@linaro.org>
:::::: CC: Linus Walleij <linus.walleij@linaro.org>

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 3+ messages in thread

* drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'
@ 2022-09-22  0:50 kernel test robot
  0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2022-09-22  0:50 UTC (permalink / raw)
  To: kbuild

[-- Attachment #1: Type: text/plain, Size: 39934 bytes --]

BCC: lkp(a)intel.com
CC: kbuild-all(a)lists.01.org
CC: linux-kernel(a)vger.kernel.org
TO: Linus Walleij <linus.walleij@linaro.org>
CC: Stephen Boyd <sboyd@kernel.org>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   dc164f4fb00a0abebdfff132f8bc7291a28f5401
commit: b14cbdfd467d1e505ad8e03f94e18b3cffc37043 clk: ux500: Add driver for the reset portions of PRCC
date:   11 months ago
:::::: branch date: 7 hours ago
:::::: commit date: 11 months ago
config: arm-randconfig-m041-20220921
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'

vim +/rstc +548 drivers/clk/ux500/u8500_of_clk.c

b4bdc81b5b234b Lee Jones     2013-07-22   48  
269f1aac1410d2 Arnd Bergmann 2016-06-20   49  static void u8500_clk_init(struct device_node *np)
82b0f4b7c576d2 Lee Jones     2013-09-17   50  {
82b0f4b7c576d2 Lee Jones     2013-09-17   51  	struct prcmu_fw_version *fw_version;
dec759d8ef01b3 Lee Jones     2013-09-17   52  	struct device_node *child = NULL;
82b0f4b7c576d2 Lee Jones     2013-09-17   53  	const char *sgaclk_parent = NULL;
4e33466095e045 Lee Jones     2013-09-17   54  	struct clk *clk, *rtc_clk, *twd_clk;
5dc0fe199b3589 Linus Walleij 2015-07-30   55  	u32 bases[CLKRST_MAX];
b14cbdfd467d1e Linus Walleij 2021-09-21   56  	struct u8500_prcc_reset *rstc;
5dc0fe199b3589 Linus Walleij 2015-07-30   57  	int i;
82b0f4b7c576d2 Lee Jones     2013-09-17   58  
b14cbdfd467d1e Linus Walleij 2021-09-21   59  	/*
b14cbdfd467d1e Linus Walleij 2021-09-21   60  	 * We allocate the reset controller here so that we can fill in the
b14cbdfd467d1e Linus Walleij 2021-09-21   61  	 * base addresses properly and pass to the reset controller init
b14cbdfd467d1e Linus Walleij 2021-09-21   62  	 * function later on.
b14cbdfd467d1e Linus Walleij 2021-09-21   63  	 */
b14cbdfd467d1e Linus Walleij 2021-09-21   64  	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
b14cbdfd467d1e Linus Walleij 2021-09-21   65  	if (!rstc)
b14cbdfd467d1e Linus Walleij 2021-09-21   66  		return;
b14cbdfd467d1e Linus Walleij 2021-09-21   67  
5dc0fe199b3589 Linus Walleij 2015-07-30   68  	for (i = 0; i < ARRAY_SIZE(bases); i++) {
5dc0fe199b3589 Linus Walleij 2015-07-30   69  		struct resource r;
5dc0fe199b3589 Linus Walleij 2015-07-30   70  
5dc0fe199b3589 Linus Walleij 2015-07-30   71  		if (of_address_to_resource(np, i, &r))
5dc0fe199b3589 Linus Walleij 2015-07-30   72  			/* Not much choice but to continue */
5dc0fe199b3589 Linus Walleij 2015-07-30   73  			pr_err("failed to get CLKRST %d base address\n",
5dc0fe199b3589 Linus Walleij 2015-07-30   74  			       i + 1);
5dc0fe199b3589 Linus Walleij 2015-07-30   75  		bases[i] = r.start;
b14cbdfd467d1e Linus Walleij 2021-09-21   76  		rstc->phy_base[i] = r.start;
5dc0fe199b3589 Linus Walleij 2015-07-30   77  	}
dec759d8ef01b3 Lee Jones     2013-09-17   78  
82b0f4b7c576d2 Lee Jones     2013-09-17   79  	/* Clock sources */
82b0f4b7c576d2 Lee Jones     2013-09-17   80  	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
66f4ae777d0c2c Stephen Boyd  2016-03-01   81  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   82  	prcmu_clk[PRCMU_PLLSOC0] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   83  
82b0f4b7c576d2 Lee Jones     2013-09-17   84  	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
66f4ae777d0c2c Stephen Boyd  2016-03-01   85  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   86  	prcmu_clk[PRCMU_PLLSOC1] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   87  
82b0f4b7c576d2 Lee Jones     2013-09-17   88  	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
66f4ae777d0c2c Stephen Boyd  2016-03-01   89  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   90  	prcmu_clk[PRCMU_PLLDDR] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   91  
82b0f4b7c576d2 Lee Jones     2013-09-17   92  	/* FIXME: Add sys, ulp and int clocks here. */
82b0f4b7c576d2 Lee Jones     2013-09-17   93  
d625a730675dec Lee Jones     2013-09-17   94  	rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
66f4ae777d0c2c Stephen Boyd  2016-03-01   95  				CLK_IGNORE_UNUSED,
82b0f4b7c576d2 Lee Jones     2013-09-17   96  				32768);
82b0f4b7c576d2 Lee Jones     2013-09-17   97  
82b0f4b7c576d2 Lee Jones     2013-09-17   98  	/* PRCMU clocks */
82b0f4b7c576d2 Lee Jones     2013-09-17   99  	fw_version = prcmu_get_fw_version();
82b0f4b7c576d2 Lee Jones     2013-09-17  100  	if (fw_version != NULL) {
82b0f4b7c576d2 Lee Jones     2013-09-17  101  		switch (fw_version->project) {
82b0f4b7c576d2 Lee Jones     2013-09-17  102  		case PRCMU_FW_PROJECT_U8500_C2:
9050ad816f5205 Linus Walleij 2021-08-02  103  		case PRCMU_FW_PROJECT_U8500_SSG1:
82b0f4b7c576d2 Lee Jones     2013-09-17  104  		case PRCMU_FW_PROJECT_U8520:
82b0f4b7c576d2 Lee Jones     2013-09-17  105  		case PRCMU_FW_PROJECT_U8420:
248fdcc77a35df Linus Walleij 2019-12-17  106  		case PRCMU_FW_PROJECT_U8420_SYSCLK:
9050ad816f5205 Linus Walleij 2021-08-02  107  		case PRCMU_FW_PROJECT_U8500_SSG2:
82b0f4b7c576d2 Lee Jones     2013-09-17  108  			sgaclk_parent = "soc0_pll";
82b0f4b7c576d2 Lee Jones     2013-09-17  109  			break;
82b0f4b7c576d2 Lee Jones     2013-09-17  110  		default:
82b0f4b7c576d2 Lee Jones     2013-09-17  111  			break;
82b0f4b7c576d2 Lee Jones     2013-09-17  112  		}
82b0f4b7c576d2 Lee Jones     2013-09-17  113  	}
82b0f4b7c576d2 Lee Jones     2013-09-17  114  
82b0f4b7c576d2 Lee Jones     2013-09-17  115  	if (sgaclk_parent)
82b0f4b7c576d2 Lee Jones     2013-09-17  116  		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
82b0f4b7c576d2 Lee Jones     2013-09-17  117  					PRCMU_SGACLK, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  118  	else
66f4ae777d0c2c Stephen Boyd  2016-03-01  119  		clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  120  	prcmu_clk[PRCMU_SGACLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  121  
66f4ae777d0c2c Stephen Boyd  2016-03-01  122  	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  123  	prcmu_clk[PRCMU_UARTCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  124  
66f4ae777d0c2c Stephen Boyd  2016-03-01  125  	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  126  	prcmu_clk[PRCMU_MSP02CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  127  
66f4ae777d0c2c Stephen Boyd  2016-03-01  128  	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  129  	prcmu_clk[PRCMU_MSP1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  130  
66f4ae777d0c2c Stephen Boyd  2016-03-01  131  	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  132  	prcmu_clk[PRCMU_I2CCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  133  
66f4ae777d0c2c Stephen Boyd  2016-03-01  134  	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  135  	prcmu_clk[PRCMU_SLIMCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  136  
66f4ae777d0c2c Stephen Boyd  2016-03-01  137  	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  138  	prcmu_clk[PRCMU_PER1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  139  
66f4ae777d0c2c Stephen Boyd  2016-03-01  140  	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  141  	prcmu_clk[PRCMU_PER2CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  142  
66f4ae777d0c2c Stephen Boyd  2016-03-01  143  	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  144  	prcmu_clk[PRCMU_PER3CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  145  
66f4ae777d0c2c Stephen Boyd  2016-03-01  146  	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  147  	prcmu_clk[PRCMU_PER5CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  148  
66f4ae777d0c2c Stephen Boyd  2016-03-01  149  	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  150  	prcmu_clk[PRCMU_PER6CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  151  
66f4ae777d0c2c Stephen Boyd  2016-03-01  152  	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  153  	prcmu_clk[PRCMU_PER7CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  154  
82b0f4b7c576d2 Lee Jones     2013-09-17  155  	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  156  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  157  	prcmu_clk[PRCMU_LCDCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  158  
66f4ae777d0c2c Stephen Boyd  2016-03-01  159  	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  160  	prcmu_clk[PRCMU_BMLCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  161  
82b0f4b7c576d2 Lee Jones     2013-09-17  162  	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  163  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  164  	prcmu_clk[PRCMU_HSITXCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  165  
82b0f4b7c576d2 Lee Jones     2013-09-17  166  	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  167  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  168  	prcmu_clk[PRCMU_HSIRXCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  169  
82b0f4b7c576d2 Lee Jones     2013-09-17  170  	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  171  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  172  	prcmu_clk[PRCMU_HDMICLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  173  
66f4ae777d0c2c Stephen Boyd  2016-03-01  174  	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  175  	prcmu_clk[PRCMU_APEATCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  176  
a6ae41b54cb077 Linus Walleij 2015-04-20  177  	clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  178  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  179  	prcmu_clk[PRCMU_APETRACECLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  180  
66f4ae777d0c2c Stephen Boyd  2016-03-01  181  	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  182  	prcmu_clk[PRCMU_MCDECLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  183  
66f4ae777d0c2c Stephen Boyd  2016-03-01  184  	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  185  	prcmu_clk[PRCMU_IPI2CCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  186  
66f4ae777d0c2c Stephen Boyd  2016-03-01  187  	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  188  	prcmu_clk[PRCMU_DSIALTCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  189  
66f4ae777d0c2c Stephen Boyd  2016-03-01  190  	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  191  	prcmu_clk[PRCMU_DMACLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  192  
66f4ae777d0c2c Stephen Boyd  2016-03-01  193  	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  194  	prcmu_clk[PRCMU_B2R2CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  195  
82b0f4b7c576d2 Lee Jones     2013-09-17  196  	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  197  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  198  	prcmu_clk[PRCMU_TVCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  199  
66f4ae777d0c2c Stephen Boyd  2016-03-01  200  	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  201  	prcmu_clk[PRCMU_SSPCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  202  
66f4ae777d0c2c Stephen Boyd  2016-03-01  203  	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  204  	prcmu_clk[PRCMU_RNGCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  205  
66f4ae777d0c2c Stephen Boyd  2016-03-01  206  	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  207  	prcmu_clk[PRCMU_UICCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  208  
66f4ae777d0c2c Stephen Boyd  2016-03-01  209  	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  210  	prcmu_clk[PRCMU_TIMCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  211  
689a318c166774 Linus Walleij 2017-01-13  212  	clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
689a318c166774 Linus Walleij 2017-01-13  213  	prcmu_clk[PRCMU_SYSCLK] = clk;
689a318c166774 Linus Walleij 2017-01-13  214  
82b0f4b7c576d2 Lee Jones     2013-09-17  215  	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
66f4ae777d0c2c Stephen Boyd  2016-03-01  216  					100000000, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  217  	prcmu_clk[PRCMU_SDMMCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  218  
82b0f4b7c576d2 Lee Jones     2013-09-17  219  	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  220  				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  221  	prcmu_clk[PRCMU_PLLDSI] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  222  
82b0f4b7c576d2 Lee Jones     2013-09-17  223  	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
82b0f4b7c576d2 Lee Jones     2013-09-17  224  				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  225  	prcmu_clk[PRCMU_DSI0CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  226  
82b0f4b7c576d2 Lee Jones     2013-09-17  227  	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
82b0f4b7c576d2 Lee Jones     2013-09-17  228  				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  229  	prcmu_clk[PRCMU_DSI1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  230  
82b0f4b7c576d2 Lee Jones     2013-09-17  231  	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  232  				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  233  	prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  234  
82b0f4b7c576d2 Lee Jones     2013-09-17  235  	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  236  				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  237  	prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  238  
82b0f4b7c576d2 Lee Jones     2013-09-17  239  	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  240  				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  241  	prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  242  
82b0f4b7c576d2 Lee Jones     2013-09-17  243  	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
66f4ae777d0c2c Stephen Boyd  2016-03-01  244  				PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
257015a20c92a4 Lee Jones     2013-09-18  245  	prcmu_clk[PRCMU_ARMSS] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  246  
4e33466095e045 Lee Jones     2013-09-17  247  	twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
82b0f4b7c576d2 Lee Jones     2013-09-17  248  				CLK_IGNORE_UNUSED, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  249  
82b0f4b7c576d2 Lee Jones     2013-09-17  250  	/*
82b0f4b7c576d2 Lee Jones     2013-09-17  251  	 * FIXME: Add special handled PRCMU clocks here:
82b0f4b7c576d2 Lee Jones     2013-09-17  252  	 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
82b0f4b7c576d2 Lee Jones     2013-09-17  253  	 * 2. ab9540_clkout1yuv, see clkout0yuv
82b0f4b7c576d2 Lee Jones     2013-09-17  254  	 */
82b0f4b7c576d2 Lee Jones     2013-09-17  255  
82b0f4b7c576d2 Lee Jones     2013-09-17  256  	/* PRCC P-clocks */
5dc0fe199b3589 Linus Walleij 2015-07-30  257  	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  258  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  259  	PRCC_PCLK_STORE(clk, 1, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  260  
5dc0fe199b3589 Linus Walleij 2015-07-30  261  	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  262  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  263  	PRCC_PCLK_STORE(clk, 1, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  264  
5dc0fe199b3589 Linus Walleij 2015-07-30  265  	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  266  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  267  	PRCC_PCLK_STORE(clk, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  268  
5dc0fe199b3589 Linus Walleij 2015-07-30  269  	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  270  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  271  	PRCC_PCLK_STORE(clk, 1, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  272  
5dc0fe199b3589 Linus Walleij 2015-07-30  273  	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  274  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  275  	PRCC_PCLK_STORE(clk, 1, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  276  
5dc0fe199b3589 Linus Walleij 2015-07-30  277  	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  278  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  279  	PRCC_PCLK_STORE(clk, 1, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  280  
5dc0fe199b3589 Linus Walleij 2015-07-30  281  	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  282  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  283  	PRCC_PCLK_STORE(clk, 1, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  284  
5dc0fe199b3589 Linus Walleij 2015-07-30  285  	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  286  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  287  	PRCC_PCLK_STORE(clk, 1, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  288  
5dc0fe199b3589 Linus Walleij 2015-07-30  289  	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  290  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  291  	PRCC_PCLK_STORE(clk, 1, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  292  
5dc0fe199b3589 Linus Walleij 2015-07-30  293  	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  294  				BIT(9), 0);
2d0803001f0736 Lee Jones     2013-09-17  295  	PRCC_PCLK_STORE(clk, 1, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  296  
5dc0fe199b3589 Linus Walleij 2015-07-30  297  	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  298  				BIT(10), 0);
2d0803001f0736 Lee Jones     2013-09-17  299  	PRCC_PCLK_STORE(clk, 1, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  300  
5dc0fe199b3589 Linus Walleij 2015-07-30  301  	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  302  				BIT(11), 0);
2d0803001f0736 Lee Jones     2013-09-17  303  	PRCC_PCLK_STORE(clk, 1, 11);
82b0f4b7c576d2 Lee Jones     2013-09-17  304  
5dc0fe199b3589 Linus Walleij 2015-07-30  305  	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  306  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  307  	PRCC_PCLK_STORE(clk, 2, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  308  
5dc0fe199b3589 Linus Walleij 2015-07-30  309  	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  310  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  311  	PRCC_PCLK_STORE(clk, 2, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  312  
5dc0fe199b3589 Linus Walleij 2015-07-30  313  	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  314  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  315  	PRCC_PCLK_STORE(clk, 2, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  316  
5dc0fe199b3589 Linus Walleij 2015-07-30  317  	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  318  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  319  	PRCC_PCLK_STORE(clk, 2, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  320  
5dc0fe199b3589 Linus Walleij 2015-07-30  321  	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  322  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  323  	PRCC_PCLK_STORE(clk, 2, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  324  
5dc0fe199b3589 Linus Walleij 2015-07-30  325  	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  326  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  327  	PRCC_PCLK_STORE(clk, 2, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  328  
5dc0fe199b3589 Linus Walleij 2015-07-30  329  	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  330  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  331  	PRCC_PCLK_STORE(clk, 2, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  332  
5dc0fe199b3589 Linus Walleij 2015-07-30  333  	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  334  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  335  	PRCC_PCLK_STORE(clk, 2, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  336  
5dc0fe199b3589 Linus Walleij 2015-07-30  337  	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  338  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  339  	PRCC_PCLK_STORE(clk, 2, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  340  
5dc0fe199b3589 Linus Walleij 2015-07-30  341  	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  342  				BIT(9), 0);
2d0803001f0736 Lee Jones     2013-09-17  343  	PRCC_PCLK_STORE(clk, 2, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  344  
5dc0fe199b3589 Linus Walleij 2015-07-30  345  	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  346  				BIT(10), 0);
2d0803001f0736 Lee Jones     2013-09-17  347  	PRCC_PCLK_STORE(clk, 2, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  348  
5dc0fe199b3589 Linus Walleij 2015-07-30  349  	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  350  				BIT(11), 0);
f5ff9a115ec633 Linus Walleij 2013-10-18  351  	PRCC_PCLK_STORE(clk, 2, 11);
82b0f4b7c576d2 Lee Jones     2013-09-17  352  
5dc0fe199b3589 Linus Walleij 2015-07-30  353  	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  354  				BIT(12), 0);
2d0803001f0736 Lee Jones     2013-09-17  355  	PRCC_PCLK_STORE(clk, 2, 12);
82b0f4b7c576d2 Lee Jones     2013-09-17  356  
5dc0fe199b3589 Linus Walleij 2015-07-30  357  	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  358  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  359  	PRCC_PCLK_STORE(clk, 3, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  360  
5dc0fe199b3589 Linus Walleij 2015-07-30  361  	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  362  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  363  	PRCC_PCLK_STORE(clk, 3, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  364  
5dc0fe199b3589 Linus Walleij 2015-07-30  365  	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  366  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  367  	PRCC_PCLK_STORE(clk, 3, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  368  
5dc0fe199b3589 Linus Walleij 2015-07-30  369  	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  370  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  371  	PRCC_PCLK_STORE(clk, 3, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  372  
5dc0fe199b3589 Linus Walleij 2015-07-30  373  	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  374  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  375  	PRCC_PCLK_STORE(clk, 3, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  376  
5dc0fe199b3589 Linus Walleij 2015-07-30  377  	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  378  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  379  	PRCC_PCLK_STORE(clk, 3, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  380  
5dc0fe199b3589 Linus Walleij 2015-07-30  381  	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  382  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  383  	PRCC_PCLK_STORE(clk, 3, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  384  
5dc0fe199b3589 Linus Walleij 2015-07-30  385  	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  386  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  387  	PRCC_PCLK_STORE(clk, 3, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  388  
5dc0fe199b3589 Linus Walleij 2015-07-30  389  	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  390  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  391  	PRCC_PCLK_STORE(clk, 3, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  392  
5dc0fe199b3589 Linus Walleij 2015-07-30  393  	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  394  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  395  	PRCC_PCLK_STORE(clk, 5, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  396  
5dc0fe199b3589 Linus Walleij 2015-07-30  397  	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  398  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  399  	PRCC_PCLK_STORE(clk, 5, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  400  
5dc0fe199b3589 Linus Walleij 2015-07-30  401  	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  402  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  403  	PRCC_PCLK_STORE(clk, 6, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  404  
5dc0fe199b3589 Linus Walleij 2015-07-30  405  	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  406  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  407  	PRCC_PCLK_STORE(clk, 6, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  408  
5dc0fe199b3589 Linus Walleij 2015-07-30  409  	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  410  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  411  	PRCC_PCLK_STORE(clk, 6, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  412  
5dc0fe199b3589 Linus Walleij 2015-07-30  413  	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  414  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  415  	PRCC_PCLK_STORE(clk, 6, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  416  
5dc0fe199b3589 Linus Walleij 2015-07-30  417  	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  418  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  419  	PRCC_PCLK_STORE(clk, 6, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  420  
5dc0fe199b3589 Linus Walleij 2015-07-30  421  	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  422  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  423  	PRCC_PCLK_STORE(clk, 6, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  424  
5dc0fe199b3589 Linus Walleij 2015-07-30  425  	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  426  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  427  	PRCC_PCLK_STORE(clk, 6, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  428  
5dc0fe199b3589 Linus Walleij 2015-07-30  429  	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  430  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  431  	PRCC_PCLK_STORE(clk, 6, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  432  
82b0f4b7c576d2 Lee Jones     2013-09-17  433  	/* PRCC K-clocks
82b0f4b7c576d2 Lee Jones     2013-09-17  434  	 *
82b0f4b7c576d2 Lee Jones     2013-09-17  435  	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
82b0f4b7c576d2 Lee Jones     2013-09-17  436  	 * by enabling just the K-clock, even if it is not a valid parent to
82b0f4b7c576d2 Lee Jones     2013-09-17  437  	 * the K-clock. Until drivers get fixed we might need some kind of
82b0f4b7c576d2 Lee Jones     2013-09-17  438  	 * "parent muxed join".
82b0f4b7c576d2 Lee Jones     2013-09-17  439  	 */
82b0f4b7c576d2 Lee Jones     2013-09-17  440  
82b0f4b7c576d2 Lee Jones     2013-09-17  441  	/* Periph1 */
82b0f4b7c576d2 Lee Jones     2013-09-17  442  	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  443  			bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  444  	PRCC_KCLK_STORE(clk, 1, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  445  
82b0f4b7c576d2 Lee Jones     2013-09-17  446  	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  447  			bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  448  	PRCC_KCLK_STORE(clk, 1, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  449  
82b0f4b7c576d2 Lee Jones     2013-09-17  450  	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  451  			bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  452  	PRCC_KCLK_STORE(clk, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  453  
82b0f4b7c576d2 Lee Jones     2013-09-17  454  	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  455  			bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  456  	PRCC_KCLK_STORE(clk, 1, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  457  
82b0f4b7c576d2 Lee Jones     2013-09-17  458  	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  459  			bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  460  	PRCC_KCLK_STORE(clk, 1, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  461  
82b0f4b7c576d2 Lee Jones     2013-09-17  462  	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  463  			bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  464  	PRCC_KCLK_STORE(clk, 1, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  465  
82b0f4b7c576d2 Lee Jones     2013-09-17  466  	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  467  			bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  468  	PRCC_KCLK_STORE(clk, 1, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  469  
82b0f4b7c576d2 Lee Jones     2013-09-17  470  	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  471  			bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  472  	PRCC_KCLK_STORE(clk, 1, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  473  
82b0f4b7c576d2 Lee Jones     2013-09-17  474  	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  475  			bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  476  	PRCC_KCLK_STORE(clk, 1, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  477  
82b0f4b7c576d2 Lee Jones     2013-09-17  478  	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  479  			bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  480  	PRCC_KCLK_STORE(clk, 1, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  481  
82b0f4b7c576d2 Lee Jones     2013-09-17  482  	/* Periph2 */
82b0f4b7c576d2 Lee Jones     2013-09-17  483  	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  484  			bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  485  	PRCC_KCLK_STORE(clk, 2, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  486  
82b0f4b7c576d2 Lee Jones     2013-09-17  487  	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  488  			bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  489  	PRCC_KCLK_STORE(clk, 2, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  490  
82b0f4b7c576d2 Lee Jones     2013-09-17  491  	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  492  			bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  493  	PRCC_KCLK_STORE(clk, 2, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  494  
82b0f4b7c576d2 Lee Jones     2013-09-17  495  	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  496  			bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  497  	PRCC_KCLK_STORE(clk, 2, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  498  
82b0f4b7c576d2 Lee Jones     2013-09-17  499  	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  500  			bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  501  	PRCC_KCLK_STORE(clk, 2, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  502  
82b0f4b7c576d2 Lee Jones     2013-09-17  503  	/* Note that rate is received from parent. */
82b0f4b7c576d2 Lee Jones     2013-09-17  504  	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  505  			bases[CLKRST2_INDEX], BIT(6),
82b0f4b7c576d2 Lee Jones     2013-09-17  506  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc Lee Jones     2013-09-17  507  	PRCC_KCLK_STORE(clk, 2, 6);
89da2dfafc9ffc Lee Jones     2013-09-17  508  
82b0f4b7c576d2 Lee Jones     2013-09-17  509  	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  510  			bases[CLKRST2_INDEX], BIT(7),
82b0f4b7c576d2 Lee Jones     2013-09-17  511  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc Lee Jones     2013-09-17  512  	PRCC_KCLK_STORE(clk, 2, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  513  
82b0f4b7c576d2 Lee Jones     2013-09-17  514  	/* Periph3 */
82b0f4b7c576d2 Lee Jones     2013-09-17  515  	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  516  			bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  517  	PRCC_KCLK_STORE(clk, 3, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  518  
82b0f4b7c576d2 Lee Jones     2013-09-17  519  	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  520  			bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  521  	PRCC_KCLK_STORE(clk, 3, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  522  
82b0f4b7c576d2 Lee Jones     2013-09-17  523  	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  524  			bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  525  	PRCC_KCLK_STORE(clk, 3, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  526  
82b0f4b7c576d2 Lee Jones     2013-09-17  527  	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  528  			bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  529  	PRCC_KCLK_STORE(clk, 3, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  530  
82b0f4b7c576d2 Lee Jones     2013-09-17  531  	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
5dc0fe199b3589 Linus Walleij 2015-07-30  532  			bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  533  	PRCC_KCLK_STORE(clk, 3, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  534  
82b0f4b7c576d2 Lee Jones     2013-09-17  535  	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  536  			bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  537  	PRCC_KCLK_STORE(clk, 3, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  538  
82b0f4b7c576d2 Lee Jones     2013-09-17  539  	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  540  			bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  541  	PRCC_KCLK_STORE(clk, 3, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  542  
82b0f4b7c576d2 Lee Jones     2013-09-17  543  	/* Periph6 */
82b0f4b7c576d2 Lee Jones     2013-09-17  544  	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  545  			bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  546  	PRCC_KCLK_STORE(clk, 6, 0);
dec759d8ef01b3 Lee Jones     2013-09-17  547  
dec759d8ef01b3 Lee Jones     2013-09-17 @548  	for_each_child_of_node(np, child) {

:::::: The code at line 548 was first introduced by commit
:::::: dec759d8ef01b3edd5ceb9832ce2338c6c396d11 clk: ux500: Provide u8500_clk with skeleton Device Tree support

:::::: TO: Lee Jones <lee.jones@linaro.org>
:::::: CC: Linus Walleij <linus.walleij@linaro.org>

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[-- Attachment #2: config.ksh --]
[-- Type: text/plain, Size: 138434 bytes --]

#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.15.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabi-gcc (GCC) 12.1.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120100
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23800
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23800
CONFIG_LLD_VERSION=0
CONFIG_CC_HAS_ASM_GOTO=y
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y

#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_COMPILE_TEST=y
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_BUILD_SALT=""
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
CONFIG_KERNEL_LZO=y
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
# CONFIG_WATCH_QUEUE is not set
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_USELIB is not set
CONFIG_HAVE_ARCH_AUDITSYSCALL=y

#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# end of IRQ subsystem

CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_TIME_KUNIT_TEST=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
# CONFIG_NO_HZ_IDLE is not set
CONFIG_NO_HZ_FULL=y
CONFIG_CONTEXT_TRACKING=y
# CONFIG_CONTEXT_TRACKING_FORCE is not set
# CONFIG_NO_HZ is not set
CONFIG_HIGH_RES_TIMERS=y
# end of Timers subsystem

CONFIG_HAVE_EBPF_JIT=y

#
# BPF subsystem
#
# CONFIG_BPF_SYSCALL is not set
# end of BPF subsystem

# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y

#
# CPU/Task time and stats accounting
#
CONFIG_VIRT_CPU_ACCOUNTING=y
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_PSI=y
# CONFIG_PSI_DEFAULT_DISABLED is not set
# end of CPU/Task time and stats accounting

CONFIG_CPU_ISOLATION=y

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_FANOUT=32
CONFIG_RCU_FANOUT_LEAF=16
# CONFIG_RCU_FAST_NO_HZ is not set
# CONFIG_RCU_BOOST is not set
CONFIG_RCU_NOCB_CPU=y
CONFIG_TASKS_TRACE_RCU_READ_MB=y
# end of RCU Subsystem

CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_IKHEADERS is not set
CONFIG_LOG_BUF_SHIFT=17
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_PRINTK_INDEX=y
CONFIG_GENERIC_SCHED_CLOCK=y

#
# Scheduler features
#
# end of Scheduler features

CONFIG_CGROUPS=y
# CONFIG_MEMCG is not set
# CONFIG_CGROUP_SCHED is not set
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
# CONFIG_CGROUP_PERF is not set
CONFIG_CGROUP_MISC=y
# CONFIG_CGROUP_DEBUG is not set
# CONFIG_NAMESPACES is not set
# CONFIG_CHECKPOINT_RESTORE is not set
# CONFIG_SCHED_AUTOGROUP is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_RD_ZSTD=y
CONFIG_BOOT_CONFIG=y
# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_LD_ORPHAN_WARN=y
CONFIG_HAVE_UID16=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_FHANDLE=y
# CONFIG_POSIX_TIMERS is not set
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
CONFIG_TIMERFD=y
# CONFIG_EVENTFD is not set
CONFIG_SHMEM=y
# CONFIG_AIO is not set
CONFIG_IO_URING=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_USERFAULTFD=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
# CONFIG_RSEQ is not set
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PC104=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters

CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_SLAB_MERGE_DEFAULT is not set
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
CONFIG_SLUB_CPU_PARTIAL=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
# CONFIG_PROFILING is not set
CONFIG_TRACEPOINTS=y
# end of General setup

CONFIG_ARM=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_DMA_USE_IOMMU=y
CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_HAVE_TCM=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_ARCH_HAS_BANDGAP=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_PGTABLE_LEVELS=2

#
# System Type
#
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_BITS_MAX=16
CONFIG_ARCH_MULTIPLATFORM=y
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_OMAP1 is not set

#
# Multiple platform selection
#

#
# CPU Core family selection
#
# CONFIG_ARCH_MULTI_V6 is not set
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_MULTI_V6_V7=y
# end of Multiple platform selection

CONFIG_ARCH_VIRT=y
# CONFIG_ARCH_ACTIONS is not set
CONFIG_ARCH_ALPINE=y
# CONFIG_ARCH_ARTPEC is not set
CONFIG_ARCH_ASPEED=y
CONFIG_MACH_ASPEED_G6=y
# CONFIG_ARCH_AT91 is not set
CONFIG_ARCH_BCM=y

#
# IPROC architected SoCs
#
CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BCM_CYGNUS=y
# CONFIG_ARCH_BCM_HR2 is not set
CONFIG_ARCH_BCM_NSP=y
# CONFIG_ARCH_BCM_5301X is not set

#
# KONA architected SoCs
#
# CONFIG_ARCH_BCM_281XX is not set
# CONFIG_ARCH_BCM_21664 is not set
# CONFIG_ARCH_BCM_23550 is not set

#
# Other Architectures
#
CONFIG_ARCH_BCM2835=y
# CONFIG_ARCH_BCM_53573 is not set
# CONFIG_ARCH_BCM_63XX is not set
# CONFIG_ARCH_BRCMSTB is not set
CONFIG_ARCH_BERLIN=y
# CONFIG_MACH_BERLIN_BG2 is not set
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_MACH_BERLIN_BG2Q=y
CONFIG_ARCH_DIGICOLOR=y
CONFIG_ARCH_EXYNOS=y
CONFIG_S5P_DEV_MFC=y
CONFIG_ARCH_EXYNOS3=y
CONFIG_ARCH_EXYNOS4=y
# CONFIG_ARCH_EXYNOS5 is not set

#
# Exynos SoCs
#
CONFIG_SOC_EXYNOS3250=y
CONFIG_CPU_EXYNOS4210=y
CONFIG_SOC_EXYNOS4412=y
CONFIG_EXYNOS_CPU_SUSPEND=y
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_HISI is not set
CONFIG_ARCH_MXC=y
CONFIG_MXC_TZIC=y
CONFIG_HAVE_IMX_ANATOP=y
CONFIG_HAVE_IMX_GPC=y
CONFIG_HAVE_IMX_MMDC=y
CONFIG_HAVE_IMX_SRC=y

#
# Cortex-A platforms
#
CONFIG_SOC_IMX5=y
# CONFIG_SOC_IMX50 is not set
# CONFIG_SOC_IMX51 is not set
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
# CONFIG_SOC_IMX6SLL is not set
CONFIG_SOC_IMX6SX=y
# CONFIG_SOC_IMX6UL is not set
CONFIG_SOC_LS1021A=y

#
# Cortex-A/Cortex-M asymmetric multiprocessing platforms
#
# CONFIG_SOC_IMX7D is not set
# CONFIG_SOC_IMX7ULP is not set
# CONFIG_SOC_VF610 is not set
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_MACH_MT2701=y
# CONFIG_MACH_MT6589 is not set
CONFIG_MACH_MT6592=y
# CONFIG_MACH_MT7623 is not set
CONFIG_MACH_MT7629=y
# CONFIG_MACH_MT8127 is not set
CONFIG_MACH_MT8135=y
# CONFIG_ARCH_MESON is not set
CONFIG_ARCH_MILBEAUT=y
# CONFIG_ARCH_MILBEAUT_M10V is not set
# CONFIG_ARCH_MMP is not set
CONFIG_ARCH_MSTARV7=y
# CONFIG_MACH_INFINITY is not set
CONFIG_MACH_MERCURY=y
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NPCM is not set
CONFIG_ARCH_OMAP=y

#
# TI OMAP Common Features
#

#
# OMAP Feature Selections
#
CONFIG_POWER_AVS_OMAP=y
CONFIG_POWER_AVS_OMAP_CLASS3=y
# CONFIG_OMAP_RESET_CLOCKS is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE=y
CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID=43
# end of TI OMAP Common Features

CONFIG_MACH_OMAP_GENERIC=y

#
# TI OMAP/AM/DM/DRA Family
#
CONFIG_OMAP_HWMOD=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
# CONFIG_SOC_OMAP5 is not set
# CONFIG_SOC_AM33XX is not set
CONFIG_SOC_AM43XX=y
CONFIG_SOC_DRA7XX=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP_INTERCONNECT_BARRIER=y

#
# TI OMAP2/3/4 Specific Features
#
CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
CONFIG_SOC_HAS_OMAP2_SDRC=y
# CONFIG_SOC_HAS_REALTIME_COUNTER is not set
# CONFIG_SOC_OMAP3430 is not set
CONFIG_SOC_TI81XX=y

#
# OMAP Legacy Platform Data Board Type
#
# CONFIG_OMAP3_SDRC_AC_TIMING is not set
# end of TI OMAP2/3/4 Specific Features

# CONFIG_OMAP5_ERRATA_801819 is not set
# end of TI OMAP/AM/DM/DRA Family

CONFIG_ARCH_QCOM=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MSM8960=y
CONFIG_ARCH_MSM8974=y
CONFIG_ARCH_MDM9615=y
# CONFIG_ARCH_RDA is not set
CONFIG_ARCH_REALTEK=y
CONFIG_ARCH_REALVIEW=y
CONFIG_MACH_REALVIEW_EB=y
# CONFIG_REALVIEW_EB_A9MP is not set
# CONFIG_MACH_REALVIEW_PBA8 is not set
CONFIG_MACH_REALVIEW_PBX=y
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_RENESAS is not set
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_SOCFPGA_SUSPEND=y
CONFIG_PLAT_SPEAR=y
# CONFIG_ARCH_SPEAR13XX is not set
CONFIG_ARCH_STI=y
# CONFIG_SOC_STIH415 is not set
# CONFIG_SOC_STIH416 is not set
CONFIG_SOC_STIH407=y
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_UNIPHIER is not set
CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB8500=y
CONFIG_UX500_DEBUG_UART=2
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_WM8850 is not set
CONFIG_ARCH_ZYNQ=y
CONFIG_PLAT_VERSATILE=y

#
# Processor Type
#
CONFIG_CPU_V7=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y

#
# Processor Features
#
# CONFIG_ARM_LPAE is not set
CONFIG_ARM_THUMB=y
# CONFIG_ARM_THUMBEE is not set
CONFIG_ARM_VIRT_EXT=y
CONFIG_SWP_EMULATE=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y
CONFIG_CPU_BPREDICT_DISABLE=y
CONFIG_CPU_SPECTRE=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
# CONFIG_KUSER_HELPERS is not set
# CONFIG_VDSO is not set
CONFIG_OUTER_CACHE=y
CONFIG_OUTER_CACHE_SYNC=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_CACHE_L2X0_PMU=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_ARM_HEAVY_MB=y
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
CONFIG_ARM_ERRATA_430973=y
# CONFIG_ARM_ERRATA_643719 is not set
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_754327=y
CONFIG_ARM_ERRATA_764369=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_ARM_ERRATA_798181=y
# CONFIG_ARM_ERRATA_773022 is not set
# CONFIG_ARM_ERRATA_818325_852422 is not set
CONFIG_ARM_ERRATA_821420=y
# CONFIG_ARM_ERRATA_825619 is not set
# CONFIG_ARM_ERRATA_857271 is not set
# CONFIG_ARM_ERRATA_852421 is not set
CONFIG_ARM_ERRATA_852423=y
# CONFIG_ARM_ERRATA_857272 is not set
# end of System Type

CONFIG_KRAIT_L2_ACCESSORS=y

#
# Bus support
#
CONFIG_ARM_ERRATA_814220=y
# end of Bus support

#
# Kernel Features
#
CONFIG_HAVE_SMP=y
CONFIG_SMP=y
# CONFIG_SMP_ON_UP is not set
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_HAVE_ARM_TWD=y
# CONFIG_MCPM is not set
# CONFIG_BIG_LITTLE is not set
# CONFIG_VMSPLIT_3G is not set
CONFIG_VMSPLIT_3G_OPT=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xB0000000
CONFIG_NR_CPUS=4
CONFIG_HOTPLUG_CPU=y
CONFIG_ARM_PSCI=y
CONFIG_ARCH_NR_GPIO=2048
CONFIG_HZ_FIXED=0
CONFIG_HZ_100=y
# CONFIG_HZ_200 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_500 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
CONFIG_THUMB2_KERNEL=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_AEABI=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
# CONFIG_CPU_SW_DOMAIN_PAN is not set
CONFIG_HW_PERF_EVENTS=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ARM_MODULE_PLTS=y
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_XEN_DOM0=y
CONFIG_XEN=y
CONFIG_STACKPROTECTOR_PER_TASK=y
# end of Kernel Features

#
# Boot options
#
CONFIG_USE_OF=y
# CONFIG_ATAGS is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y
CONFIG_CMDLINE=""
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y
# CONFIG_EFI is not set
# end of Boot options

#
# CPU Power Management
#

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set

#
# CPU frequency scaling drivers
#
CONFIG_CPUFREQ_DT=m
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_ARM_BRCMSTB_AVS_CPUFREQ=y
CONFIG_ARM_IMX6Q_CPUFREQ=m
# CONFIG_ARM_IMX_CPUFREQ_DT is not set
CONFIG_ARM_MEDIATEK_CPUFREQ=m
# CONFIG_ARM_MEDIATEK_CPUFREQ_HW is not set
CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
CONFIG_ARM_QCOM_CPUFREQ_HW=y
CONFIG_ARM_RASPBERRYPI_CPUFREQ=y
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_SPEAR_CPUFREQ=y
# CONFIG_ARM_STI_CPUFREQ is not set
# CONFIG_ARM_TI_CPUFREQ is not set
# CONFIG_QORIQ_CPUFREQ is not set
# end of CPU Frequency scaling

#
# CPU Idle
#
# CONFIG_CPU_IDLE is not set
CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
# end of CPU Idle
# end of CPU Power Management

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
CONFIG_KERNEL_MODE_NEON=y
# end of Floating point emulation

#
# Power management options
#
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_APM_EMULATION=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_SLEEP=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
# CONFIG_ENERGY_MODEL is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM_CPU_SUSPEND=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# end of Power management options

#
# Firmware Drivers
#

#
# ARM System Control and Management Interface Protocol
#
# CONFIG_ARM_SCMI_PROTOCOL is not set
CONFIG_ARM_SCMI_POWER_DOMAIN=y
# end of ARM System Control and Management Interface Protocol

CONFIG_ARM_SCPI_PROTOCOL=m
CONFIG_ARM_SCPI_POWER_DOMAIN=y
# CONFIG_FIRMWARE_MEMMAP is not set
# CONFIG_FW_CFG_SYSFS is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
# CONFIG_TI_SCI_PROTOCOL is not set
CONFIG_TRUSTED_FOUNDATIONS=y
# CONFIG_TURRIS_MOX_RWTM is not set
# CONFIG_BCM47XX_NVRAM is not set
CONFIG_TEE_BNXT_FW=m
CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_COREBOOT_TABLE=m
# CONFIG_GOOGLE_MEMCONSOLE_COREBOOT is not set
CONFIG_GOOGLE_VPD=m
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
# CONFIG_ARM_SMCCC_SOC_ID is not set

#
# Tegra firmware driver
#
# end of Tegra firmware driver
# end of Firmware Drivers

CONFIG_ARM_CRYPTO=y
CONFIG_CRYPTO_SHA1_ARM=m
CONFIG_CRYPTO_SHA1_ARM_NEON=m
# CONFIG_CRYPTO_SHA1_ARM_CE is not set
CONFIG_CRYPTO_SHA2_ARM_CE=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512_ARM=m
CONFIG_CRYPTO_BLAKE2S_ARM=y
CONFIG_CRYPTO_BLAKE2B_NEON=y
CONFIG_CRYPTO_AES_ARM=m
CONFIG_CRYPTO_AES_ARM_BS=m
CONFIG_CRYPTO_AES_ARM_CE=m
# CONFIG_CRYPTO_GHASH_ARM_CE is not set
CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m
CONFIG_CRYPTO_CRC32_ARM_CE=y
CONFIG_CRYPTO_CHACHA20_NEON=y
# CONFIG_CRYPTO_POLY1305_ARM is not set
# CONFIG_CRYPTO_NHPOLY1305_NEON is not set
CONFIG_CRYPTO_CURVE25519_NEON=y
CONFIG_AS_VFP_VMRS_FPINST=y

#
# General architecture-dependent options
#
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
CONFIG_STATIC_KEYS_SELFTEST=y
CONFIG_UPROBES=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
# CONFIG_SECCOMP is not set
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_LTO_NONE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=8
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OLD_SIGACTION=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
# CONFIG_STRICT_KERNEL_RWX is not set
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_PHYS_TO_DMA=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_HAVE_ARCH_PFN_VALID=y

#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling

CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
CONFIG_GCC_PLUGIN_RANDSTRUCT=y
CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y
# end of General architecture-dependent options

CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULE_SIG_FORMAT=y
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_MODULE_SIG=y
CONFIG_MODULE_SIG_FORCE=y
CONFIG_MODULE_SIG_ALL=y
CONFIG_MODULE_SIG_SHA1=y
# CONFIG_MODULE_SIG_SHA224 is not set
# CONFIG_MODULE_SIG_SHA256 is not set
# CONFIG_MODULE_SIG_SHA384 is not set
# CONFIG_MODULE_SIG_SHA512 is not set
CONFIG_MODULE_SIG_HASH="sha1"
CONFIG_MODULE_COMPRESS_NONE=y
# CONFIG_MODULE_COMPRESS_GZIP is not set
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
CONFIG_MODULES_TREE_LOOKUP=y
# CONFIG_BLOCK is not set
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_FREEZER=y

#
# Executable file formats
#
# CONFIG_BINFMT_ELF is not set
CONFIG_BINFMT_ELF_FDPIC=y
CONFIG_ELFCORE=y
CONFIG_BINFMT_SCRIPT=y
CONFIG_ARCH_HAS_BINFMT_FLAT=y
# CONFIG_BINFMT_FLAT is not set
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_COREDUMP is not set
# end of Executable file formats

#
# Memory Management options
#
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_COMPACTION is not set
# CONFIG_PAGE_REPORTING is not set
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_CLEANCACHE is not set
# CONFIG_CMA is not set
# CONFIG_ZPOOL is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ZONE_DMA=y
# CONFIG_PERCPU_STATS is not set
CONFIG_GUP_TEST=y
CONFIG_KMAP_LOCAL=y

#
# Data Access Monitoring
#
CONFIG_DAMON=y
# CONFIG_DAMON_KUNIT_TEST is not set
# CONFIG_DAMON_VADDR is not set
# end of Data Access Monitoring
# end of Memory Management options

# CONFIG_NET is not set

#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
CONFIG_FORCE_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
# CONFIG_PCIEASPM is not set
CONFIG_PCIE_PTM=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
# CONFIG_PCI_QUIRKS is not set
CONFIG_PCI_DEBUG=y
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
CONFIG_PCI_STUB=m
# CONFIG_PCI_PF_STUB is not set
CONFIG_PCI_ATS=y
CONFIG_PCI_ECAM=y
CONFIG_PCI_BRIDGE_EMUL=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCIE_BUS_TUNE_OFF=y
# CONFIG_PCIE_BUS_DEFAULT is not set
# CONFIG_PCIE_BUS_SAFE is not set
# CONFIG_PCIE_BUS_PERFORMANCE is not set
# CONFIG_PCIE_BUS_PEER2PEER is not set
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
CONFIG_HOTPLUG_PCI_SHPC=y

#
# PCI controller drivers
#
CONFIG_PCI_AARDVARK=m
CONFIG_PCIE_XILINX_NWL=y
# CONFIG_PCI_FTPCI100 is not set
CONFIG_PCI_IXP4XX=y
CONFIG_PCI_TEGRA=y
CONFIG_PCI_RCAR_GEN2=y
# CONFIG_PCIE_RCAR_HOST is not set
CONFIG_PCI_HOST_COMMON=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCIE_XILINX=y
# CONFIG_PCIE_XILINX_CPM is not set
CONFIG_PCI_XGENE=y
# CONFIG_PCI_XGENE_MSI is not set
CONFIG_PCI_V3_SEMI=y
# CONFIG_PCI_VERSATILE is not set
CONFIG_PCIE_IPROC=y
CONFIG_PCIE_IPROC_PLATFORM=y
# CONFIG_PCIE_IPROC_BCMA is not set
CONFIG_PCIE_IPROC_MSI=y
CONFIG_PCIE_ALTERA=y
CONFIG_PCIE_ALTERA_MSI=y
# CONFIG_PCI_HOST_THUNDER_PEM is not set
CONFIG_PCI_HOST_THUNDER_ECAM=y
# CONFIG_PCIE_ROCKCHIP_HOST is not set
CONFIG_PCIE_MEDIATEK=m
CONFIG_PCIE_MEDIATEK_GEN3=y
CONFIG_PCIE_BRCMSTB=y
CONFIG_PCIE_MICROCHIP_HOST=y

#
# DesignWare PCI Core Support
#
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
# CONFIG_PCI_DRA7XX_HOST is not set
CONFIG_PCIE_DW_PLAT=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCI_EXYNOS=m
CONFIG_PCI_IMX6=y
# CONFIG_PCIE_SPEAR13XX is not set
CONFIG_PCI_KEYSTONE=y
CONFIG_PCI_KEYSTONE_HOST=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
# CONFIG_PCIE_QCOM is not set
# CONFIG_PCIE_ARMADA_8K is not set
CONFIG_PCIE_ARTPEC6=y
CONFIG_PCIE_ARTPEC6_HOST=y
# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
# CONFIG_PCIE_INTEL_GW is not set
# CONFIG_PCIE_KEEMBAY_HOST is not set
# CONFIG_PCIE_KIRIN is not set
# CONFIG_PCIE_HISI_STB is not set
CONFIG_PCI_MESON=y
CONFIG_PCIE_TEGRA194=m
CONFIG_PCIE_TEGRA194_HOST=m
# CONFIG_PCIE_VISCONTI_HOST is not set
# CONFIG_PCIE_UNIPHIER is not set
CONFIG_PCIE_AL=y
# CONFIG_PCIE_FU740 is not set
# end of DesignWare PCI Core Support

#
# Mobiveil PCIe Core Support
#
CONFIG_PCIE_MOBIVEIL=y
CONFIG_PCIE_MOBIVEIL_HOST=y
CONFIG_PCIE_MOBIVEIL_PLAT=y
# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set
# end of Mobiveil PCIe Core Support

#
# Cadence PCIe controllers support
#
CONFIG_PCIE_CADENCE=y
CONFIG_PCIE_CADENCE_HOST=y
# CONFIG_PCIE_CADENCE_PLAT_HOST is not set
CONFIG_PCI_J721E=y
CONFIG_PCI_J721E_HOST=y
# end of Cadence PCIe controllers support
# end of PCI controller drivers

#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# end of PCI Endpoint

#
# PCI switch controller drivers
#
CONFIG_PCI_SW_SWITCHTEC=m
# end of PCI switch controller drivers

CONFIG_CXL_BUS=y
CONFIG_CXL_MEM=m
CONFIG_CXL_MEM_RAW_COMMANDS=y
CONFIG_PCCARD=m
# CONFIG_PCMCIA is not set
CONFIG_CARDBUS=y

#
# PC-card bridges
#
CONFIG_YENTA=m
CONFIG_YENTA_O2=y
# CONFIG_YENTA_RICOH is not set
# CONFIG_YENTA_TI is not set
CONFIG_YENTA_TOSHIBA=y
# CONFIG_RAPIDIO is not set

#
# Generic Driver Options
#
# CONFIG_UEVENT_HELPER is not set
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set

#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_FW_LOADER_COMPRESS=y
# CONFIG_FW_CACHE is not set
# end of Firmware loader

CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
CONFIG_DEBUG_DRIVER=y
# CONFIG_DEBUG_DEVRES is not set
CONFIG_DEBUG_TEST_DRIVER_REMOVE=y
CONFIG_PM_QOS_KUNIT_TEST=y
CONFIG_TEST_ASYNC_DRIVER_PROBE=m
# CONFIG_DRIVER_PE_KUNIT_TEST is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SLIMBUS=m
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_W1=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
# end of Generic Driver Options

#
# Bus devices
#
CONFIG_ARM_CCI=y
CONFIG_ARM_CCI400_COMMON=y
CONFIG_ARM_INTEGRATOR_LM=y
# CONFIG_BRCMSTB_GISB_ARB is not set
CONFIG_BT1_APB=y
# CONFIG_BT1_AXI is not set
# CONFIG_HISILICON_LPC is not set
CONFIG_IMX_WEIM=y
CONFIG_INTEL_IXP4XX_EB=y
CONFIG_OMAP_INTERCONNECT=y
CONFIG_OMAP_OCP2SCP=m
CONFIG_QCOM_EBI2=y
CONFIG_SIMPLE_PM_BUS=y
CONFIG_TI_SYSC=y
CONFIG_VEXPRESS_CONFIG=m
CONFIG_FSL_MC_BUS=y
# CONFIG_FSL_MC_UAPI_SUPPORT is not set
# CONFIG_MHI_BUS is not set
# end of Bus devices

# CONFIG_GNSS is not set
# CONFIG_MTD is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
# CONFIG_OF_ALL_DTBS is not set
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_PARPORT=m
# CONFIG_PARPORT_PC is not set
# CONFIG_PARPORT_AX88796 is not set
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y

#
# NVME Support
#
# end of NVME Support

#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
# CONFIG_AD525X_DPOT is not set
CONFIG_DUMMY_IRQ=m
CONFIG_PHANTOM=y
CONFIG_TIFM_CORE=m
# CONFIG_TIFM_7XX1 is not set
# CONFIG_ICS932S401 is not set
CONFIG_ATMEL_SSC=m
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_HI6421V600_IRQ=m
CONFIG_HP_ILO=m
CONFIG_QCOM_COINCELL=m
CONFIG_QCOM_FASTRPC=m
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
CONFIG_ISL29020=y
CONFIG_SENSORS_TSL2550=m
# CONFIG_SENSORS_BH1770 is not set
CONFIG_SENSORS_APDS990X=y
CONFIG_HMC6352=m
CONFIG_DS1682=m
CONFIG_PCH_PHUB=y
CONFIG_SRAM=y
CONFIG_SRAM_EXEC=y
# CONFIG_DW_XDATA_PCIE is not set
CONFIG_PCI_ENDPOINT_TEST=m
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=y
CONFIG_HISI_HIKEY_USB=y
CONFIG_C2PORT=m

#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
CONFIG_EEPROM_LEGACY=m
CONFIG_EEPROM_MAX6875=m
CONFIG_EEPROM_93CX6=y
CONFIG_EEPROM_IDT_89HPESX=m
# CONFIG_EEPROM_EE1004 is not set
# end of EEPROM support

# CONFIG_CB710_CORE is not set

#
# Texas Instruments shared transport line discipline
#
# end of Texas Instruments shared transport line discipline

CONFIG_SENSORS_LIS3_I2C=m
CONFIG_ALTERA_STAPL=y
# CONFIG_ECHO is not set
CONFIG_BCM_VK=y
# CONFIG_MISC_ALCOR_PCI is not set
CONFIG_MISC_RTSX_PCI=m
CONFIG_MISC_RTSX_USB=y
CONFIG_HABANA_AI=m
# CONFIG_UACCE is not set
# CONFIG_PVPANIC is not set
# end of Misc devices

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# end of SCSI device support

CONFIG_HAVE_PATA_PLATFORM=y
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=m
CONFIG_FIREWIRE_OHCI=m
CONFIG_FIREWIRE_NOSY=m
# end of IEEE 1394 (FireWire) support

#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=m
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_SPARSEKMAP=m
CONFIG_INPUT_MATRIXKMAP=y

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=m
CONFIG_INPUT_APMPOWER=m

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ADP5520=m
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_QT1050=m
CONFIG_KEYBOARD_QT1070=m
CONFIG_KEYBOARD_QT2160=m
# CONFIG_KEYBOARD_CLPS711X is not set
CONFIG_KEYBOARD_DLINK_DIR685=y
CONFIG_KEYBOARD_LKKBD=y
CONFIG_KEYBOARD_EP93XX=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
CONFIG_KEYBOARD_LM8333=m
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
CONFIG_KEYBOARD_MPR121=y
CONFIG_KEYBOARD_SNVS_PWRKEY=m
CONFIG_KEYBOARD_IMX=y
CONFIG_KEYBOARD_NEWTON=m
CONFIG_KEYBOARD_NOMADIK=y
CONFIG_KEYBOARD_OPENCORES=m
CONFIG_KEYBOARD_PMIC8XXX=y
CONFIG_KEYBOARD_SAMSUNG=m
CONFIG_KEYBOARD_GOLDFISH_EVENTS=m
CONFIG_KEYBOARD_STOWAWAY=m
# CONFIG_KEYBOARD_ST_KEYSCAN is not set
CONFIG_KEYBOARD_SUNKBD=m
# CONFIG_KEYBOARD_SH_KEYSC is not set
# CONFIG_KEYBOARD_STMPE is not set
CONFIG_KEYBOARD_IQS62X=m
CONFIG_KEYBOARD_OMAP4=y
# CONFIG_KEYBOARD_SPEAR is not set
# CONFIG_KEYBOARD_TC3589X is not set
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
# CONFIG_KEYBOARD_TWL4030 is not set
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=y
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_MTK_PMIC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_USB_ACECAD is not set
CONFIG_TABLET_USB_AIPTEK=y
# CONFIG_TABLET_USB_HANWANG is not set
# CONFIG_TABLET_USB_KBTAB is not set
CONFIG_TABLET_USB_PEGASUS=m
CONFIG_TABLET_SERIAL_WACOM4=y
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_88PM860X_ONKEY is not set
CONFIG_INPUT_88PM80X_ONKEY=m
# CONFIG_INPUT_AB8500_PONKEY is not set
# CONFIG_INPUT_AD714X is not set
CONFIG_INPUT_ATMEL_CAPTOUCH=y
CONFIG_INPUT_BMA150=m
CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_PM8941_PWRKEY=y
CONFIG_INPUT_PM8XXX_VIBRATOR=y
CONFIG_INPUT_PMIC8XXX_PWRKEY=m
# CONFIG_INPUT_MAX77650_ONKEY is not set
CONFIG_INPUT_MC13783_PWRBUTTON=m
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_GPIO_BEEPER is not set
CONFIG_INPUT_GPIO_DECODER=m
CONFIG_INPUT_GPIO_VIBRA=m
# CONFIG_INPUT_ATI_REMOTE2 is not set
CONFIG_INPUT_KEYSPAN_REMOTE=m
# CONFIG_INPUT_KXTJ9 is not set
CONFIG_INPUT_POWERMATE=y
CONFIG_INPUT_YEALINK=y
CONFIG_INPUT_CM109=m
# CONFIG_INPUT_REGULATOR_HAPTIC is not set
# CONFIG_INPUT_RETU_PWRBUTTON is not set
# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
CONFIG_INPUT_AXP20X_PEK=m
# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
# CONFIG_INPUT_TWL4030_VIBRA is not set
CONFIG_INPUT_TWL6040_VIBRA=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
# CONFIG_INPUT_DA7280_HAPTICS is not set
# CONFIG_INPUT_DA9052_ONKEY is not set
# CONFIG_INPUT_DA9063_ONKEY is not set
CONFIG_INPUT_ADXL34X=y
CONFIG_INPUT_ADXL34X_I2C=m
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=m
CONFIG_INPUT_IQS626A=y
# CONFIG_INPUT_CMA3000 is not set
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m
# CONFIG_INPUT_DRV260X_HAPTICS is not set
CONFIG_INPUT_DRV2665_HAPTICS=y
CONFIG_INPUT_DRV2667_HAPTICS=m
# CONFIG_INPUT_HISI_POWERKEY is not set
CONFIG_INPUT_RAVE_SP_PWRBUTTON=m
CONFIG_INPUT_SC27XX_VIBRA=m
# CONFIG_INPUT_STPMIC1_ONKEY is not set
CONFIG_RMI4_CORE=y
CONFIG_RMI4_I2C=m
CONFIG_RMI4_SMB=y
# CONFIG_RMI4_F03 is not set
CONFIG_RMI4_2D_SENSOR=y
# CONFIG_RMI4_F11 is not set
CONFIG_RMI4_F12=y
# CONFIG_RMI4_F30 is not set
CONFIG_RMI4_F34=y
# CONFIG_RMI4_F3A is not set
# CONFIG_RMI4_F55 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_PARKBD=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_PCIPS2=y
CONFIG_SERIO_LIBPS2=m
# CONFIG_SERIO_RAW is not set
CONFIG_SERIO_ALTERA_PS2=y
CONFIG_SERIO_PS2MULT=m
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_SERIO_APBPS2 is not set
CONFIG_SERIO_OLPC_APSP=y
# CONFIG_SERIO_SUN4I_PS2 is not set
# CONFIG_SERIO_GPIO_PS2 is not set
CONFIG_USERIO=y
CONFIG_GAMEPORT=y
CONFIG_GAMEPORT_NS558=y
CONFIG_GAMEPORT_L4=y
CONFIG_GAMEPORT_EMU10K1=m
CONFIG_GAMEPORT_FM801=y
# end of Hardware I/O ports
# end of Input device support

#
# Character devices
#
# CONFIG_TTY is not set
CONFIG_SERIAL_DEV_BUS=m
# CONFIG_PRINTER is not set
# CONFIG_PPDEV is not set
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_PLAT_DATA=y
CONFIG_IPMI_PANIC_EVENT=y
# CONFIG_IPMI_PANIC_STRING is not set
# CONFIG_IPMI_DEVICE_INTERFACE is not set
CONFIG_IPMI_SI=m
CONFIG_IPMI_SSIF=m
CONFIG_IPMI_WATCHDOG=m
# CONFIG_IPMI_POWEROFF is not set
CONFIG_IPMI_KCS_BMC=y
CONFIG_ASPEED_KCS_IPMI_BMC=y
# CONFIG_NPCM7XX_KCS_IPMI_BMC is not set
CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y
CONFIG_IPMI_KCS_BMC_SERIO=y
# CONFIG_ASPEED_BT_IPMI_BMC is not set
CONFIG_IPMB_DEVICE_INTERFACE=m
CONFIG_HW_RANDOM=m
CONFIG_HW_RANDOM_TIMERIOMEM=m
CONFIG_HW_RANDOM_BA431=m
CONFIG_HW_RANDOM_BCM2835=m
CONFIG_HW_RANDOM_IPROC_RNG200=m
CONFIG_HW_RANDOM_IXP4XX=m
CONFIG_HW_RANDOM_OMAP=m
CONFIG_HW_RANDOM_OMAP3_ROM=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_IMX_RNGC=m
CONFIG_HW_RANDOM_ST=m
CONFIG_HW_RANDOM_STM32=m
CONFIG_HW_RANDOM_MESON=m
CONFIG_HW_RANDOM_MTK=m
# CONFIG_HW_RANDOM_EXYNOS is not set
CONFIG_HW_RANDOM_OPTEE=m
CONFIG_HW_RANDOM_NPCM=m
CONFIG_HW_RANDOM_KEYSTONE=m
CONFIG_HW_RANDOM_CCTRNG=m
# CONFIG_HW_RANDOM_XIPHERA is not set
# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set
CONFIG_APPLICOM=m
# CONFIG_DEVMEM is not set
# CONFIG_DEVPORT is not set
CONFIG_TCG_TPM=m
CONFIG_HW_RANDOM_TPM=y
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_ATMEL=m
CONFIG_TCG_TIS_I2C_INFINEON=m
# CONFIG_TCG_TIS_I2C_NUVOTON is not set
# CONFIG_TCG_ATMEL is not set
# CONFIG_TCG_XEN is not set
CONFIG_TCG_VTPM_PROXY=m
CONFIG_TCG_FTPM_TEE=m
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
CONFIG_XILLYBUS_CLASS=m
CONFIG_XILLYBUS=m
# CONFIG_XILLYBUS_PCIE is not set
CONFIG_XILLYBUS_OF=m
CONFIG_XILLYUSB=m
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices

#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_MUX=m

#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
# CONFIG_I2C_MUX_GPMUX is not set
CONFIG_I2C_MUX_LTC4306=m
# CONFIG_I2C_MUX_PCA9541 is not set
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_MUX_REG=m
CONFIG_I2C_DEMUX_PINCTRL=m
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support

CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCA=m

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
CONFIG_I2C_ALI15X3=m
CONFIG_I2C_AMD756=y
# CONFIG_I2C_AMD8111 is not set
CONFIG_I2C_HIX5HD2=m
CONFIG_I2C_I801=y
CONFIG_I2C_ISCH=m
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
CONFIG_I2C_NVIDIA_GPU=y
# CONFIG_I2C_SIS5595 is not set
CONFIG_I2C_SIS630=y
CONFIG_I2C_SIS96X=y
CONFIG_I2C_VIA=y
CONFIG_I2C_VIAPRO=m

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
CONFIG_I2C_ALTERA=y
CONFIG_I2C_ASPEED=y
CONFIG_I2C_AT91=y
CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=y
# CONFIG_I2C_AXXIA is not set
CONFIG_I2C_BCM2835=m
CONFIG_I2C_BCM_IPROC=y
CONFIG_I2C_BCM_KONA=m
CONFIG_I2C_BRCMSTB=m
CONFIG_I2C_CADENCE=y
# CONFIG_I2C_CBUS_GPIO is not set
CONFIG_I2C_DAVINCI=y
CONFIG_I2C_DESIGNWARE_CORE=y
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=m
CONFIG_I2C_DESIGNWARE_PCI=y
# CONFIG_I2C_DIGICOLOR is not set
CONFIG_I2C_EG20T=y
CONFIG_I2C_EMEV2=y
CONFIG_I2C_EXYNOS5=m
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_HIGHLANDER=m
# CONFIG_I2C_HISI is not set
CONFIG_I2C_IMG=m
CONFIG_I2C_IMX=m
CONFIG_I2C_IMX_LPI2C=y
CONFIG_I2C_IOP3XX=m
CONFIG_I2C_JZ4780=m
CONFIG_I2C_LPC2K=m
CONFIG_I2C_MESON=m
CONFIG_I2C_MT65XX=m
CONFIG_I2C_MT7621=m
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_MXS=y
CONFIG_I2C_NOMADIK=y
# CONFIG_I2C_NPCM7XX is not set
CONFIG_I2C_OCORES=y
CONFIG_I2C_OMAP=y
CONFIG_I2C_OWL=m
CONFIG_I2C_PCA_PLATFORM=m
# CONFIG_I2C_PNX is not set
# CONFIG_I2C_PXA is not set
# CONFIG_I2C_QCOM_CCI is not set
# CONFIG_I2C_QCOM_GENI is not set
CONFIG_I2C_QUP=m
CONFIG_I2C_RIIC=y
CONFIG_I2C_RK3X=m
CONFIG_HAVE_S3C2410_I2C=y
CONFIG_I2C_S3C2410=m
# CONFIG_I2C_SH_MOBILE is not set
# CONFIG_I2C_SIMTEC is not set
CONFIG_I2C_SPRD=y
CONFIG_I2C_ST=m
CONFIG_I2C_STM32F4=m
# CONFIG_I2C_STM32F7 is not set
CONFIG_I2C_SUN6I_P2WI=m
# CONFIG_I2C_SYNQUACER is not set
CONFIG_I2C_TEGRA=m
CONFIG_I2C_TEGRA_BPMP=y
# CONFIG_I2C_UNIPHIER is not set
CONFIG_I2C_UNIPHIER_F=y
CONFIG_I2C_VERSATILE=y
CONFIG_I2C_WMT=y
CONFIG_I2C_XILINX=y
# CONFIG_I2C_XLR is not set
# CONFIG_I2C_XLP9XX is not set
# CONFIG_I2C_RCAR is not set

#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
CONFIG_I2C_CP2615=y
# CONFIG_I2C_PARPORT is not set
CONFIG_I2C_ROBOTFUZZ_OSIF=y
CONFIG_I2C_TINY_USB=m

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
CONFIG_I2C_FSI=m
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support

# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
# CONFIG_I2C_SLAVE_EEPROM is not set
# CONFIG_I2C_SLAVE_TESTUNIT is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
CONFIG_I2C_DEBUG_BUS=y
# end of I2C support

# CONFIG_I3C is not set
# CONFIG_SPI is not set
CONFIG_SPMI=y
CONFIG_SPMI_HISI3670=y
CONFIG_SPMI_MSM_PMIC_ARB=m
# CONFIG_HSI is not set
# CONFIG_PPS is not set

#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK_OPTIONAL=y

#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support

CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
CONFIG_DEBUG_PINCTRL=y
# CONFIG_PINCTRL_AS3722 is not set
# CONFIG_PINCTRL_AXP209 is not set
# CONFIG_PINCTRL_AT91PIO4 is not set
CONFIG_PINCTRL_AMD=y
# CONFIG_PINCTRL_BM1880 is not set
CONFIG_PINCTRL_DA850_PUPD=y
CONFIG_PINCTRL_DA9062=y
CONFIG_PINCTRL_DIGICOLOR=y
# CONFIG_PINCTRL_LPC18XX is not set
CONFIG_PINCTRL_MCP23S08_I2C=m
CONFIG_PINCTRL_MCP23S08=m
CONFIG_PINCTRL_ROCKCHIP=y
# CONFIG_PINCTRL_SINGLE is not set
# CONFIG_PINCTRL_SX150X is not set
# CONFIG_PINCTRL_PISTACHIO is not set
CONFIG_PINCTRL_ST=y
CONFIG_PINCTRL_STMFX=m
CONFIG_PINCTRL_ZYNQ=y
# CONFIG_PINCTRL_INGENIC is not set
# CONFIG_PINCTRL_OCELOT is not set
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
# CONFIG_PINCTRL_OWL is not set
CONFIG_PINCTRL_ASPEED=y
CONFIG_PINCTRL_ASPEED_G4=y
CONFIG_PINCTRL_ASPEED_G5=y
CONFIG_PINCTRL_ASPEED_G6=y
CONFIG_PINCTRL_BCM281XX=y
CONFIG_PINCTRL_BCM2835=y
CONFIG_PINCTRL_BCM63XX=y
CONFIG_PINCTRL_BCM6318=y
# CONFIG_PINCTRL_BCM6328 is not set
# CONFIG_PINCTRL_BCM6358 is not set
# CONFIG_PINCTRL_BCM6362 is not set
# CONFIG_PINCTRL_BCM6368 is not set
CONFIG_PINCTRL_BCM63268=y
# CONFIG_PINCTRL_IPROC_GPIO is not set
# CONFIG_PINCTRL_CYGNUS_MUX is not set
CONFIG_PINCTRL_NS=y
# CONFIG_PINCTRL_NSP_GPIO is not set
# CONFIG_PINCTRL_NS2_MUX is not set
CONFIG_PINCTRL_NSP_MUX=y
CONFIG_PINCTRL_BERLIN=y
# CONFIG_PINCTRL_AS370 is not set
CONFIG_PINCTRL_BERLIN_BG2CD=y
CONFIG_PINCTRL_BERLIN_BG2Q=y
# CONFIG_PINCTRL_BERLIN_BG4CT is not set
CONFIG_PINCTRL_IMX=y
CONFIG_PINCTRL_IMX53=y
CONFIG_PINCTRL_IMX6Q=y
CONFIG_PINCTRL_IMX6SL=y
CONFIG_PINCTRL_IMX6SX=y
# CONFIG_PINCTRL_IMX8MM is not set
# CONFIG_PINCTRL_IMX8MN is not set
# CONFIG_PINCTRL_IMX8MP is not set
CONFIG_PINCTRL_IMX8MQ=y
CONFIG_PINCTRL_IMX8ULP=m
CONFIG_PINCTRL_ABX500=y
CONFIG_PINCTRL_AB8500=y
CONFIG_PINCTRL_AB8505=y
CONFIG_PINCTRL_NOMADIK=y
CONFIG_PINCTRL_DB8500=y
CONFIG_PINCTRL_NPCM7XX=y
CONFIG_PINCTRL_PXA=y
CONFIG_PINCTRL_PXA25X=m
CONFIG_PINCTRL_PXA27X=y
CONFIG_PINCTRL_MSM=m
# CONFIG_PINCTRL_APQ8064 is not set
CONFIG_PINCTRL_APQ8084=m
CONFIG_PINCTRL_IPQ4019=m
CONFIG_PINCTRL_IPQ8064=m
# CONFIG_PINCTRL_IPQ8074 is not set
CONFIG_PINCTRL_IPQ6018=m
CONFIG_PINCTRL_MSM8226=m
# CONFIG_PINCTRL_MSM8660 is not set
CONFIG_PINCTRL_MSM8960=m
CONFIG_PINCTRL_MDM9607=m
CONFIG_PINCTRL_MDM9615=m
CONFIG_PINCTRL_MSM8X74=m
CONFIG_PINCTRL_MSM8916=m
# CONFIG_PINCTRL_MSM8953 is not set
CONFIG_PINCTRL_MSM8976=m
CONFIG_PINCTRL_MSM8994=m
CONFIG_PINCTRL_MSM8996=m
CONFIG_PINCTRL_MSM8998=m
CONFIG_PINCTRL_QCS404=m
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
# CONFIG_PINCTRL_SC7180 is not set
CONFIG_PINCTRL_SC7280=m
CONFIG_PINCTRL_SC8180X=m
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SDX55 is not set
CONFIG_PINCTRL_SM6115=m
CONFIG_PINCTRL_SM6125=m
CONFIG_PINCTRL_SM8150=m
CONFIG_PINCTRL_SM8250=m
CONFIG_PINCTRL_SM8350=m
# CONFIG_PINCTRL_LPASS_LPI is not set

#
# Renesas pinctrl drivers
#
# CONFIG_PINCTRL_RENESAS is not set
CONFIG_PINCTRL_SH_PFC=y
CONFIG_PINCTRL_SH_PFC_GPIO=y
CONFIG_PINCTRL_SH_FUNC_GPIO=y
CONFIG_PINCTRL_PFC_EMEV2=y
# CONFIG_PINCTRL_PFC_R8A77995 is not set
CONFIG_PINCTRL_PFC_R8A7794=y
CONFIG_PINCTRL_PFC_R8A77990=y
# CONFIG_PINCTRL_PFC_R8A7779 is not set
CONFIG_PINCTRL_PFC_R8A7790=y
# CONFIG_PINCTRL_PFC_R8A77950 is not set
CONFIG_PINCTRL_PFC_R8A77951=y
CONFIG_PINCTRL_PFC_R8A7778=y
CONFIG_PINCTRL_PFC_R8A7793=y
# CONFIG_PINCTRL_PFC_R8A7791 is not set
# CONFIG_PINCTRL_PFC_R8A77965 is not set
CONFIG_PINCTRL_PFC_R8A77960=y
# CONFIG_PINCTRL_PFC_R8A77961 is not set
CONFIG_PINCTRL_PFC_R8A7792=y
CONFIG_PINCTRL_PFC_R8A77980=y
# CONFIG_PINCTRL_PFC_R8A77970 is not set
CONFIG_PINCTRL_PFC_R8A779A0=y
# CONFIG_PINCTRL_PFC_R8A7740 is not set
CONFIG_PINCTRL_PFC_R8A73A4=y
# CONFIG_PINCTRL_RZA1 is not set
CONFIG_PINCTRL_RZA2=y
CONFIG_PINCTRL_RZG2L=y
CONFIG_PINCTRL_PFC_R8A77470=y
CONFIG_PINCTRL_PFC_R8A7745=y
# CONFIG_PINCTRL_PFC_R8A7742 is not set
# CONFIG_PINCTRL_PFC_R8A7743 is not set
CONFIG_PINCTRL_PFC_R8A7744=y
# CONFIG_PINCTRL_PFC_R8A774C0 is not set
# CONFIG_PINCTRL_PFC_R8A774E1 is not set
# CONFIG_PINCTRL_PFC_R8A774A1 is not set
# CONFIG_PINCTRL_PFC_R8A774B1 is not set
CONFIG_PINCTRL_RZN1=y
CONFIG_PINCTRL_PFC_SH7203=y
CONFIG_PINCTRL_PFC_SH7264=y
CONFIG_PINCTRL_PFC_SH7269=y
CONFIG_PINCTRL_PFC_SH7720=y
CONFIG_PINCTRL_PFC_SH7722=y
CONFIG_PINCTRL_PFC_SH7734=y
CONFIG_PINCTRL_PFC_SH7757=y
CONFIG_PINCTRL_PFC_SH7785=y
# CONFIG_PINCTRL_PFC_SH7786 is not set
# CONFIG_PINCTRL_PFC_SH73A0 is not set
# CONFIG_PINCTRL_PFC_SH7723 is not set
CONFIG_PINCTRL_PFC_SH7724=y
# CONFIG_PINCTRL_PFC_SHX3 is not set
# end of Renesas pinctrl drivers

CONFIG_PINCTRL_SAMSUNG=y
CONFIG_PINCTRL_EXYNOS=y
CONFIG_PINCTRL_EXYNOS_ARM=y
CONFIG_PINCTRL_EXYNOS_ARM64=y
CONFIG_PINCTRL_S3C24XX=y
# CONFIG_PINCTRL_S3C64XX is not set
# CONFIG_PINCTRL_SPRD_SC9860 is not set
CONFIG_PINCTRL_STM32=y
CONFIG_PINCTRL_STM32F429=y
# CONFIG_PINCTRL_STM32F469 is not set
# CONFIG_PINCTRL_STM32F746 is not set
CONFIG_PINCTRL_STM32F769=y
CONFIG_PINCTRL_STM32H743=y
# CONFIG_PINCTRL_STM32MP135 is not set
# CONFIG_PINCTRL_STM32MP157 is not set
CONFIG_PINCTRL_TI_IODELAY=y
# CONFIG_PINCTRL_UNIPHIER is not set

#
# MediaTek pinctrl drivers
#
CONFIG_EINT_MTK=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_PARIS=y
CONFIG_PINCTRL_MT2701=y
# CONFIG_PINCTRL_MT7623 is not set
# CONFIG_PINCTRL_MT7629 is not set
# CONFIG_PINCTRL_MT8135 is not set
CONFIG_PINCTRL_MT8127=y
CONFIG_PINCTRL_MT2712=y
CONFIG_PINCTRL_MT6765=y
CONFIG_PINCTRL_MT6779=m
# CONFIG_PINCTRL_MT6797 is not set
# CONFIG_PINCTRL_MT7622 is not set
CONFIG_PINCTRL_MT8167=y
CONFIG_PINCTRL_MT8173=y
CONFIG_PINCTRL_MT8183=y
CONFIG_PINCTRL_MT8192=y
CONFIG_PINCTRL_MT8195=y
# CONFIG_PINCTRL_MT8365 is not set
# CONFIG_PINCTRL_MT8516 is not set
# CONFIG_PINCTRL_MT6397 is not set
# end of MediaTek pinctrl drivers

CONFIG_PINCTRL_MADERA=m
CONFIG_PINCTRL_CS47L35=y
# CONFIG_PINCTRL_TMPV7700 is not set
CONFIG_PINCTRL_EQUILIBRIUM=m
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_DEBUG_GPIO=y
# CONFIG_GPIO_SYSFS is not set
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_CDEV_V1=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_REGMAP=y
CONFIG_GPIO_MAX730X=m

#
# Memory mapped GPIO drivers
#
# CONFIG_GPIO_74XX_MMIO is not set
CONFIG_GPIO_ALTERA=y
# CONFIG_GPIO_ASPEED is not set
# CONFIG_GPIO_ASPEED_SGPIO is not set
CONFIG_GPIO_ATH79=y
# CONFIG_GPIO_RASPBERRYPI_EXP is not set
CONFIG_GPIO_BCM_KONA=y
# CONFIG_GPIO_BCM_XGS_IPROC is not set
# CONFIG_GPIO_BRCMSTB is not set
CONFIG_GPIO_CADENCE=m
CONFIG_GPIO_CLPS711X=m
CONFIG_GPIO_DAVINCI=y
# CONFIG_GPIO_DWAPB is not set
CONFIG_GPIO_EIC_SPRD=y
# CONFIG_GPIO_EM is not set
# CONFIG_GPIO_FTGPIO010 is not set
CONFIG_GPIO_GENERIC_PLATFORM=m
CONFIG_GPIO_GRGPIO=m
CONFIG_GPIO_HISI=y
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_IOP is not set
# CONFIG_GPIO_LOGICVC is not set
CONFIG_GPIO_LPC18XX=m
# CONFIG_GPIO_LPC32XX is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_MENZ127=y
CONFIG_GPIO_MPC8XXX=y
# CONFIG_GPIO_MT7621 is not set
# CONFIG_GPIO_MXC is not set
CONFIG_GPIO_MXS=y
# CONFIG_GPIO_OMAP is not set
CONFIG_GPIO_PL061=y
# CONFIG_GPIO_PMIC_EIC_SPRD is not set
# CONFIG_GPIO_PXA is not set
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_RDA=y
# CONFIG_GPIO_ROCKCHIP is not set
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
CONFIG_GPIO_SIFIVE=y
# CONFIG_GPIO_SNPS_CREG is not set
# CONFIG_GPIO_SPEAR_SPICS is not set
CONFIG_GPIO_SPRD=m
# CONFIG_GPIO_STP_XWAY is not set
CONFIG_GPIO_SYSCON=y
# CONFIG_GPIO_TEGRA is not set
CONFIG_GPIO_TEGRA186=m
CONFIG_GPIO_TS4800=m
CONFIG_GPIO_UNIPHIER=y
# CONFIG_GPIO_VISCONTI is not set
CONFIG_GPIO_VX855=m
CONFIG_GPIO_WCD934X=m
CONFIG_GPIO_XGENE_SB=y
# CONFIG_GPIO_XILINX is not set
CONFIG_GPIO_XLP=m
CONFIG_GPIO_ZEVIO=y
# CONFIG_GPIO_ZYNQ is not set
CONFIG_GPIO_AMD_FCH=y
CONFIG_GPIO_MSC313=y
CONFIG_GPIO_IDT3243X=m
# end of Memory mapped GPIO drivers

#
# I2C GPIO expanders
#
CONFIG_GPIO_ADP5588=m
# CONFIG_GPIO_ADNP is not set
CONFIG_GPIO_GW_PLD=m
CONFIG_GPIO_MAX7300=m
CONFIG_GPIO_MAX732X=y
# CONFIG_GPIO_MAX732X_IRQ is not set
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
# CONFIG_GPIO_PCA9570 is not set
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=y
CONFIG_GPIO_TS4900=y
# end of I2C GPIO expanders

#
# MFD GPIO expanders
#
CONFIG_GPIO_ADP5520=y
CONFIG_GPIO_ARIZONA=m
# CONFIG_GPIO_BD71815 is not set
CONFIG_GPIO_BD71828=m
CONFIG_GPIO_DA9052=m
# CONFIG_HTC_EGPIO is not set
CONFIG_GPIO_JANZ_TTL=m
CONFIG_GPIO_LP3943=m
# CONFIG_GPIO_LP873X is not set
CONFIG_GPIO_LP87565=m
CONFIG_GPIO_MADERA=m
CONFIG_GPIO_MAX77650=m
# CONFIG_GPIO_RC5T583 is not set
# CONFIG_GPIO_SL28CPLD is not set
# CONFIG_GPIO_STMPE is not set
CONFIG_GPIO_TC3589X=y
CONFIG_GPIO_TPS65086=m
CONFIG_GPIO_TQMX86=m
CONFIG_GPIO_TWL4030=y
# CONFIG_GPIO_TWL6040 is not set
CONFIG_GPIO_WM8350=m
CONFIG_GPIO_WM8994=m
# end of MFD GPIO expanders

#
# PCI GPIO expanders
#
CONFIG_GPIO_AMD8111=y
CONFIG_GPIO_BT8XX=m
CONFIG_GPIO_ML_IOH=m
# CONFIG_GPIO_PCH is not set
CONFIG_GPIO_PCI_IDIO_16=m
CONFIG_GPIO_PCIE_IDIO_24=m
CONFIG_GPIO_RDC321X=m
# end of PCI GPIO expanders

#
# USB GPIO expanders
#
# end of USB GPIO expanders

#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=m
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_VIRTIO=y
# end of Virtual GPIO drivers

CONFIG_W1=y

#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_MATROX=y
# CONFIG_W1_MASTER_DS2490 is not set
CONFIG_W1_MASTER_DS2482=y
CONFIG_W1_MASTER_MXC=m
# CONFIG_W1_MASTER_DS1WM is not set
CONFIG_W1_MASTER_GPIO=m
# CONFIG_HDQ_MASTER_OMAP is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters

#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
# CONFIG_W1_SLAVE_SMEM is not set
CONFIG_W1_SLAVE_DS2405=m
CONFIG_W1_SLAVE_DS2408=y
CONFIG_W1_SLAVE_DS2408_READBACK=y
CONFIG_W1_SLAVE_DS2413=y
CONFIG_W1_SLAVE_DS2406=y
# CONFIG_W1_SLAVE_DS2423 is not set
CONFIG_W1_SLAVE_DS2805=y
# CONFIG_W1_SLAVE_DS2430 is not set
CONFIG_W1_SLAVE_DS2431=m
# CONFIG_W1_SLAVE_DS2433 is not set
CONFIG_W1_SLAVE_DS2438=y
# CONFIG_W1_SLAVE_DS250X is not set
CONFIG_W1_SLAVE_DS2780=m
CONFIG_W1_SLAVE_DS2781=m
CONFIG_W1_SLAVE_DS28E04=y
CONFIG_W1_SLAVE_DS28E17=y
# end of 1-wire Slaves

CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_AS3722=y
# CONFIG_POWER_RESET_BRCMKONA is not set
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GEMINI_POWEROFF is not set
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_POWER_RESET_MSM is not set
# CONFIG_POWER_RESET_QCOM_PON is not set
# CONFIG_POWER_RESET_OCELOT_RESET is not set
# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set
CONFIG_POWER_RESET_LTC2952=y
# CONFIG_POWER_RESET_MT6323 is not set
# CONFIG_POWER_RESET_REGULATOR is not set
# CONFIG_POWER_RESET_RESTART is not set
CONFIG_POWER_RESET_ST=y
CONFIG_POWER_RESET_TPS65086=y
CONFIG_POWER_RESET_VERSATILE=y
# CONFIG_POWER_RESET_KEYSTONE is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_POWER_RESET_RMOBILE=m
# CONFIG_SYSCON_REBOOT_MODE is not set
CONFIG_POWER_RESET_SC27XX=y
# CONFIG_NVMEM_REBOOT_MODE is not set
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
CONFIG_PDA_POWER=m
# CONFIG_APM_POWER is not set
# CONFIG_WM8350_POWER is not set
# CONFIG_TEST_POWER is not set
CONFIG_BATTERY_88PM860X=y
# CONFIG_CHARGER_ADP5061 is not set
# CONFIG_BATTERY_ACT8945A is not set
# CONFIG_BATTERY_CW2015 is not set
# CONFIG_BATTERY_DS2760 is not set
CONFIG_BATTERY_DS2780=m
CONFIG_BATTERY_DS2781=m
CONFIG_BATTERY_DS2782=m
CONFIG_BATTERY_SBS=y
CONFIG_CHARGER_SBS=m
CONFIG_MANAGER_SBS=m
# CONFIG_BATTERY_BQ27XXX is not set
CONFIG_BATTERY_DA9052=m
CONFIG_BATTERY_MAX17040=y
CONFIG_BATTERY_MAX17042=m
CONFIG_BATTERY_MAX1721X=y
# CONFIG_CHARGER_88PM860X is not set
CONFIG_CHARGER_ISP1704=m
CONFIG_CHARGER_MAX8903=y
CONFIG_CHARGER_LP8727=m
CONFIG_CHARGER_GPIO=m
CONFIG_CHARGER_MANAGER=y
CONFIG_CHARGER_LT3651=y
CONFIG_CHARGER_LTC4162L=m
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
CONFIG_CHARGER_MAX77650=m
CONFIG_CHARGER_MT6360=y
# CONFIG_CHARGER_QCOM_SMBB is not set
CONFIG_CHARGER_BQ2415X=y
CONFIG_CHARGER_BQ24190=m
# CONFIG_CHARGER_BQ24257 is not set
# CONFIG_CHARGER_BQ24735 is not set
CONFIG_CHARGER_BQ2515X=y
CONFIG_CHARGER_BQ25890=m
# CONFIG_CHARGER_BQ25980 is not set
CONFIG_CHARGER_BQ256XX=m
CONFIG_CHARGER_SMB347=y
CONFIG_CHARGER_TPS65217=m
CONFIG_BATTERY_GAUGE_LTC2941=m
# CONFIG_BATTERY_GOLDFISH is not set
# CONFIG_BATTERY_RT5033 is not set
# CONFIG_CHARGER_RT9455 is not set
CONFIG_CHARGER_SC2731=y
CONFIG_CHARGER_UCS1002=y
# CONFIG_CHARGER_BD99954 is not set
CONFIG_BATTERY_ACER_A500=m
CONFIG_HWMON=m
CONFIG_HWMON_VID=m
CONFIG_HWMON_DEBUG_CHIP=y

#
# Native drivers
#
CONFIG_SENSORS_AD7414=m
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
# CONFIG_SENSORS_ADM1031 is not set
CONFIG_SENSORS_ADM1177=m
CONFIG_SENSORS_ADM9240=m
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
CONFIG_SENSORS_ADT7470=m
CONFIG_SENSORS_ADT7475=m
# CONFIG_SENSORS_AHT10 is not set
# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
CONFIG_SENSORS_AS370=m
CONFIG_SENSORS_ASC7621=m
CONFIG_SENSORS_AXI_FAN_CONTROL=m
CONFIG_SENSORS_ARM_SCPI=m
# CONFIG_SENSORS_ASPEED is not set
CONFIG_SENSORS_ATXP1=m
CONFIG_SENSORS_BT1_PVT=m
CONFIG_SENSORS_BT1_PVT_ALARMS=y
CONFIG_SENSORS_CORSAIR_CPRO=m
CONFIG_SENSORS_CORSAIR_PSU=m
CONFIG_SENSORS_DS620=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_DA9052_ADC=m
CONFIG_SENSORS_I5K_AMB=m
CONFIG_SENSORS_SPARX5=m
CONFIG_SENSORS_F71805F=m
CONFIG_SENSORS_F71882FG=m
CONFIG_SENSORS_F75375S=m
CONFIG_SENSORS_GSC=m
# CONFIG_SENSORS_MC13783_ADC is not set
CONFIG_SENSORS_FTSTEUTATES=m
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
CONFIG_SENSORS_G760A=m
CONFIG_SENSORS_G762=m
# CONFIG_SENSORS_GPIO_FAN is not set
CONFIG_SENSORS_HIH6130=m
CONFIG_SENSORS_IBMAEM=m
CONFIG_SENSORS_IBMPEX=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_JC42=m
# CONFIG_SENSORS_POWR1220 is not set
CONFIG_SENSORS_LINEAGE=m
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2947_I2C is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC2992 is not set
CONFIG_SENSORS_LTC4151=m
CONFIG_SENSORS_LTC4215=m
CONFIG_SENSORS_LTC4222=m
CONFIG_SENSORS_LTC4245=m
CONFIG_SENSORS_LTC4260=m
CONFIG_SENSORS_LTC4261=m
# CONFIG_SENSORS_MAX127 is not set
# CONFIG_SENSORS_MAX16065 is not set
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_MAX1668=m
CONFIG_SENSORS_MAX197=m
CONFIG_SENSORS_MAX31730=m
# CONFIG_SENSORS_MAX6621 is not set
CONFIG_SENSORS_MAX6639=m
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
CONFIG_SENSORS_MAX6697=m
# CONFIG_SENSORS_MAX31790 is not set
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_MLXREG_FAN=m
# CONFIG_SENSORS_TC654 is not set
CONFIG_SENSORS_TPS23861=m
CONFIG_SENSORS_MENF21BMC_HWMON=m
CONFIG_SENSORS_MR75203=m
# CONFIG_SENSORS_LM63 is not set
CONFIG_SENSORS_LM73=m
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
# CONFIG_SENSORS_LM92 is not set
CONFIG_SENSORS_LM93=m
CONFIG_SENSORS_LM95234=m
CONFIG_SENSORS_LM95241=m
# CONFIG_SENSORS_LM95245 is not set
CONFIG_SENSORS_PC87360=m
CONFIG_SENSORS_PC87427=m
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
CONFIG_SENSORS_NCT6775=m
CONFIG_SENSORS_NCT7802=m
CONFIG_SENSORS_NCT7904=m
CONFIG_SENSORS_NPCM7XX=m
CONFIG_SENSORS_NSA320=m
# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
CONFIG_SENSORS_OCC_P8_I2C=m
CONFIG_SENSORS_OCC_P9_SBE=m
CONFIG_SENSORS_OCC=m
# CONFIG_SENSORS_PCF8591 is not set
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1275=m
CONFIG_SENSORS_BEL_PFE=m
# CONFIG_SENSORS_BPA_RS600 is not set
CONFIG_SENSORS_FSP_3Y=m
CONFIG_SENSORS_IBM_CFFPS=m
# CONFIG_SENSORS_DPS920AB is not set
CONFIG_SENSORS_INSPUR_IPSPS=m
CONFIG_SENSORS_IR35221=m
CONFIG_SENSORS_IR36021=m
CONFIG_SENSORS_IR38064=m
CONFIG_SENSORS_IRPS5401=m
# CONFIG_SENSORS_ISL68137 is not set
# CONFIG_SENSORS_LM25066 is not set
CONFIG_SENSORS_LTC2978=m
# CONFIG_SENSORS_LTC2978_REGULATOR is not set
CONFIG_SENSORS_LTC3815=m
CONFIG_SENSORS_MAX15301=m
CONFIG_SENSORS_MAX16064=m
CONFIG_SENSORS_MAX16601=m
# CONFIG_SENSORS_MAX20730 is not set
CONFIG_SENSORS_MAX20751=m
CONFIG_SENSORS_MAX31785=m
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
CONFIG_SENSORS_MP2888=m
CONFIG_SENSORS_MP2975=m
CONFIG_SENSORS_PIM4328=m
# CONFIG_SENSORS_PM6764TR is not set
CONFIG_SENSORS_PXE1610=m
# CONFIG_SENSORS_Q54SJ108A2 is not set
# CONFIG_SENSORS_STPDDC60 is not set
# CONFIG_SENSORS_TPS40422 is not set
# CONFIG_SENSORS_TPS53679 is not set
# CONFIG_SENSORS_UCD9000 is not set
CONFIG_SENSORS_UCD9200=m
# CONFIG_SENSORS_XDPE122 is not set
CONFIG_SENSORS_ZL6100=m
CONFIG_SENSORS_PWM_FAN=m
CONFIG_SENSORS_RASPBERRYPI_HWMON=m
# CONFIG_SENSORS_SL28CPLD is not set
# CONFIG_SENSORS_SBTSI is not set
# CONFIG_SENSORS_SBRMI is not set
CONFIG_SENSORS_SHT15=m
# CONFIG_SENSORS_SHT21 is not set
CONFIG_SENSORS_SHT3x=m
CONFIG_SENSORS_SHT4x=m
CONFIG_SENSORS_SHTC1=m
# CONFIG_SENSORS_SIS5595 is not set
CONFIG_SENSORS_DME1737=m
# CONFIG_SENSORS_EMC1403 is not set
CONFIG_SENSORS_EMC2103=m
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
CONFIG_SENSORS_SMSC47M192=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_SCH56XX_COMMON=m
CONFIG_SENSORS_SCH5627=m
CONFIG_SENSORS_SCH5636=m
# CONFIG_SENSORS_STTS751 is not set
CONFIG_SENSORS_SMM665=m
CONFIG_SENSORS_ADC128D818=m
CONFIG_SENSORS_ADS7828=m
CONFIG_SENSORS_AMC6821=m
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
CONFIG_SENSORS_TC74=m
CONFIG_SENSORS_THMC50=m
CONFIG_SENSORS_TMP102=m
# CONFIG_SENSORS_TMP103 is not set
CONFIG_SENSORS_TMP108=m
# CONFIG_SENSORS_TMP401 is not set
CONFIG_SENSORS_TMP421=m
CONFIG_SENSORS_TMP513=m
# CONFIG_SENSORS_VEXPRESS is not set
# CONFIG_SENSORS_VIA686A is not set
CONFIG_SENSORS_VT1211=m
# CONFIG_SENSORS_VT8231 is not set
CONFIG_SENSORS_W83773G=m
# CONFIG_SENSORS_W83781D is not set
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83795=m
CONFIG_SENSORS_W83795_FANCTRL=y
CONFIG_SENSORS_W83L785TS=m
CONFIG_SENSORS_W83L786NG=m
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
CONFIG_SENSORS_WM8350=m
CONFIG_THERMAL=y
CONFIG_THERMAL_STATISTICS=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_OF=y
# CONFIG_THERMAL_WRITABLE_TRIPS is not set
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
CONFIG_THERMAL_GOV_FAIR_SHARE=y
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_BANG_BANG=y
# CONFIG_THERMAL_GOV_USER_SPACE is not set
CONFIG_CPU_THERMAL=y
CONFIG_CPU_FREQ_THERMAL=y
# CONFIG_DEVFREQ_THERMAL is not set
# CONFIG_THERMAL_EMULATION is not set
CONFIG_THERMAL_MMIO=y
# CONFIG_HISI_THERMAL is not set
# CONFIG_IMX_THERMAL is not set
CONFIG_IMX8MM_THERMAL=y
# CONFIG_K3_THERMAL is not set
CONFIG_QORIQ_THERMAL=m
# CONFIG_SPEAR_THERMAL is not set
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_RCAR_THERMAL=y
# CONFIG_RCAR_GEN3_THERMAL is not set
CONFIG_KIRKWOOD_THERMAL=y
CONFIG_DOVE_THERMAL=y
# CONFIG_DB8500_THERMAL is not set
# CONFIG_ARMADA_THERMAL is not set
# CONFIG_DA9062_THERMAL is not set
# CONFIG_MTK_THERMAL is not set

#
# Intel thermal drivers
#

#
# ACPI INT340X thermal drivers
#
# end of ACPI INT340X thermal drivers
# end of Intel thermal drivers

#
# Broadcom thermal drivers
#
CONFIG_BCM2711_THERMAL=y
# CONFIG_BCM2835_THERMAL is not set
CONFIG_BRCMSTB_THERMAL=m
CONFIG_BCM_NS_THERMAL=m
CONFIG_BCM_SR_THERMAL=m
# end of Broadcom thermal drivers

#
# Texas Instruments thermal drivers
#
# CONFIG_TI_SOC_THERMAL is not set
# end of Texas Instruments thermal drivers

#
# Samsung thermal drivers
#
CONFIG_EXYNOS_THERMAL=y
# end of Samsung thermal drivers

#
# STMicroelectronics thermal drivers
#
CONFIG_ST_THERMAL=y
# CONFIG_ST_THERMAL_SYSCFG is not set
CONFIG_ST_THERMAL_MEMMAP=y
# end of STMicroelectronics thermal drivers

#
# NVIDIA Tegra thermal drivers
#
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_TEGRA30_TSENSOR=y
# end of NVIDIA Tegra thermal drivers

#
# Qualcomm thermal drivers
#
CONFIG_QCOM_LMH=y
# end of Qualcomm thermal drivers

# CONFIG_UNIPHIER_THERMAL is not set
CONFIG_SPRD_THERMAL=m
CONFIG_KHADAS_MCU_FAN_THERMAL=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
# CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is not set
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
CONFIG_WATCHDOG_SYSFS=y
# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set

#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_BD957XMUF_WATCHDOG=y
CONFIG_DA9052_WATCHDOG=y
CONFIG_DA9055_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=m
CONFIG_DA9062_WATCHDOG=m
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_MENF21BMC_WATCHDOG=y
# CONFIG_MENZ069_WATCHDOG is not set
CONFIG_WM8350_WATCHDOG=y
CONFIG_XILINX_WATCHDOG=m
CONFIG_ZIIRAVE_WATCHDOG=m
# CONFIG_RAVE_SP_WATCHDOG is not set
CONFIG_MLX_WDT=y
# CONFIG_SL28CPLD_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_ARMADA_37XX_WATCHDOG=y
CONFIG_ASM9260_WATCHDOG=y
# CONFIG_AT91RM9200_WATCHDOG is not set
CONFIG_AT91SAM9X_WATCHDOG=m
CONFIG_SAMA5D4_WATCHDOG=y
CONFIG_CADENCE_WATCHDOG=y
# CONFIG_977_WATCHDOG is not set
# CONFIG_FTWDT010_WATCHDOG is not set
CONFIG_S3C2410_WATCHDOG=y
# CONFIG_DW_WATCHDOG is not set
CONFIG_EP93XX_WATCHDOG=m
# CONFIG_OMAP_WATCHDOG is not set
CONFIG_PNX4008_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=y
CONFIG_K3_RTI_WATCHDOG=y
CONFIG_ORION_WATCHDOG=y
CONFIG_RN5T618_WATCHDOG=m
CONFIG_SUNXI_WATCHDOG=y
CONFIG_NPCM7XX_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=m
CONFIG_STMP3XXX_RTC_WATCHDOG=y
# CONFIG_TS4800_WATCHDOG is not set
# CONFIG_TS72XX_WATCHDOG is not set
CONFIG_MAX63XX_WATCHDOG=y
CONFIG_MAX77620_WATCHDOG=y
# CONFIG_IMX2_WDT is not set
# CONFIG_IMX7ULP_WDT is not set
CONFIG_UX500_WATCHDOG=y
# CONFIG_RETU_WATCHDOG is not set
CONFIG_MOXART_WDT=y
# CONFIG_ST_LPC_WATCHDOG is not set
CONFIG_TEGRA_WATCHDOG=m
# CONFIG_QCOM_WDT is not set
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=y
# CONFIG_MEDIATEK_WATCHDOG is not set
# CONFIG_DIGICOLOR_WATCHDOG is not set
CONFIG_ARM_SMC_WATCHDOG=y
# CONFIG_LPC18XX_WATCHDOG is not set
# CONFIG_RENESAS_WDT is not set
# CONFIG_RENESAS_RZAWDT is not set
CONFIG_ASPEED_WATCHDOG=y
# CONFIG_STPMIC1_WATCHDOG is not set
# CONFIG_UNIPHIER_WATCHDOG is not set
# CONFIG_RTD119X_WATCHDOG is not set
# CONFIG_SPRD_WATCHDOG is not set
CONFIG_PM8916_WATCHDOG=m
CONFIG_VISCONTI_WATCHDOG=m
CONFIG_MSC313E_WATCHDOG=m
CONFIG_ALIM7101_WDT=y
CONFIG_SC520_WDT=m
CONFIG_I6300ESB_WDT=y
# CONFIG_RDC321X_WDT is not set
# CONFIG_ATH79_WDT is not set
CONFIG_BCM47XX_WDT=y
CONFIG_BCM2835_WDT=m
CONFIG_BCM_KONA_WDT=y
CONFIG_BCM_KONA_WDT_DEBUG=y
CONFIG_BCM7038_WDT=y
CONFIG_IMGPDC_WDT=m
# CONFIG_MPC5200_WDT is not set
CONFIG_MEN_A21_WDT=m
# CONFIG_XEN_WDT is not set
CONFIG_UML_WATCHDOG=m

#
# PCI-based Watchdog Cards
#
CONFIG_PCIPCWATCHDOG=y
CONFIG_WDTPCI=y

#
# USB-based Watchdog Cards
#
CONFIG_USBPCWATCHDOG=y
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=y
CONFIG_BCMA_HOST_PCI_POSSIBLE=y
CONFIG_BCMA_HOST_PCI=y
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_PCI=y
CONFIG_BCMA_DRIVER_MIPS=y
CONFIG_BCMA_PFLASH=y
# CONFIG_BCMA_SFLASH is not set
CONFIG_BCMA_NFLASH=y
CONFIG_BCMA_DRIVER_GMAC_CMN=y
# CONFIG_BCMA_DRIVER_GPIO is not set
# CONFIG_BCMA_DEBUG is not set

#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_ALTERA_SYSMGR=y
# CONFIG_MFD_ACT8945A is not set
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
CONFIG_MFD_AS3722=y
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_AT91_USART is not set
CONFIG_MFD_ATMEL_FLEXCOM=y
CONFIG_MFD_ATMEL_HLCDC=y
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
CONFIG_MFD_AXP20X=m
CONFIG_MFD_AXP20X_I2C=m
CONFIG_MFD_MADERA=m
# CONFIG_MFD_MADERA_I2C is not set
# CONFIG_MFD_CS47L15 is not set
CONFIG_MFD_CS47L35=y
# CONFIG_MFD_CS47L85 is not set
# CONFIG_MFD_CS47L90 is not set
# CONFIG_MFD_CS47L92 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_PMIC_DA903X is not set
CONFIG_PMIC_DA9052=y
CONFIG_MFD_DA9052_I2C=y
# CONFIG_MFD_DA9055 is not set
CONFIG_MFD_DA9062=y
CONFIG_MFD_DA9063=m
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
CONFIG_MFD_ENE_KB3930=m
CONFIG_MFD_EXYNOS_LPASS=y
CONFIG_MFD_GATEWORKS_GSC=y
CONFIG_MFD_MC13XXX=m
CONFIG_MFD_MC13XXX_I2C=m
CONFIG_MFD_MP2629=y
CONFIG_MFD_MXS_LRADC=y
CONFIG_MFD_MX25_TSADC=y
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_HI6421_SPMI=y
CONFIG_MFD_HI655X_PMIC=m
CONFIG_HTC_PASIC3=m
CONFIG_HTC_I2CPLD=y
CONFIG_LPC_ICH=m
CONFIG_LPC_SCH=m
# CONFIG_MFD_INTEL_PMT is not set
CONFIG_MFD_IQS62X=m
CONFIG_MFD_JANZ_CMODIO=y
# CONFIG_MFD_KEMPLD is not set
CONFIG_MFD_88PM800=m
CONFIG_MFD_88PM805=y
CONFIG_MFD_88PM860X=y
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77620 is not set
CONFIG_MFD_MAX77650=y
CONFIG_MFD_MAX77686=m
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
CONFIG_MFD_MAX8997=y
# CONFIG_MFD_MAX8998 is not set
CONFIG_MFD_MT6360=y
CONFIG_MFD_MT6397=m
CONFIG_MFD_MENF21BMC=m
# CONFIG_MFD_VIPERBOARD is not set
CONFIG_MFD_NTXEC=y
CONFIG_MFD_RETU=y
# CONFIG_MFD_PCF50633 is not set
CONFIG_MFD_PM8XXX=y
CONFIG_MFD_QCOM_RPM=y
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_RDC321X=m
CONFIG_MFD_RT4831=m
# CONFIG_MFD_RT5033 is not set
CONFIG_MFD_RC5T583=y
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
CONFIG_MFD_SEC_CORE=y
# CONFIG_MFD_SI476X_CORE is not set
CONFIG_MFD_SIMPLE_MFD_I2C=m
CONFIG_MFD_SL28CPLD=m
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
CONFIG_ABX500_CORE=y
CONFIG_AB8500_CORE=y
CONFIG_MFD_DB8500_PRCMU=y
CONFIG_MFD_STMPE=y

#
# STMicroelectronics STMPE Interface Drivers
#
# CONFIG_STMPE_I2C is not set
# end of STMicroelectronics STMPE Interface Drivers

CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=y
CONFIG_MFD_LP3943=m
# CONFIG_MFD_LP8788 is not set
CONFIG_MFD_TI_LMU=m
# CONFIG_MFD_OMAP_USB_HOST is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
CONFIG_TPS65010=y
CONFIG_TPS6507X=y
CONFIG_MFD_TPS65086=m
# CONFIG_MFD_TPS65090 is not set
CONFIG_MFD_TPS65217=y
CONFIG_MFD_TI_LP873X=m
CONFIG_MFD_TI_LP87565=y
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS80031 is not set
CONFIG_TWL4030_CORE=y
CONFIG_TWL4030_POWER=y
# CONFIG_MFD_TWL4030_AUDIO is not set
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TIMBERDALE is not set
CONFIG_MFD_TC3589X=y
CONFIG_MFD_TMIO=y
CONFIG_MFD_T7L66XB=y
CONFIG_MFD_TC6387XB=y
# CONFIG_MFD_TC6393XB is not set
CONFIG_MFD_TQMX86=m
CONFIG_MFD_VX855=y
# CONFIG_MFD_LOCHNAGAR is not set
CONFIG_MFD_ARIZONA=m
CONFIG_MFD_ARIZONA_I2C=m
CONFIG_MFD_CS47L24=y
# CONFIG_MFD_WM5102 is not set
CONFIG_MFD_WM5110=y
CONFIG_MFD_WM8997=y
CONFIG_MFD_WM8998=y
CONFIG_MFD_WM8400=y
# CONFIG_MFD_WM831X_I2C is not set
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=m
# CONFIG_MFD_STW481X is not set
CONFIG_MFD_ROHM_BD718XX=y
# CONFIG_MFD_ROHM_BD70528 is not set
CONFIG_MFD_ROHM_BD71828=m
CONFIG_MFD_ROHM_BD957XMUF=y
CONFIG_MFD_STM32_LPTIMER=m
# CONFIG_MFD_STM32_TIMERS is not set
CONFIG_MFD_STPMIC1=m
CONFIG_MFD_STMFX=m
CONFIG_MFD_WCD934X=m
# CONFIG_MFD_ATC260X_I2C is not set
CONFIG_MFD_KHADAS_MCU=m
CONFIG_MFD_ACER_A500_EC=m
# CONFIG_MFD_QCOM_PM8008 is not set
CONFIG_MFD_VEXPRESS_SYSREG=m
CONFIG_RAVE_SP_CORE=m
# CONFIG_MFD_RSMU_I2C is not set
# end of Multifunction device drivers

CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
CONFIG_REGULATOR_USERSPACE_CONSUMER=y
# CONFIG_REGULATOR_88PG86X is not set
CONFIG_REGULATOR_88PM800=m
CONFIG_REGULATOR_88PM8607=y
# CONFIG_REGULATOR_ACT8865 is not set
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ANATOP=m
CONFIG_REGULATOR_AB8500=y
CONFIG_REGULATOR_AS3722=m
CONFIG_REGULATOR_AXP20X=m
CONFIG_REGULATOR_BD71815=m
CONFIG_REGULATOR_BD71828=m
# CONFIG_REGULATOR_BD718XX is not set
CONFIG_REGULATOR_BD957XMUF=y
# CONFIG_REGULATOR_DA9052 is not set
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_DA9063=m
CONFIG_REGULATOR_DA9121=m
# CONFIG_REGULATOR_DA9210 is not set
# CONFIG_REGULATOR_DA9211 is not set
CONFIG_REGULATOR_DBX500_PRCMU=y
CONFIG_REGULATOR_DB8500_PRCMU=y
CONFIG_REGULATOR_FAN53555=m
CONFIG_REGULATOR_FAN53880=y
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_HI6421 is not set
CONFIG_REGULATOR_HI6421V530=y
CONFIG_REGULATOR_HI655X=m
# CONFIG_REGULATOR_HI6421V600 is not set
CONFIG_REGULATOR_ISL9305=y
# CONFIG_REGULATOR_ISL6271A is not set
CONFIG_REGULATOR_LM363X=m
CONFIG_REGULATOR_LP3971=m
CONFIG_REGULATOR_LP3972=y
# CONFIG_REGULATOR_LP872X is not set
CONFIG_REGULATOR_LP873X=m
CONFIG_REGULATOR_LP8755=y
CONFIG_REGULATOR_LP87565=y
CONFIG_REGULATOR_LTC3589=y
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX1586=m
# CONFIG_REGULATOR_MAX77620 is not set
CONFIG_REGULATOR_MAX77650=m
CONFIG_REGULATOR_MAX8649=y
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8893 is not set
CONFIG_REGULATOR_MAX8907=m
# CONFIG_REGULATOR_MAX8952 is not set
CONFIG_REGULATOR_MAX8973=y
# CONFIG_REGULATOR_MAX8997 is not set
CONFIG_REGULATOR_MAX77686=m
CONFIG_REGULATOR_MAX77693=m
CONFIG_REGULATOR_MAX77802=y
CONFIG_REGULATOR_MAX77826=y
CONFIG_REGULATOR_MC13XXX_CORE=m
CONFIG_REGULATOR_MC13783=m
# CONFIG_REGULATOR_MC13892 is not set
CONFIG_REGULATOR_MCP16502=y
CONFIG_REGULATOR_MP5416=y
CONFIG_REGULATOR_MP8859=y
CONFIG_REGULATOR_MP886X=m
# CONFIG_REGULATOR_MPQ7920 is not set
CONFIG_REGULATOR_MT6311=y
CONFIG_REGULATOR_MT6315=m
# CONFIG_REGULATOR_MT6323 is not set
# CONFIG_REGULATOR_MT6358 is not set
# CONFIG_REGULATOR_MT6359 is not set
CONFIG_REGULATOR_MT6360=m
CONFIG_REGULATOR_MT6380=m
# CONFIG_REGULATOR_MT6397 is not set
CONFIG_REGULATOR_PBIAS=m
# CONFIG_REGULATOR_PCA9450 is not set
# CONFIG_REGULATOR_PF8X00 is not set
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=m
CONFIG_REGULATOR_PV88080=y
CONFIG_REGULATOR_PV88090=m
# CONFIG_REGULATOR_QCOM_RPM is not set
CONFIG_REGULATOR_QCOM_RPMH=m
CONFIG_REGULATOR_QCOM_SPMI=m
CONFIG_REGULATOR_QCOM_USB_VBUS=m
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RC5T583=m
CONFIG_REGULATOR_ROHM=m
CONFIG_REGULATOR_RT4801=y
CONFIG_REGULATOR_RT4831=m
CONFIG_REGULATOR_RT6160=m
# CONFIG_REGULATOR_RT6245 is not set
# CONFIG_REGULATOR_RTQ2134 is not set
# CONFIG_REGULATOR_RTMV20 is not set
CONFIG_REGULATOR_RTQ6752=m
# CONFIG_REGULATOR_S2MPA01 is not set
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
# CONFIG_REGULATOR_SC2731 is not set
CONFIG_REGULATOR_SLG51000=y
CONFIG_REGULATOR_STM32_BOOSTER=m
CONFIG_REGULATOR_STM32_VREFBUF=m
# CONFIG_REGULATOR_STM32_PWR is not set
CONFIG_REGULATOR_STPMIC1=m
# CONFIG_REGULATOR_TI_ABB is not set
# CONFIG_REGULATOR_STW481X_VMMC is not set
# CONFIG_REGULATOR_SY8106A is not set
CONFIG_REGULATOR_SY8824X=y
CONFIG_REGULATOR_SY8827N=m
CONFIG_REGULATOR_TPS51632=m
CONFIG_REGULATOR_TPS62360=m
CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=m
# CONFIG_REGULATOR_TPS65086 is not set
CONFIG_REGULATOR_TPS65132=y
CONFIG_REGULATOR_TPS65217=m
CONFIG_REGULATOR_TWL4030=m
CONFIG_REGULATOR_UNIPHIER=m
# CONFIG_REGULATOR_VCTRL is not set
CONFIG_REGULATOR_VEXPRESS=m
CONFIG_REGULATOR_VQMMC_IPQ4019=m
CONFIG_REGULATOR_WM8350=y
# CONFIG_REGULATOR_WM8400 is not set
CONFIG_REGULATOR_WM8994=m
CONFIG_REGULATOR_QCOM_LABIBB=y
CONFIG_RC_CORE=m
# CONFIG_RC_MAP is not set
# CONFIG_LIRC is not set
CONFIG_RC_DECODERS=y
CONFIG_IR_NEC_DECODER=m
CONFIG_IR_RC5_DECODER=m
CONFIG_IR_RC6_DECODER=m
# CONFIG_IR_JVC_DECODER is not set
CONFIG_IR_SONY_DECODER=m
CONFIG_IR_SANYO_DECODER=m
CONFIG_IR_SHARP_DECODER=m
CONFIG_IR_MCE_KBD_DECODER=m
CONFIG_IR_XMP_DECODER=m
# CONFIG_IR_IMON_DECODER is not set
CONFIG_IR_RCMM_DECODER=m
# CONFIG_RC_DEVICES is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_SUPPORT is not set

#
# Graphics support
#
# CONFIG_VGA_ARB is not set
CONFIG_TEGRA_HOST1X=m
# CONFIG_TEGRA_HOST1X_FIREWALL is not set
# CONFIG_IMX_IPUV3_CORE is not set
# CONFIG_DRM is not set

#
# ARM devices
#
# end of ARM devices

#
# Frame buffer Devices
#
# CONFIG_FB is not set
CONFIG_MMP_DISP=m
# CONFIG_MMP_DISP_CONTROLLER is not set
# end of Frame buffer Devices

#
# Backlight & LCD device support
#
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_DA9052=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BACKLIGHT_RT4831 is not set
CONFIG_BACKLIGHT_ADP5520=m
CONFIG_BACKLIGHT_ADP8860=m
CONFIG_BACKLIGHT_ADP8870=m
CONFIG_BACKLIGHT_88PM860X=m
CONFIG_BACKLIGHT_LM3639=m
CONFIG_BACKLIGHT_PANDORA=m
# CONFIG_BACKLIGHT_TPS65217 is not set
# CONFIG_BACKLIGHT_GPIO is not set
CONFIG_BACKLIGHT_LV5207LP=m
# CONFIG_BACKLIGHT_BD6107 is not set
CONFIG_BACKLIGHT_ARCXCNN=m
# CONFIG_BACKLIGHT_RAVE_SP is not set
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support
# end of Graphics support

CONFIG_SOUND=m
# CONFIG_SND is not set

#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
CONFIG_HID_ACCUTOUCH=m
# CONFIG_HID_ACRUX is not set
CONFIG_HID_APPLE=m
CONFIG_HID_APPLEIR=m
CONFIG_HID_ASUS=m
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=m
CONFIG_HID_CORSAIR=m
CONFIG_HID_COUGAR=y
CONFIG_HID_MACALLY=y
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_CREATIVE_SB0540 is not set
CONFIG_HID_CYPRESS=m
# CONFIG_HID_DRAGONRISE is not set
CONFIG_HID_EMS_FF=y
CONFIG_HID_ELAN=m
CONFIG_HID_ELECOM=y
CONFIG_HID_ELO=m
# CONFIG_HID_EZKEY is not set
CONFIG_HID_GEMBIRD=y
CONFIG_HID_GFRM=m
CONFIG_HID_GLORIOUS=m
# CONFIG_HID_HOLTEK is not set
CONFIG_HID_VIVALDI=y
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=y
# CONFIG_HID_KYE is not set
CONFIG_HID_UCLOGIC=m
# CONFIG_HID_WALTOP is not set
CONFIG_HID_VIEWSONIC=m
# CONFIG_HID_GYRATION is not set
CONFIG_HID_ICADE=m
# CONFIG_HID_ITE is not set
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=m
CONFIG_HID_LENOVO=m
CONFIG_HID_LOGITECH=m
CONFIG_HID_LOGITECH_HIDPP=m
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
CONFIG_LOGIG940_FF=y
CONFIG_LOGIWHEELS_FF=y
# CONFIG_HID_MAGICMOUSE is not set
CONFIG_HID_MALTRON=m
CONFIG_HID_MAYFLASH=y
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=y
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NTI=y
CONFIG_HID_NTRIG=m
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
CONFIG_HID_PENMOUNT=m
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PLAYSTATION is not set
CONFIG_HID_PRIMAX=y
CONFIG_HID_RETRODE=m
CONFIG_HID_ROCCAT=m
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SAMSUNG=m
# CONFIG_HID_SEMITEK is not set
CONFIG_HID_SONY=m
CONFIG_SONY_FF=y
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=y
# CONFIG_HID_STEELSERIES is not set
CONFIG_HID_SUNPLUS=m
# CONFIG_HID_RMI is not set
CONFIG_HID_GREENASIA=m
# CONFIG_GREENASIA_FF is not set
CONFIG_HID_SMARTJOYPLUS=m
# CONFIG_SMARTJOYPLUS_FF is not set
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=m
CONFIG_HID_THINGM=m
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
CONFIG_HID_U2FZERO=m
CONFIG_HID_WACOM=m
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
CONFIG_HID_ZEROPLUS=y
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set
CONFIG_HID_ALPS=y
CONFIG_HID_MCP2221=m
# end of Special HID drivers

#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set

#
# USB HID Boot Protocol drivers
#
CONFIG_USB_KBD=m
CONFIG_USB_MOUSE=m
# end of USB HID Boot Protocol drivers
# end of USB HID support

#
# I2C HID support
#
CONFIG_I2C_HID_OF=m
CONFIG_I2C_HID_OF_GOODIX=y
# end of I2C HID support

CONFIG_I2C_HID_CORE=y

#
# Intel ISH HID support
#
# end of Intel ISH HID support

#
# AMD SFH HID Support
#
CONFIG_AMD_SFH_HID=m
# end of AMD SFH HID Support
# end of HID support

CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
CONFIG_USB_ULPI_BUS=y
CONFIG_USB_CONN_GPIO=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
# CONFIG_USB_PCI is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
# CONFIG_USB_DEFAULT_PERSIST is not set
CONFIG_USB_FEW_INIT_RETRIES=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y
CONFIG_USB_OTG_FSM=y
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_MON is not set

#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=m
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
# CONFIG_USB_XHCI_HISTB is not set
CONFIG_USB_XHCI_MTK=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_XHCI_RCAR=m
# CONFIG_USB_BRCMSTB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
# CONFIG_USB_EHCI_FSL is not set
CONFIG_USB_EHCI_HCD_NPCM7XX=y
# CONFIG_USB_EHCI_HCD_ORION is not set
# CONFIG_USB_EHCI_HCD_SPEAR is not set
CONFIG_USB_EHCI_HCD_STI=m
CONFIG_USB_EHCI_HCD_AT91=m
CONFIG_USB_EHCI_SH=y
# CONFIG_USB_EHCI_EXYNOS is not set
CONFIG_USB_EHCI_MV=y
# CONFIG_USB_CNS3XXX_EHCI is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OXU210HP_HCD=y
CONFIG_USB_ISP116X_HCD=y
CONFIG_USB_ISP1362_HCD=y
# CONFIG_USB_FOTG210_HCD is not set
CONFIG_USB_OHCI_HCD=m
# CONFIG_USB_OHCI_HCD_SPEAR is not set
# CONFIG_USB_OHCI_HCD_STI is not set
CONFIG_USB_OHCI_HCD_S3C2410=m
CONFIG_USB_OHCI_HCD_LPC32XX=m
# CONFIG_USB_OHCI_HCD_AT91 is not set
CONFIG_USB_OHCI_HCD_OMAP3=m
# CONFIG_USB_OHCI_HCD_DAVINCI is not set
# CONFIG_USB_OHCI_SH is not set
CONFIG_USB_OHCI_EXYNOS=m
# CONFIG_USB_CNS3XXX_OHCI is not set
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC=y
CONFIG_USB_UHCI_PLATFORM=y
CONFIG_USB_UHCI_ASPEED=y
CONFIG_USB_U132_HCD=m
CONFIG_USB_SL811_HCD=y
CONFIG_USB_SL811_HCD_ISO=y
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_RENESAS_USBHS_HCD=m
CONFIG_USB_HCD_BCMA=y
# CONFIG_USB_HCD_TEST_MODE is not set
CONFIG_USB_RENESAS_USBHS=m

#
# USB Device Class drivers
#
CONFIG_USB_PRINTER=y
CONFIG_USB_WDM=y
CONFIG_USB_TMC=m

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#

#
# USB Imaging devices
#
CONFIG_USB_MDC800=y
CONFIG_USB_CDNS_SUPPORT=y
# CONFIG_USB_CDNS3 is not set
CONFIG_USB_MTU3=m
# CONFIG_USB_MTU3_HOST is not set
# CONFIG_USB_MTU3_GADGET is not set
CONFIG_USB_MTU3_DUAL_ROLE=y
# CONFIG_USB_MTU3_DEBUG is not set
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_HOST=y

#
# Platform Glue Layer
#
# CONFIG_USB_MUSB_OMAP2PLUS is not set
CONFIG_USB_MUSB_DSPS=m
# CONFIG_USB_MUSB_UX500 is not set

#
# MUSB DMA mode
#
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_ULPI=y
CONFIG_USB_DWC3_HOST=y

#
# Platform Glue Driver Support
#
# CONFIG_USB_DWC3_OMAP is not set
CONFIG_USB_DWC3_EXYNOS=m
# CONFIG_USB_DWC3_KEYSTONE is not set
CONFIG_USB_DWC3_MESON_G12A=m
# CONFIG_USB_DWC3_OF_SIMPLE is not set
CONFIG_USB_DWC3_ST=m
CONFIG_USB_DWC3_QCOM=m
# CONFIG_USB_DWC3_IMX8MP is not set
CONFIG_USB_DWC2=m
CONFIG_USB_DWC2_HOST=y

#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_PERIPHERAL is not set
# CONFIG_USB_DWC2_DUAL_ROLE is not set
CONFIG_USB_DWC2_DEBUG=y
# CONFIG_USB_DWC2_VERBOSE is not set
CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y
# CONFIG_USB_DWC2_DEBUG_PERIODIC is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_ISP1760_HOST_ROLE=y
# CONFIG_USB_ISP1760_GADGET_ROLE is not set
# CONFIG_USB_ISP1760_DUAL_ROLE is not set

#
# USB port drivers
#
CONFIG_USB_USS720=m

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
CONFIG_USB_ADUTUX=m
CONFIG_USB_SEVSEG=y
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
CONFIG_USB_CYPRESS_CY7C63=y
CONFIG_USB_CYTHERM=y
# CONFIG_USB_IDMOUSE is not set
CONFIG_USB_FTDI_ELAN=m
CONFIG_USB_APPLEDISPLAY=m
CONFIG_APPLE_MFI_FASTCHARGE=m
CONFIG_USB_SISUSBVGA=y
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=y
CONFIG_USB_IOWARRIOR=y
# CONFIG_USB_TEST is not set
CONFIG_USB_EHSET_TEST_FIXTURE=y
CONFIG_USB_ISIGHTFW=y
CONFIG_USB_YUREX=m
# CONFIG_USB_EZUSB_FX2 is not set
CONFIG_USB_HUB_USB251XB=m
CONFIG_USB_HSIC_USB3503=y
CONFIG_USB_HSIC_USB4604=m
CONFIG_USB_LINK_LAYER_TEST=m
# CONFIG_USB_CHAOSKEY is not set
# CONFIG_BRCM_USB_PINMAP is not set

#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
CONFIG_AB8500_USB=m
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=m
# CONFIG_TAHVO_USB is not set
CONFIG_USB_ISP1301=y
CONFIG_USB_MV_OTG=m
CONFIG_USB_MXS_PHY=y
# CONFIG_USB_TEGRA_PHY is not set
# CONFIG_USB_ULPI is not set
# CONFIG_JZ4770_PHY is not set
# end of USB Physical Layer drivers

CONFIG_USB_GADGET=m
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2

#
# USB Peripheral Controller
#
CONFIG_USB_LPC32XX=m
CONFIG_USB_FUSB300=m
CONFIG_USB_FOTG210_UDC=m
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
CONFIG_USB_RENESAS_USBHS_UDC=m
CONFIG_USB_RENESAS_USB3=m
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
CONFIG_USB_SNP_CORE=m
CONFIG_USB_SNP_UDC_PLAT=m
CONFIG_USB_M66592=m
# CONFIG_USB_BDC_UDC is not set
CONFIG_USB_NET2272=m
# CONFIG_USB_NET2272_DMA is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_ASPEED_VHUB is not set
# CONFIG_USB_DUMMY_HCD is not set
# end of USB Peripheral Controller

CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_F_FS=m
CONFIG_USB_F_HID=m
CONFIG_USB_F_PRINTER=m
CONFIG_USB_CONFIGFS=m
CONFIG_USB_CONFIGFS_F_LB_SS=y
# CONFIG_USB_CONFIGFS_F_FS is not set
CONFIG_USB_CONFIGFS_F_HID=y
CONFIG_USB_CONFIGFS_F_PRINTER=y

#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
# CONFIG_USB_GADGETFS is not set
CONFIG_USB_FUNCTIONFS=m
CONFIG_USB_FUNCTIONFS_GENERIC=y
CONFIG_USB_G_PRINTER=m
CONFIG_USB_G_HID=m
# CONFIG_USB_RAW_GADGET is not set
# end of USB Gadget precomposed configurations

# CONFIG_TYPEC is not set
CONFIG_USB_ROLE_SWITCH=y
# CONFIG_MMC is not set
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y

#
# MemoryStick drivers
#
CONFIG_MEMSTICK_UNSAFE_RESUME=y

#
# MemoryStick Host Controller Drivers
#
CONFIG_MEMSTICK_TIFM_MS=m
CONFIG_MEMSTICK_JMICRON_38X=m
CONFIG_MEMSTICK_R592=y
CONFIG_MEMSTICK_REALTEK_PCI=m
CONFIG_MEMSTICK_REALTEK_USB=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
# CONFIG_LEDS_CLASS_FLASH is not set
CONFIG_LEDS_CLASS_MULTICOLOR=m
CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y

#
# LED drivers
#
# CONFIG_LEDS_88PM860X is not set
# CONFIG_LEDS_AN30259A is not set
CONFIG_LEDS_ARIEL=m
CONFIG_LEDS_AW2013=m
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
CONFIG_LEDS_TURRIS_OMNIA=m
CONFIG_LEDS_LM3530=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_LM3642=m
# CONFIG_LEDS_LM3692X is not set
CONFIG_LEDS_MT6323=m
# CONFIG_LEDS_S3C24XX is not set
# CONFIG_LEDS_COBALT_QUBE is not set
CONFIG_LEDS_PCA9532=m
# CONFIG_LEDS_PCA9532_GPIO is not set
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_LP3944=m
CONFIG_LEDS_LP3952=m
CONFIG_LEDS_LP50XX=m
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
CONFIG_LEDS_LP8501=m
CONFIG_LEDS_LP8860=m
CONFIG_LEDS_PCA955X=m
# CONFIG_LEDS_PCA955X_GPIO is not set
# CONFIG_LEDS_PCA963X is not set
CONFIG_LEDS_WM8350=m
CONFIG_LEDS_DA9052=m
CONFIG_LEDS_REGULATOR=m
CONFIG_LEDS_BD2802=m
CONFIG_LEDS_LT3593=m
# CONFIG_LEDS_ADP5520 is not set
CONFIG_LEDS_MC13783=m
CONFIG_LEDS_NS2=m
CONFIG_LEDS_NETXBIG=m
CONFIG_LEDS_TCA6507=m
CONFIG_LEDS_TLC591XX=m
# CONFIG_LEDS_MAX77650 is not set
# CONFIG_LEDS_MAX8997 is not set
# CONFIG_LEDS_LM355x is not set
CONFIG_LEDS_OT200=m
# CONFIG_LEDS_MENF21BMC is not set
CONFIG_LEDS_IS31FL319X=m
# CONFIG_LEDS_IS31FL32XX is not set

#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_PM8058=m
# CONFIG_LEDS_MLXREG is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_TI_LMU_COMMON is not set
CONFIG_LEDS_IP30=m
CONFIG_LEDS_ACER_A500=m
CONFIG_LEDS_LGM=m

#
# Flash and Torch LED drivers
#

#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=m
CONFIG_LEDS_TRIGGER_GPIO=m
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=m
# CONFIG_LEDS_TRIGGER_CAMERA is not set
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_PATTERN=y
CONFIG_LEDS_TRIGGER_AUDIO=y
CONFIG_ACCESSIBILITY=y

#
# Speakup console speech
#
# end of Speakup console speech

CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
CONFIG_DMADEVICES=y
CONFIG_DMADEVICES_DEBUG=y
CONFIG_DMADEVICES_VDEBUG=y

#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
CONFIG_ALTERA_MSGDMA=m
# CONFIG_AMBA_PL08X is not set
CONFIG_AXI_DMAC=m
# CONFIG_DMA_BCM2835 is not set
CONFIG_DMA_JZ4780=m
CONFIG_DMA_SA11X0=y
CONFIG_DMA_SUN6I=y
# CONFIG_DW_AXI_DMAC is not set
CONFIG_EP93XX_DMA=y
CONFIG_FSL_EDMA=y
# CONFIG_FSL_QDMA is not set
CONFIG_HISI_DMA=m
CONFIG_IMG_MDC_DMA=y
CONFIG_IMX_DMA=m
CONFIG_IMX_SDMA=y
# CONFIG_INTEL_IDMA64 is not set
CONFIG_INTEL_IOP_ADMA=m
CONFIG_K3_DMA=m
# CONFIG_MCF_EDMA is not set
# CONFIG_MILBEAUT_HDMAC is not set
# CONFIG_MILBEAUT_XDMAC is not set
CONFIG_MMP_PDMA=m
CONFIG_MMP_TDMA=m
# CONFIG_MV_XOR is not set
# CONFIG_MXS_DMA is not set
# CONFIG_MX3_IPU is not set
CONFIG_NBPFAXI_DMA=m
CONFIG_PCH_DMA=m
# CONFIG_PL330_DMA is not set
# CONFIG_PLX_DMA is not set
# CONFIG_STE_DMA40 is not set
CONFIG_ST_FDMA=y
# CONFIG_STM32_DMA is not set
CONFIG_STM32_DMAMUX=y
# CONFIG_STM32_MDMA is not set
CONFIG_SPRD_DMA=m
CONFIG_S3C24XX_DMAC=y
CONFIG_TEGRA20_APB_DMA=m
# CONFIG_TEGRA210_ADMA is not set
# CONFIG_TIMB_DMA is not set
CONFIG_UNIPHIER_MDMAC=m
CONFIG_UNIPHIER_XDMAC=y
CONFIG_XGENE_DMA=y
# CONFIG_XILINX_DMA is not set
# CONFIG_XILINX_ZYNQMP_DMA is not set
CONFIG_XILINX_ZYNQMP_DPDMA=m
CONFIG_MTK_HSDMA=y
CONFIG_MTK_CQDMA=y
CONFIG_QCOM_ADM=m
# CONFIG_QCOM_BAM_DMA is not set
# CONFIG_QCOM_GPI_DMA is not set
CONFIG_QCOM_HIDMA_MGMT=m
CONFIG_QCOM_HIDMA=y
CONFIG_DW_DMAC_CORE=y
# CONFIG_DW_DMAC is not set
CONFIG_DW_DMAC_PCI=y
CONFIG_DW_EDMA=y
CONFIG_DW_EDMA_PCIE=m
# CONFIG_SF_PDMA is not set
CONFIG_RENESAS_DMA=y
# CONFIG_SH_DMAE_BASE is not set
# CONFIG_RCAR_DMAC is not set
CONFIG_RENESAS_USB_DMAC=m
CONFIG_RZ_DMAC=y
# CONFIG_TI_CPPI41 is not set
CONFIG_TI_EDMA=m
CONFIG_DMA_OMAP=y
CONFIG_TI_DMA_CROSSBAR=y
CONFIG_INTEL_LDMA=y

#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
CONFIG_DMATEST=m
CONFIG_DMA_ENGINE_RAID=y

#
# DMABUF options
#
# CONFIG_SYNC_FILE is not set
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
CONFIG_DMABUF_DEBUG=y
# CONFIG_DMABUF_SELFTESTS is not set
CONFIG_DMABUF_HEAPS=y
# CONFIG_DMABUF_SYSFS_STATS is not set
# CONFIG_DMABUF_HEAPS_SYSTEM is not set
# end of DMABUF options

CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_HD44780_COMMON=y
# CONFIG_HD44780 is not set
CONFIG_IMG_ASCII_LCD=y
# CONFIG_LCD2S is not set
CONFIG_ARM_CHARLCD=y
CONFIG_PARPORT_PANEL=m
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
CONFIG_PANEL_CHANGE_MESSAGE=y
CONFIG_PANEL_BOOT_MESSAGE=""
# CONFIG_CHARLCD_BL_OFF is not set
CONFIG_CHARLCD_BL_ON=y
# CONFIG_CHARLCD_BL_FLASH is not set
# CONFIG_PANEL is not set
CONFIG_UIO=m
# CONFIG_UIO_CIF is not set
CONFIG_UIO_PDRV_GENIRQ=m
CONFIG_UIO_DMEM_GENIRQ=m
# CONFIG_UIO_AEC is not set
# CONFIG_UIO_SERCOS3 is not set
# CONFIG_UIO_PCI_GENERIC is not set
CONFIG_UIO_NETX=m
CONFIG_UIO_PRUSS=m
CONFIG_UIO_MF624=m
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set

#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support

#
# Xen driver support
#
CONFIG_XEN_BALLOON=y
CONFIG_XEN_SCRUB_PAGES_DEFAULT=y
CONFIG_XEN_DEV_EVTCHN=m
# CONFIG_XEN_BACKEND is not set
# CONFIG_XENFS is not set
# CONFIG_XEN_SYS_HYPERVISOR is not set
CONFIG_XEN_XENBUS_FRONTEND=m
# CONFIG_XEN_GNTDEV is not set
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_XEN_GRANT_DMA_ALLOC=y
CONFIG_SWIOTLB_XEN=y
CONFIG_XEN_PRIVCMD=m
CONFIG_XEN_AUTO_XLATE=y
# end of Xen driver support

# CONFIG_GREYBUS is not set
CONFIG_COMEDI=m
# CONFIG_COMEDI_DEBUG is not set
CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
# CONFIG_COMEDI_MISC_DRIVERS is not set
# CONFIG_COMEDI_ISA_DRIVERS is not set
CONFIG_COMEDI_PCI_DRIVERS=m
CONFIG_COMEDI_8255_PCI=m
CONFIG_COMEDI_ADDI_WATCHDOG=m
# CONFIG_COMEDI_ADDI_APCI_1032 is not set
# CONFIG_COMEDI_ADDI_APCI_1500 is not set
# CONFIG_COMEDI_ADDI_APCI_1516 is not set
CONFIG_COMEDI_ADDI_APCI_1564=m
CONFIG_COMEDI_ADDI_APCI_16XX=m
CONFIG_COMEDI_ADDI_APCI_2032=m
CONFIG_COMEDI_ADDI_APCI_2200=m
CONFIG_COMEDI_ADDI_APCI_3120=m
CONFIG_COMEDI_ADDI_APCI_3501=m
CONFIG_COMEDI_ADDI_APCI_3XXX=m
# CONFIG_COMEDI_ADL_PCI6208 is not set
# CONFIG_COMEDI_ADL_PCI7X3X is not set
CONFIG_COMEDI_ADL_PCI8164=m
CONFIG_COMEDI_ADL_PCI9111=m
CONFIG_COMEDI_ADL_PCI9118=m
# CONFIG_COMEDI_ADV_PCI1710 is not set
CONFIG_COMEDI_ADV_PCI1720=m
# CONFIG_COMEDI_ADV_PCI1723 is not set
# CONFIG_COMEDI_ADV_PCI1724 is not set
CONFIG_COMEDI_ADV_PCI1760=m
# CONFIG_COMEDI_ADV_PCI_DIO is not set
# CONFIG_COMEDI_AMPLC_DIO200_PCI is not set
# CONFIG_COMEDI_AMPLC_PC236_PCI is not set
CONFIG_COMEDI_AMPLC_PC263_PCI=m
CONFIG_COMEDI_AMPLC_PCI224=m
CONFIG_COMEDI_AMPLC_PCI230=m
# CONFIG_COMEDI_CONTEC_PCI_DIO is not set
# CONFIG_COMEDI_DAS08_PCI is not set
CONFIG_COMEDI_DT3000=m
# CONFIG_COMEDI_DYNA_PCI10XX is not set
CONFIG_COMEDI_GSC_HPDI=m
CONFIG_COMEDI_MF6X4=m
CONFIG_COMEDI_ICP_MULTI=m
# CONFIG_COMEDI_DAQBOARD2000 is not set
CONFIG_COMEDI_JR3_PCI=m
# CONFIG_COMEDI_KE_COUNTER is not set
# CONFIG_COMEDI_CB_PCIDAS64 is not set
# CONFIG_COMEDI_CB_PCIDAS is not set
# CONFIG_COMEDI_CB_PCIDDA is not set
# CONFIG_COMEDI_CB_PCIMDAS is not set
# CONFIG_COMEDI_CB_PCIMDDA is not set
CONFIG_COMEDI_ME4000=m
CONFIG_COMEDI_ME_DAQ=m
CONFIG_COMEDI_NI_6527=m
CONFIG_COMEDI_NI_65XX=m
# CONFIG_COMEDI_NI_660X is not set
CONFIG_COMEDI_NI_670X=m
CONFIG_COMEDI_NI_LABPC_PCI=m
CONFIG_COMEDI_NI_PCIDIO=m
CONFIG_COMEDI_NI_PCIMIO=m
CONFIG_COMEDI_RTD520=m
CONFIG_COMEDI_S626=m
CONFIG_COMEDI_MITE=m
CONFIG_COMEDI_NI_TIOCMD=m
CONFIG_COMEDI_USB_DRIVERS=m
CONFIG_COMEDI_DT9812=m
# CONFIG_COMEDI_NI_USB6501 is not set
# CONFIG_COMEDI_USBDUX is not set
# CONFIG_COMEDI_USBDUXFAST is not set
CONFIG_COMEDI_USBDUXSIGMA=m
CONFIG_COMEDI_VMK80XX=m
CONFIG_COMEDI_8254=m
CONFIG_COMEDI_8255=m
# CONFIG_COMEDI_8255_SA is not set
CONFIG_COMEDI_KCOMEDILIB=m
CONFIG_COMEDI_NI_LABPC=m
CONFIG_COMEDI_NI_TIO=m
CONFIG_COMEDI_NI_ROUTING=m
CONFIG_COMEDI_TESTS=m
CONFIG_COMEDI_TESTS_EXAMPLE=m
CONFIG_COMEDI_TESTS_NI_ROUTES=m
CONFIG_STAGING=y
CONFIG_USB_EMXX=m
CONFIG_STAGING_MEDIA=y

#
# Android
#
# end of Android

# CONFIG_STAGING_BOARD is not set
# CONFIG_GS_FPGABOOT is not set
# CONFIG_UNISYSSPAR is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_MOST_COMPONENTS=m
CONFIG_MOST_DIM2=m
CONFIG_MOST_I2C=m
CONFIG_BCM_VIDEOCORE=m
# CONFIG_BCM2835_VCHIQ is not set
CONFIG_XIL_AXIS_FIFO=m
CONFIG_FIELDBUS_DEV=m
# CONFIG_HMS_ANYBUSS_BUS is not set
CONFIG_GOLDFISH=y
CONFIG_GOLDFISH_PIPE=y
CONFIG_CHROME_PLATFORMS=y
# CONFIG_CROS_EC is not set
CONFIG_MELLANOX_PLATFORM=y
CONFIG_MLXREG_HOTPLUG=m
CONFIG_MLXREG_IO=m
CONFIG_OLPC_XO175=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Clock driver for ARM Reference designs
#
CONFIG_ICST=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=m
# end of Clock driver for ARM Reference designs

CONFIG_CLK_HSDK=y
# CONFIG_COMMON_CLK_MAX77686 is not set
CONFIG_COMMON_CLK_MAX9485=y
CONFIG_COMMON_CLK_HI655X=y
# CONFIG_COMMON_CLK_SCMI is not set
# CONFIG_COMMON_CLK_SCPI is not set
# CONFIG_COMMON_CLK_SI5341 is not set
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_SI514 is not set
CONFIG_COMMON_CLK_SI544=y
# CONFIG_COMMON_CLK_SI570 is not set
CONFIG_COMMON_CLK_BM1880=y
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CDCE925 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
CONFIG_COMMON_CLK_FSL_FLEXSPI=y
# CONFIG_COMMON_CLK_FSL_SAI is not set
CONFIG_COMMON_CLK_GEMINI=y
CONFIG_COMMON_CLK_ASPEED=y
CONFIG_COMMON_CLK_S2MPS11=m
CONFIG_CLK_TWL6040=y
CONFIG_COMMON_CLK_AXI_CLKGEN=y
# CONFIG_CLK_QORIQ is not set
# CONFIG_CLK_LS1028A_PLLDIG is not set
CONFIG_COMMON_CLK_XGENE=y
CONFIG_COMMON_CLK_OXNAS=y
CONFIG_COMMON_CLK_VC5=m
CONFIG_COMMON_CLK_MMP2_AUDIO=m
# CONFIG_COMMON_CLK_BD718XX is not set
# CONFIG_COMMON_CLK_FIXED_MMIO is not set
# CONFIG_CLK_ACTIONS is not set
# CONFIG_CLK_BAIKAL_T1 is not set
# CONFIG_CLK_BCM2711_DVP is not set
CONFIG_CLK_BCM2835=y
CONFIG_CLK_BCM_63XX=y
# CONFIG_CLK_BCM_63XX_GATE is not set
# CONFIG_CLK_BCM_KONA is not set
CONFIG_COMMON_CLK_IPROC=y
# CONFIG_CLK_BCM_CYGNUS is not set
# CONFIG_CLK_BCM_HR2 is not set
# CONFIG_CLK_BCM_NSP is not set
# CONFIG_CLK_BCM_NS2 is not set
CONFIG_CLK_BCM_SR=y
# CONFIG_CLK_RASPBERRYPI is not set
# CONFIG_COMMON_CLK_HI3516CV300 is not set
CONFIG_COMMON_CLK_HI3519=y
# CONFIG_COMMON_CLK_HI3559A is not set
CONFIG_COMMON_CLK_HI3660=y
# CONFIG_COMMON_CLK_HI3670 is not set
# CONFIG_COMMON_CLK_HI3798CV200 is not set
CONFIG_COMMON_CLK_HI6220=y
CONFIG_RESET_HISI=y
CONFIG_STUB_CLK_HI6220=y
# CONFIG_STUB_CLK_HI3660 is not set
# CONFIG_COMMON_CLK_BOSTON is not set
CONFIG_MXC_CLK=y
CONFIG_CLK_IMX5=y
CONFIG_CLK_IMX6Q=y
CONFIG_CLK_IMX6SL=y
CONFIG_CLK_IMX6SX=y
# CONFIG_CLK_IMX8MM is not set
CONFIG_CLK_IMX8MN=y
CONFIG_CLK_IMX8MP=m
CONFIG_CLK_IMX8MQ=y

#
# Ingenic SoCs drivers
#
CONFIG_INGENIC_CGU_COMMON=y
CONFIG_INGENIC_CGU_JZ4740=y
CONFIG_INGENIC_CGU_JZ4725B=y
CONFIG_INGENIC_CGU_JZ4760=y
CONFIG_INGENIC_CGU_JZ4770=y
# CONFIG_INGENIC_CGU_JZ4780 is not set
# CONFIG_INGENIC_CGU_X1000 is not set
# CONFIG_INGENIC_CGU_X1830 is not set
CONFIG_INGENIC_TCU_CLK=y
# end of Ingenic SoCs drivers

CONFIG_COMMON_CLK_KEYSTONE=y
# CONFIG_TI_SYSCON_CLK is not set

#
# Clock driver for MediaTek SoC
#
CONFIG_COMMON_CLK_MEDIATEK=y
# CONFIG_COMMON_CLK_MT2701 is not set
# CONFIG_COMMON_CLK_MT2712 is not set
# CONFIG_COMMON_CLK_MT6765 is not set
# CONFIG_COMMON_CLK_MT6779 is not set
CONFIG_COMMON_CLK_MT6797=y
# CONFIG_COMMON_CLK_MT6797_MMSYS is not set
CONFIG_COMMON_CLK_MT6797_IMGSYS=y
CONFIG_COMMON_CLK_MT6797_VDECSYS=y
# CONFIG_COMMON_CLK_MT6797_VENCSYS is not set
CONFIG_COMMON_CLK_MT7622=y
# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
CONFIG_COMMON_CLK_MT7622_HIFSYS=y
CONFIG_COMMON_CLK_MT7622_AUDSYS=y
CONFIG_COMMON_CLK_MT7629=y
CONFIG_COMMON_CLK_MT7629_ETHSYS=y
CONFIG_COMMON_CLK_MT7629_HIFSYS=y
CONFIG_COMMON_CLK_MT8135=y
# CONFIG_COMMON_CLK_MT8167 is not set
# CONFIG_COMMON_CLK_MT8173 is not set
CONFIG_COMMON_CLK_MT8183=y
CONFIG_COMMON_CLK_MT8183_AUDIOSYS=y
CONFIG_COMMON_CLK_MT8183_CAMSYS=y
# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set
CONFIG_COMMON_CLK_MT8183_IPU_CORE0=y
CONFIG_COMMON_CLK_MT8183_IPU_CORE1=y
CONFIG_COMMON_CLK_MT8183_IPU_ADL=y
# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set
CONFIG_COMMON_CLK_MT8183_MFGCFG=y
# CONFIG_COMMON_CLK_MT8183_MMSYS is not set
# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set
# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set
CONFIG_COMMON_CLK_MT8192=y
# CONFIG_COMMON_CLK_MT8192_AUDSYS is not set
CONFIG_COMMON_CLK_MT8192_CAMSYS=y
# CONFIG_COMMON_CLK_MT8192_IMGSYS is not set
CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
CONFIG_COMMON_CLK_MT8192_IPESYS=y
# CONFIG_COMMON_CLK_MT8192_MDPSYS is not set
# CONFIG_COMMON_CLK_MT8192_MFGCFG is not set
CONFIG_COMMON_CLK_MT8192_MMSYS=y
# CONFIG_COMMON_CLK_MT8192_MSDC is not set
# CONFIG_COMMON_CLK_MT8192_SCP_ADSP is not set
# CONFIG_COMMON_CLK_MT8192_VDECSYS is not set
CONFIG_COMMON_CLK_MT8192_VENCSYS=y
CONFIG_COMMON_CLK_MT8516=y
# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set
# end of Clock driver for MediaTek SoC

#
# Clock support for Amlogic platforms
#
# CONFIG_COMMON_CLK_MESON8B is not set
# end of Clock support for Amlogic platforms

CONFIG_MSTAR_MSC313_MPLL=y
# CONFIG_COMMON_CLK_PISTACHIO is not set
CONFIG_KRAIT_CLOCKS=y
CONFIG_QCOM_GDSC=y
CONFIG_QCOM_RPMCC=y
CONFIG_COMMON_CLK_QCOM=y
# CONFIG_QCOM_A53PLL is not set
# CONFIG_QCOM_A7PLL is not set
CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCS_SDX55=y
CONFIG_QCOM_CLK_RPM=y
# CONFIG_QCOM_CLK_RPMH is not set
CONFIG_APQ_GCC_8084=m
CONFIG_APQ_MMCC_8084=m
CONFIG_IPQ_APSS_PLL=m
# CONFIG_IPQ_APSS_6018 is not set
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8660=y
# CONFIG_MSM_GCC_8916 is not set
CONFIG_MSM_GCC_8939=m
CONFIG_MSM_GCC_8960=m
CONFIG_MSM_LCC_8960=m
CONFIG_MDM_GCC_9607=m
CONFIG_MDM_GCC_9615=m
CONFIG_MDM_LCC_9615=m
# CONFIG_MSM_MMCC_8960 is not set
CONFIG_MSM_GCC_8953=y
CONFIG_MSM_GCC_8974=m
# CONFIG_MSM_MMCC_8974 is not set
CONFIG_MSM_MMCC_8994=m
CONFIG_MSM_GCC_8994=y
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_MMCC_8996 is not set
CONFIG_MSM_GCC_8998=y
# CONFIG_MSM_GPUCC_8998 is not set
CONFIG_MSM_MMCC_8998=y
CONFIG_QCS_GCC_404=y
CONFIG_SC_CAMCC_7180=m
CONFIG_SC_DISPCC_7180=m
# CONFIG_SC_DISPCC_7280 is not set
CONFIG_SC_GCC_7180=m
CONFIG_SC_GCC_7280=y
CONFIG_SC_GCC_8180X=y
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
CONFIG_SC_GPUCC_7280=y
# CONFIG_SC_MSS_7180 is not set
CONFIG_SC_VIDEOCC_7180=m
CONFIG_SC_VIDEOCC_7280=y
CONFIG_SDM_CAMCC_845=m
CONFIG_SDM_GCC_660=m
# CONFIG_SDM_MMCC_660 is not set
CONFIG_SDM_GPUCC_660=m
CONFIG_QCS_TURING_404=m
CONFIG_QCS_Q6SSTOP_404=y
CONFIG_SDM_GCC_845=y
CONFIG_SDM_GPUCC_845=y
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SDM_DISPCC_845=m
CONFIG_SDM_LPASSCC_845=y
CONFIG_SDX_GCC_55=y
# CONFIG_SM_CAMCC_8250 is not set
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_GCC_6115=y
# CONFIG_SM_GCC_6125 is not set
CONFIG_SM_GCC_6350=m
CONFIG_SM_GCC_8150=y
CONFIG_SM_GCC_8250=y
CONFIG_SM_GCC_8350=y
CONFIG_SM_GPUCC_8150=m
CONFIG_SM_GPUCC_8250=y
CONFIG_SM_VIDEOCC_8150=y
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPMI_PMIC_CLKDIV=y
CONFIG_QCOM_HFPLL=m
# CONFIG_KPSS_XCC is not set
CONFIG_KRAITCC=m
# CONFIG_CLK_GFM_LPASS_SM8250 is not set
# CONFIG_CLK_MT7621 is not set
# CONFIG_CLK_RENESAS is not set
CONFIG_COMMON_CLK_SAMSUNG=y
CONFIG_S3C64XX_COMMON_CLK=y
# CONFIG_S5PV210_COMMON_CLK is not set
CONFIG_EXYNOS_3250_COMMON_CLK=y
CONFIG_EXYNOS_4_COMMON_CLK=y
CONFIG_EXYNOS_5250_COMMON_CLK=y
CONFIG_EXYNOS_5260_COMMON_CLK=y
# CONFIG_EXYNOS_5410_COMMON_CLK is not set
CONFIG_EXYNOS_5420_COMMON_CLK=y
CONFIG_EXYNOS_ARM64_COMMON_CLK=y
# CONFIG_EXYNOS_AUDSS_CLK_CON is not set
CONFIG_EXYNOS_CLKOUT=m
CONFIG_S3C2410_COMMON_CLK=y
CONFIG_S3C2412_COMMON_CLK=y
CONFIG_S3C2443_COMMON_CLK=y
CONFIG_CLK_SIFIVE=y
# CONFIG_CLK_SIFIVE_PRCI is not set
CONFIG_CLK_INTEL_SOCFPGA=y
CONFIG_CLK_INTEL_SOCFPGA32=y
# CONFIG_CLK_INTEL_SOCFPGA64 is not set
CONFIG_SPRD_COMMON_CLK=m
CONFIG_SPRD_SC9860_CLK=m
CONFIG_SPRD_SC9863A_CLK=m
CONFIG_CLK_SUNXI=y
CONFIG_CLK_SUNXI_CLOCKS=y
CONFIG_CLK_SUNXI_PRCM_SUN6I=y
CONFIG_CLK_SUNXI_PRCM_SUN8I=y
# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
CONFIG_SUNXI_CCU=y
# CONFIG_SUNIV_F1C100S_CCU is not set
# CONFIG_SUN50I_A64_CCU is not set
# CONFIG_SUN50I_A100_CCU is not set
# CONFIG_SUN50I_A100_R_CCU is not set
# CONFIG_SUN50I_H6_CCU is not set
CONFIG_SUN50I_H616_CCU=y
CONFIG_SUN50I_H6_R_CCU=y
CONFIG_SUN4I_A10_CCU=y
# CONFIG_SUN5I_CCU is not set
# CONFIG_SUN6I_A31_CCU is not set
CONFIG_SUN8I_A23_CCU=y
# CONFIG_SUN8I_A33_CCU is not set
CONFIG_SUN8I_A83T_CCU=y
# CONFIG_SUN8I_H3_CCU is not set
# CONFIG_SUN8I_V3S_CCU is not set
# CONFIG_SUN8I_DE2_CCU is not set
CONFIG_SUN8I_R40_CCU=y
CONFIG_SUN9I_A80_CCU=y
CONFIG_SUN8I_R_CCU=y
# CONFIG_COMMON_CLK_TI_ADPLL is not set
# CONFIG_CLK_UNIPHIER is not set
CONFIG_CLK_LGM_CGU=y
CONFIG_XILINX_VCU=y
# CONFIG_COMMON_CLK_ZYNQMP is not set
# CONFIG_HWSPINLOCK is not set

#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_OMAP_DM_TIMER=y
CONFIG_CLKSRC_MMIO=y
CONFIG_BCM2835_TIMER=y
# CONFIG_BCM_KONA_TIMER is not set
# CONFIG_DAVINCI_TIMER is not set
CONFIG_DIGICOLOR_TIMER=y
CONFIG_DW_APB_TIMER=y
CONFIG_DW_APB_TIMER_OF=y
# CONFIG_FTTMR010_TIMER is not set
CONFIG_IXP4XX_TIMER=y
# CONFIG_ROCKCHIP_TIMER is not set
CONFIG_ARMADA_370_XP_TIMER=y
CONFIG_MESON6_TIMER=y
CONFIG_ORION_TIMER=y
CONFIG_OWL_TIMER=y
# CONFIG_RDA_TIMER is not set
# CONFIG_SUN4I_TIMER is not set
# CONFIG_SUN5I_HSTIMER is not set
# CONFIG_TEGRA_TIMER is not set
CONFIG_VT8500_TIMER=y
# CONFIG_NPCM7XX_TIMER is not set
CONFIG_CADENCE_TTC_TIMER=y
# CONFIG_ASM9260_TIMER is not set
CONFIG_CLKSRC_NOMADIK_MTU=y
CONFIG_CLKSRC_DBX500_PRCMU=y
# CONFIG_CLPS711X_TIMER is not set
# CONFIG_MXS_TIMER is not set
CONFIG_NSPIRE_TIMER=y
CONFIG_KEYSTONE_TIMER=y
# CONFIG_INTEGRATOR_AP_TIMER is not set
# CONFIG_CLKSRC_LPC32XX is not set
# CONFIG_CLKSRC_PISTACHIO is not set
CONFIG_CLKSRC_TI_32K=y
CONFIG_CLKSRC_STM32=y
CONFIG_CLKSRC_STM32_LP=y
# CONFIG_CLKSRC_MPS2 is not set
CONFIG_ARC_TIMERS=y
# CONFIG_ARC_TIMERS_64BIT is not set
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_GLOBAL_TIMER=y
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
CONFIG_ARM_TIMER_SP804=y
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
# CONFIG_ARMV7M_SYSTICK is not set
# CONFIG_ATMEL_PIT is not set
# CONFIG_ATMEL_ST is not set
# CONFIG_ATMEL_TCB_CLKSRC is not set
CONFIG_CLKSRC_EXYNOS_MCT=y
CONFIG_CLKSRC_SAMSUNG_PWM=y
# CONFIG_FSL_FTM_TIMER is not set
# CONFIG_OXNAS_RPS_TIMER is not set
CONFIG_MTK_TIMER=y
# CONFIG_SPRD_TIMER is not set
CONFIG_CLKSRC_JCORE_PIT=y
CONFIG_SH_TIMER_CMT=y
CONFIG_SH_TIMER_MTU2=y
# CONFIG_RENESAS_OSTM is not set
# CONFIG_SH_TIMER_TMU is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_CLKSRC_QCOM=y
CONFIG_CLKSRC_VERSATILE=y
# CONFIG_CLKSRC_PXA is not set
# CONFIG_H8300_TMR8 is not set
# CONFIG_H8300_TMR16 is not set
# CONFIG_H8300_TPU is not set
CONFIG_CLKSRC_IMX_GPT=y
CONFIG_CLKSRC_IMX_TPM=y
CONFIG_TIMER_IMX_SYS_CTR=y
CONFIG_CLKSRC_ST_LPC=y
# CONFIG_ATCPIT100_TIMER is not set
# CONFIG_MILBEAUT_TIMER is not set
# CONFIG_INGENIC_TIMER is not set
# CONFIG_INGENIC_SYSOST is not set
CONFIG_INGENIC_OST=y
CONFIG_MICROCHIP_PIT64B=y
# end of Clock Source drivers

CONFIG_MAILBOX=y
# CONFIG_ARM_MHU is not set
CONFIG_ARM_MHU_V2=m
# CONFIG_IMX_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
CONFIG_PL320_MBOX=y
CONFIG_ARMADA_37XX_RWTM_MBOX=y
CONFIG_OMAP2PLUS_MBOX=y
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
# CONFIG_ROCKCHIP_MBOX is not set
CONFIG_ALTERA_MBOX=m
# CONFIG_BCM2835_MBOX is not set
CONFIG_STI_MBOX=y
CONFIG_TI_MESSAGE_MANAGER=y
# CONFIG_HI3660_MBOX is not set
# CONFIG_HI6220_MBOX is not set
CONFIG_MAILBOX_TEST=y
CONFIG_POLARFIRE_SOC_MAILBOX=y
# CONFIG_QCOM_APCS_IPC is not set
CONFIG_BCM_PDC_MBOX=y
CONFIG_STM32_IPCC=m
CONFIG_MTK_CMDQ_MBOX=m
CONFIG_SUN6I_MSGBOX=y
# CONFIG_SPRD_MBOX is not set
# CONFIG_QCOM_IPCC is not set
CONFIG_IOMMU_IOVA=m
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y

#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set
# end of Generic IOMMU Pagetable Support

# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
CONFIG_OF_IOMMU=y
# CONFIG_MSM_IOMMU is not set
# CONFIG_OMAP_IOMMU is not set
# CONFIG_ROCKCHIP_IOMMU is not set
CONFIG_SUN50I_IOMMU=y
# CONFIG_EXYNOS_IOMMU is not set
# CONFIG_IPMMU_VMSA is not set
# CONFIG_APPLE_DART is not set
# CONFIG_ARM_SMMU is not set
CONFIG_S390_CCW_IOMMU=y
# CONFIG_S390_AP_IOMMU is not set
# CONFIG_MTK_IOMMU is not set
# CONFIG_MTK_IOMMU_V1 is not set
CONFIG_QCOM_IOMMU=y
CONFIG_SPRD_IOMMU=y

#
# Remoteproc drivers
#
CONFIG_REMOTEPROC=y
# CONFIG_REMOTEPROC_CDEV is not set
# CONFIG_IMX_REMOTEPROC is not set
CONFIG_INGENIC_VPU_RPROC=m
# CONFIG_MTK_SCP is not set
# CONFIG_WKUP_M3_RPROC is not set
# CONFIG_KEYSTONE_REMOTEPROC is not set
CONFIG_ST_REMOTEPROC=y
CONFIG_ST_SLIM_REMOTEPROC=y
# end of Remoteproc drivers

#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_NS=m
CONFIG_RPMSG_QCOM_GLINK=m
CONFIG_RPMSG_QCOM_GLINK_RPM=m
CONFIG_RPMSG_VIRTIO=m
# end of Rpmsg drivers

CONFIG_SOUNDWIRE=m

#
# SoundWire Devices
#

#
# SOC (System On Chip) specific Drivers
#
# CONFIG_OWL_PM_DOMAINS is not set

#
# Amlogic SoC drivers
#
# CONFIG_MESON_CANVAS is not set
CONFIG_MESON_CLK_MEASURE=m
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=m
# CONFIG_MESON_MX_SOCINFO is not set
# end of Amlogic SoC drivers

#
# ASPEED SoC drivers
#
CONFIG_ASPEED_LPC_CTRL=m
# CONFIG_ASPEED_LPC_SNOOP is not set
# CONFIG_ASPEED_P2A_CTRL is not set
CONFIG_ASPEED_SOCINFO=y
# end of ASPEED SoC drivers

# CONFIG_AT91_SOC_ID is not set
# CONFIG_AT91_SOC_SFR is not set

#
# Broadcom SoC drivers
#
CONFIG_BCM2835_POWER=y
CONFIG_SOC_BCM63XX=y
CONFIG_SOC_BRCMSTB=y
CONFIG_BCM63XX_POWER=y
CONFIG_BCM_PMB=y
# end of Broadcom SoC drivers

#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_FSL_MC_DPIO is not set
CONFIG_DPAA2_CONSOLE=m
# CONFIG_FSL_RCPM is not set
# end of NXP/Freescale QorIQ SoC drivers

#
# i.MX SoC drivers
#
CONFIG_IMX_GPCV2_PM_DOMAINS=y
CONFIG_SOC_IMX8M=y
# end of i.MX SoC drivers

#
# IXP4xx SoC drivers
#
CONFIG_IXP4XX_QMGR=m
CONFIG_IXP4XX_NPE=y
# end of IXP4xx SoC drivers

#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=m
# end of Enable LiteX SoC Builder specific drivers

#
# MediaTek SoC drivers
#
CONFIG_MTK_CMDQ=m
# CONFIG_MTK_DEVAPC is not set
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=m
# CONFIG_MTK_SCPSYS is not set
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_MMSYS=y
# end of MediaTek SoC drivers

#
# Qualcomm SoC drivers
#
CONFIG_QCOM_AOSS_QMP=m
CONFIG_QCOM_COMMAND_DB=m
# CONFIG_QCOM_CPR is not set
CONFIG_QCOM_GENI_SE=y
CONFIG_QCOM_GSBI=y
CONFIG_QCOM_LLCC=y
CONFIG_QCOM_OCMEM=m
CONFIG_QCOM_RMTFS_MEM=m
CONFIG_QCOM_RPMH=m
CONFIG_QCOM_RPMHPD=m
# CONFIG_QCOM_SMD_RPM is not set
CONFIG_QCOM_WCNSS_CTRL=m
# end of Qualcomm SoC drivers

CONFIG_SOC_RENESAS=y
CONFIG_RST_RCAR=y
CONFIG_SYSC_RCAR=y
# CONFIG_SYSC_R8A77995 is not set
# CONFIG_SYSC_R8A7794 is not set
CONFIG_SYSC_R8A77990=y
CONFIG_SYSC_R8A7779=y
CONFIG_SYSC_R8A7790=y
# CONFIG_SYSC_R8A7795 is not set
# CONFIG_SYSC_R8A7791 is not set
CONFIG_SYSC_R8A77965=y
# CONFIG_SYSC_R8A77960 is not set
CONFIG_SYSC_R8A77961=y
# CONFIG_SYSC_R8A7792 is not set
# CONFIG_SYSC_R8A77980 is not set
# CONFIG_SYSC_R8A77970 is not set
CONFIG_SYSC_R8A779A0=y
CONFIG_SYSC_RMOBILE=y
CONFIG_SYSC_R8A77470=y
CONFIG_SYSC_R8A7745=y
CONFIG_SYSC_R8A7742=y
# CONFIG_SYSC_R8A7743 is not set
CONFIG_SYSC_R8A774C0=y
# CONFIG_SYSC_R8A774E1 is not set
# CONFIG_SYSC_R8A774A1 is not set
# CONFIG_SYSC_R8A774B1 is not set
CONFIG_ROCKCHIP_GRF=y
# CONFIG_ROCKCHIP_IODOMAIN is not set
# CONFIG_ROCKCHIP_PM_DOMAINS is not set
CONFIG_SOC_SAMSUNG=y
CONFIG_EXYNOS_ASV_ARM=y
CONFIG_EXYNOS_CHIPID=y
CONFIG_EXYNOS_PMU=y
CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
CONFIG_EXYNOS_PM_DOMAINS=y
# CONFIG_EXYNOS_REGULATOR_COUPLER is not set
CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y
# CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER is not set
CONFIG_SOC_TI=y
# CONFIG_KEYSTONE_NAVIGATOR_QMSS is not set
CONFIG_KEYSTONE_NAVIGATOR_DMA=y
# CONFIG_TI_PRUSS is not set
# CONFIG_UX500_SOC_ID is not set
CONFIG_SOC_REALVIEW=y

#
# Xilinx SoC drivers
#
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers

CONFIG_PM_DEVFREQ=y

#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=m
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
CONFIG_DEVFREQ_GOV_USERSPACE=m
CONFIG_DEVFREQ_GOV_PASSIVE=y

#
# DEVFREQ Drivers
#
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
CONFIG_ARM_IMX_BUS_DEVFREQ=m
# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
# CONFIG_ARM_TEGRA_DEVFREQ is not set
CONFIG_ARM_RK3399_DMC_DEVFREQ=m
CONFIG_PM_DEVFREQ_EVENT=y
# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set
CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m
CONFIG_EXTCON=y

#
# Extcon Device Drivers
#
CONFIG_EXTCON_FSA9480=y
# CONFIG_EXTCON_GPIO is not set
CONFIG_EXTCON_MAX3355=m
CONFIG_EXTCON_MAX8997=m
CONFIG_EXTCON_PTN5150=y
# CONFIG_EXTCON_QCOM_SPMI_MISC is not set
CONFIG_EXTCON_RT8973A=y
CONFIG_EXTCON_SM5502=m
# CONFIG_EXTCON_USB_GPIO is not set
CONFIG_EXTCON_USBC_TUSB320=y
CONFIG_MEMORY=y
CONFIG_DDR=y
CONFIG_ARM_PL172_MPMC=y
# CONFIG_ATMEL_SDRAMC is not set
# CONFIG_ATMEL_EBI is not set
CONFIG_BRCMSTB_DPFE=y
# CONFIG_BT1_L2_CTL is not set
# CONFIG_TI_AEMIF is not set
CONFIG_TI_EMIF=m
CONFIG_OMAP_GPMC=y
# CONFIG_OMAP_GPMC_DEBUG is not set
CONFIG_TI_EMIF_SRAM=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_FSL_CORENET_CF=m
# CONFIG_FSL_IFC is not set
CONFIG_JZ4780_NEMC=y
CONFIG_MTK_SMI=m
CONFIG_DA8XX_DDRCTL=y
# CONFIG_PL353_SMC is not set
# CONFIG_RENESAS_RPCIF is not set
# CONFIG_STM32_FMC2_EBI is not set
CONFIG_SAMSUNG_MC=y
CONFIG_EXYNOS5422_DMC=y
CONFIG_EXYNOS_SROM=y
CONFIG_TEGRA_MC=y
# CONFIG_TEGRA20_EMC is not set
CONFIG_TEGRA30_EMC=y
# CONFIG_TEGRA124_EMC is not set
CONFIG_TEGRA210_EMC_TABLE=y
CONFIG_TEGRA210_EMC=y
# CONFIG_IIO is not set
CONFIG_NTB=y
CONFIG_NTB_MSI=y
# CONFIG_NTB_IDT is not set
CONFIG_NTB_EPF=m
# CONFIG_NTB_SWITCHTEC is not set
# CONFIG_NTB_PINGPONG is not set
CONFIG_NTB_TOOL=m
# CONFIG_NTB_PERF is not set
# CONFIG_NTB_MSI_TEST is not set
# CONFIG_NTB_TRANSPORT is not set
# CONFIG_VME_BUS is not set
# CONFIG_PWM is not set

#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=2
CONFIG_ARM_GIC_V2M=y
CONFIG_GIC_NON_BANKED=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
CONFIG_ALPINE_MSI=y
# CONFIG_AL_FIC is not set
CONFIG_BRCMSTB_L2_IRQ=y
CONFIG_DW_APB_ICTL=y
CONFIG_MADERA_IRQ=m
CONFIG_OMAP_IRQCHIP=y
# CONFIG_JCORE_AIC is not set
CONFIG_RENESAS_INTC_IRQPIN=y
# CONFIG_RENESAS_IRQC is not set
# CONFIG_RENESAS_RZA1_IRQC is not set
CONFIG_SL28CPLD_INTC=y
CONFIG_ST_IRQCHIP=y
CONFIG_TS4800_IRQ=m
# CONFIG_XILINX_INTC is not set
CONFIG_IRQ_CROSSBAR=y
CONFIG_KEYSTONE_IRQ=m
# CONFIG_INGENIC_TCU_IRQ is not set
# CONFIG_RENESAS_H8S_INTC is not set
CONFIG_LS_EXTIRQ=y
CONFIG_LS_SCFG_MSI=y
CONFIG_PARTITION_PERCPU=y
CONFIG_IRQ_UNIPHIER_AIDET=y
CONFIG_QCOM_PDC=m
CONFIG_IMX_IRQSTEER=y
# CONFIG_IMX_INTMUX is not set
CONFIG_EXYNOS_IRQ_COMBINER=y
# CONFIG_LOONGSON_PCH_PIC is not set
# CONFIG_LOONGSON_PCH_MSI is not set
CONFIG_MST_IRQ=y
# end of IRQ chip support

CONFIG_IPACK_BUS=m
# CONFIG_BOARD_TPCI200 is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_ATH79=y
# CONFIG_RESET_AXS10X is not set
# CONFIG_RESET_BCM6345 is not set
# CONFIG_RESET_BERLIN is not set
CONFIG_RESET_BRCMSTB=y
# CONFIG_RESET_BRCMSTB_RESCAL is not set
# CONFIG_RESET_HSDK is not set
CONFIG_RESET_IMX7=m
# CONFIG_RESET_INTEL_GW is not set
CONFIG_RESET_K210=y
# CONFIG_RESET_LANTIQ is not set
CONFIG_RESET_LPC18XX=y
CONFIG_RESET_MCHP_SPARX5=y
CONFIG_RESET_MESON=y
# CONFIG_RESET_MESON_AUDIO_ARB is not set
CONFIG_RESET_NPCM=y
# CONFIG_RESET_PISTACHIO is not set
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RESET_RASPBERRYPI=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=m
# CONFIG_RESET_SCMI is not set
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SOCFPGA=y
# CONFIG_RESET_SUNXI is not set
# CONFIG_RESET_TI_SYSCON is not set
CONFIG_RESET_UNIPHIER=m
CONFIG_RESET_UNIPHIER_GLUE=m
# CONFIG_RESET_ZYNQ is not set
CONFIG_STI_RESET_SYSCFG=y
CONFIG_STIH407_RESET=y
CONFIG_COMMON_RESET_HI3660=m
CONFIG_COMMON_RESET_HI6220=m

#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
CONFIG_PHY_LPC18XX_USB_OTG=m
# CONFIG_PHY_PISTACHIO_USB is not set
# CONFIG_PHY_XGENE is not set
# CONFIG_USB_LGM_PHY is not set
# CONFIG_PHY_CAN_TRANSCEIVER is not set
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_SUN6I_MIPI_DPHY=y
# CONFIG_PHY_SUN9I_USB is not set
CONFIG_PHY_SUN50I_USB3=m
CONFIG_PHY_MESON8B_USB2=y
CONFIG_PHY_MESON_GXL_USB2=y
# CONFIG_PHY_MESON_G12A_USB2 is not set
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
CONFIG_PHY_MESON_AXG_PCIE=y
# CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set
# CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set
# CONFIG_PHY_BCM63XX_USBH is not set
# CONFIG_PHY_CYGNUS_PCIE is not set
CONFIG_PHY_BCM_SR_USB=m
# CONFIG_BCM_KONA_USB2_PHY is not set
CONFIG_PHY_BCM_NS_USB2=y
# CONFIG_PHY_NS2_USB_DRD is not set
# CONFIG_PHY_BRCM_SATA is not set
CONFIG_PHY_BRCM_USB=y
CONFIG_PHY_BCM_SR_PCIE=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_CADENCE_DPHY=y
CONFIG_PHY_CADENCE_SIERRA=m
CONFIG_PHY_CADENCE_SALVO=m
CONFIG_PHY_FSL_IMX8MQ_USB=y
CONFIG_PHY_MIXEL_MIPI_DPHY=m
CONFIG_PHY_HI6220_USB=y
CONFIG_PHY_HI3660_USB=y
CONFIG_PHY_HI3670_USB=m
# CONFIG_PHY_HISTB_COMBPHY is not set
CONFIG_PHY_HISI_INNO_USB2=y
# CONFIG_PHY_INGENIC_USB is not set
# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set
# CONFIG_PHY_LANTIQ_RCU_USB2 is not set
# CONFIG_ARMADA375_USBCLUSTER_PHY is not set
CONFIG_PHY_BERLIN_SATA=m
CONFIG_PHY_BERLIN_USB=m
CONFIG_PHY_MVEBU_A3700_COMPHY=m
CONFIG_PHY_MVEBU_A3700_UTMI=y
CONFIG_PHY_MVEBU_A38X_COMPHY=y
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
CONFIG_PHY_MVEBU_CP110_UTMI=y
# CONFIG_PHY_PXA_28NM_HSIC is not set
CONFIG_PHY_PXA_28NM_USB2=y
# CONFIG_PHY_PXA_USB is not set
CONFIG_PHY_MMP3_USB=m
CONFIG_PHY_MMP3_HSIC=y
# CONFIG_PHY_MTK_TPHY is not set
# CONFIG_PHY_MTK_UFS is not set
CONFIG_PHY_MTK_XSPHY=m
# CONFIG_PHY_MTK_HDMI is not set
CONFIG_PHY_MTK_MIPI_DSI=y
CONFIG_PHY_SPARX5_SERDES=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_ATH79_USB is not set
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
CONFIG_PHY_QCOM_IPQ806X_SATA=m
CONFIG_PHY_QCOM_PCIE2=m
# CONFIG_PHY_QCOM_QMP is not set
CONFIG_PHY_QCOM_QUSB2=y
CONFIG_PHY_QCOM_USB_HS=m
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_HSIC is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PHY_QCOM_IPQ806X_USB=m
CONFIG_PHY_MT7621_PCI=y
# CONFIG_PHY_RALINK_USB is not set
CONFIG_PHY_RCAR_GEN3_USB3=y
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
CONFIG_PHY_ROCKCHIP_PCIE=m
# CONFIG_PHY_ROCKCHIP_TYPEC is not set
CONFIG_PHY_EXYNOS_DP_VIDEO=m
CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
CONFIG_PHY_EXYNOS_PCIE=y
# CONFIG_PHY_SAMSUNG_UFS is not set
CONFIG_PHY_SAMSUNG_USB2=y
CONFIG_PHY_EXYNOS4210_USB2=y
CONFIG_PHY_EXYNOS4X12_USB2=y
# CONFIG_PHY_S5PV210_USB2 is not set
CONFIG_PHY_EXYNOS5_USBDRD=m
CONFIG_PHY_UNIPHIER_USB2=m
CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_UNIPHIER_PCIE=y
CONFIG_PHY_UNIPHIER_AHCI=m
CONFIG_PHY_MIPHY28LP=m
CONFIG_PHY_ST_SPEAR1310_MIPHY=y
CONFIG_PHY_ST_SPEAR1340_MIPHY=y
# CONFIG_PHY_STIH407_USB is not set
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PHY_TEGRA194_P2U=y
# CONFIG_PHY_DA8XX_USB is not set
# CONFIG_PHY_DM816X_USB is not set
CONFIG_PHY_AM654_SERDES=y
# CONFIG_PHY_J721E_WIZ is not set
CONFIG_OMAP_CONTROL_PHY=y
# CONFIG_OMAP_USB2 is not set
CONFIG_TI_PIPE3=y
CONFIG_PHY_TUSB1210=m
CONFIG_PHY_INTEL_KEEMBAY_EMMC=y
CONFIG_PHY_INTEL_KEEMBAY_USB=y
CONFIG_PHY_INTEL_LGM_COMBO=y
# CONFIG_PHY_INTEL_LGM_EMMC is not set
CONFIG_PHY_XILINX_ZYNQMP=y
# end of PHY Subsystem

CONFIG_POWERCAP=y
CONFIG_DTPM=y
CONFIG_MCB=y
CONFIG_MCB_PCI=y
CONFIG_MCB_LPC=y

#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCI400_PMU=y
# CONFIG_ARM_CCI5xx_PMU is not set
# CONFIG_ARM_CCN is not set
CONFIG_ARM_PMU=y
CONFIG_FSL_IMX8_DDR_PMU=y
CONFIG_ARM_DMC620_PMU=m
# end of Performance monitor support

# CONFIG_RAS is not set
CONFIG_USB4=y
CONFIG_USB4_DEBUGFS_WRITE=y
# CONFIG_USB4_KUNIT_TEST is not set
# CONFIG_USB4_DMA_TEST is not set

#
# Android
#
# CONFIG_ANDROID is not set
# end of Android

# CONFIG_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_IMX_IIM=m
# CONFIG_NVMEM_IMX_OCOTP is not set
CONFIG_JZ4780_EFUSE=y
# CONFIG_NVMEM_LPC18XX_EEPROM is not set
CONFIG_NVMEM_LPC18XX_OTP=y
# CONFIG_NVMEM_MXS_OCOTP is not set
# CONFIG_MTK_EFUSE is not set
# CONFIG_NVMEM_NINTENDO_OTP is not set
# CONFIG_QCOM_QFPROM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
# CONFIG_ROCKCHIP_EFUSE is not set
CONFIG_ROCKCHIP_OTP=y
# CONFIG_NVMEM_BCM_OCOTP is not set
# CONFIG_NVMEM_STM32_ROMEM is not set
CONFIG_UNIPHIER_EFUSE=y
CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_MESON_MX_EFUSE=y
CONFIG_NVMEM_SNVS_LPGPR=y
# CONFIG_RAVE_SP_EEPROM is not set
CONFIG_SC27XX_EFUSE=y
CONFIG_SPRD_EFUSE=y
CONFIG_NVMEM_RMEM=y
CONFIG_NVMEM_BRCM_NVRAM=y

#
# HW tracing support
#
CONFIG_STM=m
# CONFIG_STM_PROTO_BASIC is not set
CONFIG_STM_PROTO_SYS_T=m
CONFIG_STM_DUMMY=m
CONFIG_STM_SOURCE_CONSOLE=m
CONFIG_STM_SOURCE_HEARTBEAT=m
CONFIG_STM_SOURCE_FTRACE=m
CONFIG_INTEL_TH=m
CONFIG_INTEL_TH_PCI=m
CONFIG_INTEL_TH_GTH=m
# CONFIG_INTEL_TH_STH is not set
CONFIG_INTEL_TH_MSU=m
CONFIG_INTEL_TH_PTI=m
# CONFIG_INTEL_TH_DEBUG is not set
# end of HW tracing support

CONFIG_FPGA=m
CONFIG_FPGA_MGR_SOCFPGA=m
# CONFIG_FPGA_MGR_SOCFPGA_A10 is not set
CONFIG_ALTERA_PR_IP_CORE=m
# CONFIG_ALTERA_PR_IP_CORE_PLAT is not set
# CONFIG_FPGA_MGR_ALTERA_CVP is not set
# CONFIG_FPGA_MGR_ZYNQ_FPGA is not set
# CONFIG_FPGA_BRIDGE is not set
# CONFIG_FPGA_DFL is not set
# CONFIG_FPGA_MGR_ZYNQMP_FPGA is not set
CONFIG_FPGA_MGR_VERSAL_FPGA=m
CONFIG_FSI=m
CONFIG_FSI_NEW_DEV_NODE=y
CONFIG_FSI_MASTER_GPIO=m
# CONFIG_FSI_MASTER_HUB is not set
CONFIG_FSI_MASTER_ASPEED=m
# CONFIG_FSI_SCOM is not set
CONFIG_FSI_SBEFIFO=m
CONFIG_FSI_OCC=m
CONFIG_TEE=y

#
# TEE drivers
#
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
# end of TEE drivers

CONFIG_MULTIPLEXER=y

#
# Multiplexer drivers
#
CONFIG_MUX_ADG792A=m
# CONFIG_MUX_GPIO is not set
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers

CONFIG_PM_OPP=y
# CONFIG_SIOX is not set
CONFIG_SLIMBUS=y
# CONFIG_SLIM_QCOM_CTRL is not set
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_IMX=m
# CONFIG_INTERCONNECT_IMX8MM is not set
CONFIG_INTERCONNECT_IMX8MN=m
# CONFIG_INTERCONNECT_IMX8MQ is not set
# CONFIG_INTERCONNECT_QCOM is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_SAMSUNG=y
CONFIG_INTERCONNECT_EXYNOS=y
# CONFIG_COUNTER is not set
CONFIG_MOST=y
# CONFIG_MOST_USB_HDM is not set
CONFIG_MOST_CDEV=y
# end of Device Drivers

#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
# CONFIG_VALIDATE_FS_PARSER is not set
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
# CONFIG_FILE_LOCKING is not set
# CONFIG_FS_ENCRYPTION is not set
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
# CONFIG_INOTIFY_USER is not set
# CONFIG_FANOTIFY is not set
CONFIG_QUOTA=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=m
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=m
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=y
CONFIG_AUTOFS_FS=y
# CONFIG_FUSE_FS is not set
# CONFIG_OVERLAY_FS is not set

#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_SYSCTL is not set
# CONFIG_PROC_PAGE_MONITOR is not set
# CONFIG_PROC_CHILDREN is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
CONFIG_TMPFS_XATTR=y
CONFIG_MEMFD_CREATE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems

# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
CONFIG_NLS_CODEPAGE_857=m
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
CONFIG_NLS_CODEPAGE_862=y
CONFIG_NLS_CODEPAGE_863=y
CONFIG_NLS_CODEPAGE_864=m
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
CONFIG_NLS_CODEPAGE_869=y
CONFIG_NLS_CODEPAGE_936=y
CONFIG_NLS_CODEPAGE_950=y
# CONFIG_NLS_CODEPAGE_932 is not set
CONFIG_NLS_CODEPAGE_949=y
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=y
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
# CONFIG_NLS_ISO8859_5 is not set
CONFIG_NLS_ISO8859_6=m
# CONFIG_NLS_ISO8859_7 is not set
CONFIG_NLS_ISO8859_9=y
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=m
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
CONFIG_NLS_MAC_CELTIC=m
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=m
# CONFIG_NLS_MAC_CYRILLIC is not set
CONFIG_NLS_MAC_GAELIC=y
CONFIG_NLS_MAC_GREEK=m
# CONFIG_NLS_MAC_ICELAND is not set
CONFIG_NLS_MAC_INUIT=m
CONFIG_NLS_MAC_ROMANIAN=y
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=m
# CONFIG_UNICODE is not set
CONFIG_IO_WQ=y
# end of File systems

#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_REQUEST_CACHE=y
# CONFIG_PERSISTENT_KEYRINGS is not set
CONFIG_TRUSTED_KEYS=m
CONFIG_ENCRYPTED_KEYS=m
CONFIG_KEY_DH_OPERATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
# CONFIG_SECURITY_NETWORK is not set
CONFIG_SECURITY_PATH=y
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
CONFIG_HARDENED_USERCOPY_FALLBACK=y
# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
CONFIG_FORTIFY_SOURCE=y
CONFIG_STATIC_USERMODEHELPER=y
CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper"
CONFIG_SECURITY_YAMA=y
CONFIG_SECURITY_SAFESETID=y
# CONFIG_SECURITY_LOCKDOWN_LSM is not set
CONFIG_SECURITY_LANDLOCK=y
# CONFIG_INTEGRITY is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"

#
# Kernel hardening options
#

#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
# CONFIG_INIT_STACK_NONE is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
CONFIG_INIT_STACK_ALL_PATTERN=y
# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
CONFIG_ZERO_CALL_USED_REGS=y
# end of Memory initialization
# end of Kernel hardening options
# end of Security options

CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=m
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_SIMD=m

#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=m
# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_CURVE25519=m

#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=m
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_SEQIV=m
# CONFIG_CRYPTO_ECHAINIV is not set

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
# CONFIG_CRYPTO_OFB is not set
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
# CONFIG_CRYPTO_ADIANTUM is not set
CONFIG_CRYPTO_ESSIV=y

#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=m
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32=y
# CONFIG_CRYPTO_XXHASH is not set
CONFIG_CRYPTO_BLAKE2B=y
# CONFIG_CRYPTO_BLAKE2S is not set
CONFIG_CRYPTO_CRCT10DIF=m
CONFIG_CRYPTO_GHASH=y
# CONFIG_CRYPTO_POLY1305 is not set
CONFIG_CRYPTO_MD4=m
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_SM3=m
CONFIG_CRYPTO_STREEBOG=y
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=m
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_SERPENT is not set
CONFIG_CRYPTO_SM4=m
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y

#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_842 is not set
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=y
# CONFIG_CRYPTO_ZSTD is not set

#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
# CONFIG_CRYPTO_DRBG_HASH is not set
# CONFIG_CRYPTO_DRBG_CTR is not set
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_HASH_INFO=y

#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
# CONFIG_CRYPTO_LIB_BLAKE2S is not set
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CHACHA=m
CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
CONFIG_CRYPTO_LIB_CURVE25519=y
CONFIG_CRYPTO_LIB_DES=m
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m
CONFIG_CRYPTO_LIB_POLY1305=m
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_SM4=m
# CONFIG_CRYPTO_HW is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
# CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=y
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set

#
# Certificates for signature checking
#
CONFIG_MODULE_SIG_KEY="certs/signing_key.pem"
CONFIG_MODULE_SIG_KEY_TYPE_RSA=y
# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
CONFIG_SYSTEM_EXTRA_CERTIFICATE=y
CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096
CONFIG_SECONDARY_TRUSTED_KEYRING=y
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
# end of Certificates for signature checking

CONFIG_BINARY_PRINTF=y

#
# Library routines
#
CONFIG_LINEAR_RANGES=y
CONFIG_PACKING=y
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=y
# CONFIG_PRIME_NUMBERS is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_STMP_DEVICE=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=m
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
CONFIG_CRC32_SELFTEST=y
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=y
CONFIG_CRC4=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=m
CONFIG_CRC8=y
CONFIG_XXHASH=y
CONFIG_RANDOM32_SELFTEST=y
CONFIG_ZLIB_INFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=m
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
# CONFIG_XZ_DEC_X86 is not set
# CONFIG_XZ_DEC_POWERPC is not set
# CONFIG_XZ_DEC_IA64 is not set
# CONFIG_XZ_DEC_ARM is not set
# CONFIG_XZ_DEC_ARMTHUMB is not set
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_XZ_DEC_TEST=m
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_DECOMPRESS_ZSTD=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_SWIOTLB=y
# CONFIG_DMA_RESTRICTED_POOL is not set
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_API_DEBUG=y
# CONFIG_DMA_API_DEBUG_SG is not set
CONFIG_DMA_MAP_BENCHMARK=y
CONFIG_SGL_ALLOC=y
# CONFIG_CPUMASK_OFFSTACK is not set
CONFIG_GLOB=y
CONFIG_GLOB_SELFTEST=y
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=y
CONFIG_STACKDEPOT=y
CONFIG_STACK_HASH_ORDER=20
# CONFIG_PARMAN is not set
# CONFIG_OBJAGG is not set
# end of Library routines

CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_ASN1_ENCODER=m

#
# Kernel hacking
#

#
# printk and dmesg options
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_PRINTK_CALLER is not set
CONFIG_STACKTRACE_BUILD_ID=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
CONFIG_DYNAMIC_DEBUG_CORE=y
CONFIG_SYMBOLIC_ERRNAME=y
CONFIG_DEBUG_BUGVERBOSE=y
# end of printk and dmesg options

#
# Compile-time checks and compiler options
#
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
# CONFIG_VMLINUX_MAP is not set
CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
# end of Compile-time checks and compiler options

#
# Generic Kernel Debugging Instruments
#
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
CONFIG_DEBUG_FS_DISALLOW_MOUNT=y
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_KGDB=y
# CONFIG_KGDB_HONOUR_BLOCKLIST is not set
CONFIG_KGDB_TESTS=y
CONFIG_KGDB_TESTS_ON_BOOT=y
CONFIG_KGDB_TESTS_BOOT_STRING="V1F100"
CONFIG_KGDB_KDB=y
CONFIG_KDB_DEFAULT_ENABLE=0x1
CONFIG_KDB_CONTINUE_CATASTROPHIC=0
# CONFIG_UBSAN is not set
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments

CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_MISC is not set

#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
CONFIG_DEBUG_PAGEALLOC=y
CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y
CONFIG_PAGE_OWNER=y
CONFIG_PAGE_POISONING=y
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_WX is not set
CONFIG_DEBUG_OBJECTS=y
# CONFIG_DEBUG_OBJECTS_SELFTEST is not set
CONFIG_DEBUG_OBJECTS_FREE=y
CONFIG_DEBUG_OBJECTS_TIMERS=y
CONFIG_DEBUG_OBJECTS_WORK=y
# CONFIG_DEBUG_OBJECTS_RCU_HEAD is not set
# CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER is not set
CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
CONFIG_SCHED_STACK_END_CHECK=y
# CONFIG_DEBUG_VM is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_DEBUG_PER_CPU_MAPS=y
# CONFIG_DEBUG_KMAP_LOCAL is not set
# CONFIG_DEBUG_HIGHMEM is not set
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
# CONFIG_KASAN is not set
# end of Memory Debugging

# CONFIG_DEBUG_SHIRQ is not set

#
# Debug Oops, Lockups and Hangs
#
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=0
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_DETECT_HUNG_TASK is not set
# CONFIG_WQ_WATCHDOG is not set
CONFIG_TEST_LOCKUP=m
# end of Debug Oops, Lockups and Hangs

#
# Scheduler Debugging
#
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
# end of Scheduler Debugging

CONFIG_DEBUG_TIMEKEEPING=y
CONFIG_DEBUG_PREEMPT=y

#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_PROVE_LOCKING=y
CONFIG_PROVE_RAW_LOCK_NESTING=y
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
CONFIG_DEBUG_LOCKDEP=y
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=y
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_SCF_TORTURE_TEST=m
# end of Lock Debugging (spinlocks, mutexes, etc...)

CONFIG_TRACE_IRQFLAGS=y
CONFIG_DEBUG_IRQFLAGS=y
CONFIG_STACKTRACE=y
CONFIG_WARN_ALL_UNSEEDED_RANDOM=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_KOBJECT_RELEASE=y

#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_DEBUG_NOTIFIERS=y
CONFIG_BUG_ON_DATA_CORRUPTION=y
# end of Debug kernel data structures

# CONFIG_DEBUG_CREDENTIALS is not set

#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
CONFIG_PROVE_RCU_LIST=y
CONFIG_TORTURE_TEST=y
# CONFIG_RCU_SCALE_TEST is not set
CONFIG_RCU_TORTURE_TEST=y
CONFIG_RCU_REF_SCALE_TEST=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_EQS_DEBUG=y
# CONFIG_RCU_STRICT_GRACE_PERIOD is not set
# end of RCU Debugging

CONFIG_DEBUG_WQ_FORCE_RR_CPU=y
CONFIG_CPU_HOTPLUG_STATE_CONTROL=y
CONFIG_LATENCYTOP=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACER_MAX_TRACE=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_PREEMPTIRQ_TRACEPOINTS=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
CONFIG_BOOTTIME_TRACING=y
CONFIG_FUNCTION_TRACER=y
# CONFIG_DYNAMIC_FTRACE is not set
CONFIG_FUNCTION_PROFILER=y
# CONFIG_STACK_TRACER is not set
CONFIG_TRACE_PREEMPT_TOGGLE=y
CONFIG_IRQSOFF_TRACER=y
CONFIG_PREEMPT_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_HWLAT_TRACER=y
# CONFIG_OSNOISE_TRACER is not set
# CONFIG_TIMERLAT_TRACER is not set
CONFIG_FTRACE_SYSCALLS=y
CONFIG_TRACER_SNAPSHOT=y
CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_KPROBE_EVENTS is not set
CONFIG_UPROBE_EVENTS=y
CONFIG_DYNAMIC_EVENTS=y
CONFIG_PROBE_EVENTS=y
CONFIG_TRACING_MAP=y
CONFIG_SYNTH_EVENTS=y
CONFIG_HIST_TRIGGERS=y
CONFIG_TRACE_EVENT_INJECT=y
CONFIG_TRACEPOINT_BENCHMARK=y
CONFIG_RING_BUFFER_BENCHMARK=m
CONFIG_TRACE_EVAL_MAP_FILE=y
CONFIG_FTRACE_RECORD_RECURSION=y
CONFIG_FTRACE_RECORD_RECURSION_SIZE=128
# CONFIG_RING_BUFFER_RECORD_RECURSION is not set
# CONFIG_GCOV_PROFILE_FTRACE is not set
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS=y
CONFIG_PREEMPTIRQ_DELAY_TEST=m
CONFIG_SYNTH_EVENT_GEN_TEST=m
# CONFIG_HIST_TRIGGERS_DEBUG is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set

#
# arm Debugging
#
CONFIG_ARM_PTDUMP_CORE=y
CONFIG_ARM_PTDUMP_DEBUGFS=y
CONFIG_UNWINDER_ARM=y
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
CONFIG_DEBUG_LL=y
CONFIG_DEBUG_ALPINE_UART0=y
# CONFIG_DEBUG_BCM2836 is not set
# CONFIG_DEBUG_BCM_5301X is not set
# CONFIG_DEBUG_BCM_IPROC_UART3 is not set
# CONFIG_DEBUG_BERLIN_UART is not set
# CONFIG_DEBUG_DIGICOLOR_UA0 is not set
# CONFIG_DEBUG_IMX53_UART is not set
# CONFIG_DEBUG_IMX6Q_UART is not set
# CONFIG_DEBUG_IMX6SL_UART is not set
# CONFIG_DEBUG_IMX6SX_UART is not set
# CONFIG_DEBUG_KEYSTONE_UART0 is not set
# CONFIG_DEBUG_KEYSTONE_UART1 is not set
# CONFIG_DEBUG_MSTARV7_PMUART is not set
# CONFIG_DEBUG_MT6589_UART0 is not set
# CONFIG_DEBUG_MT8127_UART0 is not set
# CONFIG_DEBUG_MT8135_UART3 is not set
# CONFIG_DEBUG_OMAP2UART1 is not set
# CONFIG_DEBUG_OMAP2UART2 is not set
# CONFIG_DEBUG_OMAP2UART3 is not set
# CONFIG_DEBUG_OMAP3UART3 is not set
# CONFIG_DEBUG_OMAP4UART3 is not set
# CONFIG_DEBUG_OMAP3UART4 is not set
# CONFIG_DEBUG_OMAP4UART4 is not set
# CONFIG_DEBUG_TI81XXUART1 is not set
# CONFIG_DEBUG_TI81XXUART2 is not set
# CONFIG_DEBUG_TI81XXUART3 is not set
# CONFIG_DEBUG_AM33XXUART1 is not set
# CONFIG_DEBUG_ZOOM_UART is not set
# CONFIG_DEBUG_QCOM_UARTDM is not set
# CONFIG_DEBUG_REALVIEW_STD_PORT is not set
# CONFIG_DEBUG_S3C_UART0 is not set
# CONFIG_DEBUG_S3C_UART1 is not set
# CONFIG_DEBUG_S3C_UART2 is not set
# CONFIG_DEBUG_S3C_UART3 is not set
# CONFIG_DEBUG_SOCFPGA_UART0 is not set
# CONFIG_DEBUG_SOCFPGA_ARRIA10_UART1 is not set
# CONFIG_DEBUG_SOCFPGA_CYCLONE5_UART1 is not set
# CONFIG_DEBUG_STIH41X_ASC2 is not set
# CONFIG_DEBUG_STIH41X_SBC_ASC1 is not set
# CONFIG_DEBUG_STIH418_SBC_ASC0 is not set
# CONFIG_DEBUG_UX500_UART is not set
# CONFIG_DEBUG_ZYNQ_UART0 is not set
# CONFIG_DEBUG_ZYNQ_UART1 is not set
# CONFIG_DEBUG_ICEDCC is not set
# CONFIG_DEBUG_SEMIHOSTING is not set
# CONFIG_DEBUG_LL_UART_8250 is not set
# CONFIG_DEBUG_LL_UART_PL01X is not set
CONFIG_DEBUG_UART_FLOW_CONTROL=y
CONFIG_DEBUG_LL_INCLUDE="debug/palmchip.S"
CONFIG_DEBUG_UART_8250=y
CONFIG_DEBUG_UART_PHYS=0xfd883000
CONFIG_DEBUG_UART_VIRT=0xfd883000
CONFIG_DEBUG_UART_8250_SHIFT=2
# CONFIG_DEBUG_UART_8250_WORD is not set
CONFIG_DEBUG_UART_8250_PALMCHIP=y
# CONFIG_DEBUG_UNCOMPRESS is not set
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_EARLY_PRINTK=y
# CONFIG_ARM_KPROBES_TEST is not set
CONFIG_PID_IN_CONTEXTIDR=y
CONFIG_CORESIGHT=m
CONFIG_CORESIGHT_LINKS_AND_SINKS=m
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
# CONFIG_CORESIGHT_CATU is not set
# CONFIG_CORESIGHT_SINK_TPIU is not set
CONFIG_CORESIGHT_SINK_ETBV10=m
CONFIG_CORESIGHT_SOURCE_ETM3X=m
CONFIG_CORESIGHT_STM=m
CONFIG_CORESIGHT_CPU_DEBUG=m
CONFIG_CORESIGHT_CTI=m
CONFIG_CORESIGHT_CTI_INTEGRATION_REGS=y
# end of arm Debugging

#
# Kernel Testing and Coverage
#
CONFIG_KUNIT=y
# CONFIG_KUNIT_DEBUGFS is not set
CONFIG_KUNIT_TEST=y
CONFIG_KUNIT_EXAMPLE_TEST=m
# CONFIG_KUNIT_ALL_TESTS is not set
CONFIG_NOTIFIER_ERROR_INJECTION=y
CONFIG_PM_NOTIFIER_ERROR_INJECT=m
CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m
CONFIG_FAULT_INJECTION=y
# CONFIG_FAILSLAB is not set
# CONFIG_FAIL_PAGE_ALLOC is not set
CONFIG_FAULT_INJECTION_USERCOPY=y
# CONFIG_FAIL_FUTEX is not set
CONFIG_FAULT_INJECTION_DEBUG_FS=y
CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_KCOV=y
CONFIG_KCOV_ENABLE_COMPARISONS=y
CONFIG_KCOV_INSTRUMENT_ALL=y
CONFIG_KCOV_IRQ_AREA_SIZE=0x40000
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
# CONFIG_MEMTEST is not set
# end of Kernel Testing and Coverage

CONFIG_WARN_MISSING_DOCUMENTS=y
CONFIG_WARN_ABI_ERRORS=y
# end of Kernel hacking

^ permalink raw reply	[flat|nested] 3+ messages in thread

* drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'
@ 2022-05-02  3:35 kernel test robot
  0 siblings, 0 replies; 3+ messages in thread
From: kernel test robot @ 2022-05-02  3:35 UTC (permalink / raw)
  To: kbuild

[-- Attachment #1: Type: text/plain, Size: 40020 bytes --]

CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
CC: linux-kernel(a)vger.kernel.org
TO: Linus Walleij <linus.walleij@linaro.org>
CC: Stephen Boyd <sboyd@kernel.org>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   672c0c5173427e6b3e2a9bbb7be51ceeec78093a
commit: b14cbdfd467d1e505ad8e03f94e18b3cffc37043 clk: ux500: Add driver for the reset portions of PRCC
date:   6 months ago
:::::: branch date: 6 hours ago
:::::: commit date: 6 months ago
config: arm-randconfig-m031-20220427 (https://download.01.org/0day-ci/archive/20220502/202205021108.NpjPDRkt-lkp(a)intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc'

vim +/rstc +548 drivers/clk/ux500/u8500_of_clk.c

b4bdc81b5b234b Lee Jones     2013-07-22   48  
269f1aac1410d2 Arnd Bergmann 2016-06-20   49  static void u8500_clk_init(struct device_node *np)
82b0f4b7c576d2 Lee Jones     2013-09-17   50  {
82b0f4b7c576d2 Lee Jones     2013-09-17   51  	struct prcmu_fw_version *fw_version;
dec759d8ef01b3 Lee Jones     2013-09-17   52  	struct device_node *child = NULL;
82b0f4b7c576d2 Lee Jones     2013-09-17   53  	const char *sgaclk_parent = NULL;
4e33466095e045 Lee Jones     2013-09-17   54  	struct clk *clk, *rtc_clk, *twd_clk;
5dc0fe199b3589 Linus Walleij 2015-07-30   55  	u32 bases[CLKRST_MAX];
b14cbdfd467d1e Linus Walleij 2021-09-21   56  	struct u8500_prcc_reset *rstc;
5dc0fe199b3589 Linus Walleij 2015-07-30   57  	int i;
82b0f4b7c576d2 Lee Jones     2013-09-17   58  
b14cbdfd467d1e Linus Walleij 2021-09-21   59  	/*
b14cbdfd467d1e Linus Walleij 2021-09-21   60  	 * We allocate the reset controller here so that we can fill in the
b14cbdfd467d1e Linus Walleij 2021-09-21   61  	 * base addresses properly and pass to the reset controller init
b14cbdfd467d1e Linus Walleij 2021-09-21   62  	 * function later on.
b14cbdfd467d1e Linus Walleij 2021-09-21   63  	 */
b14cbdfd467d1e Linus Walleij 2021-09-21   64  	rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
b14cbdfd467d1e Linus Walleij 2021-09-21   65  	if (!rstc)
b14cbdfd467d1e Linus Walleij 2021-09-21   66  		return;
b14cbdfd467d1e Linus Walleij 2021-09-21   67  
5dc0fe199b3589 Linus Walleij 2015-07-30   68  	for (i = 0; i < ARRAY_SIZE(bases); i++) {
5dc0fe199b3589 Linus Walleij 2015-07-30   69  		struct resource r;
5dc0fe199b3589 Linus Walleij 2015-07-30   70  
5dc0fe199b3589 Linus Walleij 2015-07-30   71  		if (of_address_to_resource(np, i, &r))
5dc0fe199b3589 Linus Walleij 2015-07-30   72  			/* Not much choice but to continue */
5dc0fe199b3589 Linus Walleij 2015-07-30   73  			pr_err("failed to get CLKRST %d base address\n",
5dc0fe199b3589 Linus Walleij 2015-07-30   74  			       i + 1);
5dc0fe199b3589 Linus Walleij 2015-07-30   75  		bases[i] = r.start;
b14cbdfd467d1e Linus Walleij 2021-09-21   76  		rstc->phy_base[i] = r.start;
5dc0fe199b3589 Linus Walleij 2015-07-30   77  	}
dec759d8ef01b3 Lee Jones     2013-09-17   78  
82b0f4b7c576d2 Lee Jones     2013-09-17   79  	/* Clock sources */
82b0f4b7c576d2 Lee Jones     2013-09-17   80  	clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
66f4ae777d0c2c Stephen Boyd  2016-03-01   81  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   82  	prcmu_clk[PRCMU_PLLSOC0] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   83  
82b0f4b7c576d2 Lee Jones     2013-09-17   84  	clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
66f4ae777d0c2c Stephen Boyd  2016-03-01   85  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   86  	prcmu_clk[PRCMU_PLLSOC1] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   87  
82b0f4b7c576d2 Lee Jones     2013-09-17   88  	clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
66f4ae777d0c2c Stephen Boyd  2016-03-01   89  				CLK_IGNORE_UNUSED);
f9fcb8e8c8f40c Lee Jones     2013-09-17   90  	prcmu_clk[PRCMU_PLLDDR] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17   91  
82b0f4b7c576d2 Lee Jones     2013-09-17   92  	/* FIXME: Add sys, ulp and int clocks here. */
82b0f4b7c576d2 Lee Jones     2013-09-17   93  
d625a730675dec Lee Jones     2013-09-17   94  	rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
66f4ae777d0c2c Stephen Boyd  2016-03-01   95  				CLK_IGNORE_UNUSED,
82b0f4b7c576d2 Lee Jones     2013-09-17   96  				32768);
82b0f4b7c576d2 Lee Jones     2013-09-17   97  
82b0f4b7c576d2 Lee Jones     2013-09-17   98  	/* PRCMU clocks */
82b0f4b7c576d2 Lee Jones     2013-09-17   99  	fw_version = prcmu_get_fw_version();
82b0f4b7c576d2 Lee Jones     2013-09-17  100  	if (fw_version != NULL) {
82b0f4b7c576d2 Lee Jones     2013-09-17  101  		switch (fw_version->project) {
82b0f4b7c576d2 Lee Jones     2013-09-17  102  		case PRCMU_FW_PROJECT_U8500_C2:
9050ad816f5205 Linus Walleij 2021-08-02  103  		case PRCMU_FW_PROJECT_U8500_SSG1:
82b0f4b7c576d2 Lee Jones     2013-09-17  104  		case PRCMU_FW_PROJECT_U8520:
82b0f4b7c576d2 Lee Jones     2013-09-17  105  		case PRCMU_FW_PROJECT_U8420:
248fdcc77a35df Linus Walleij 2019-12-17  106  		case PRCMU_FW_PROJECT_U8420_SYSCLK:
9050ad816f5205 Linus Walleij 2021-08-02  107  		case PRCMU_FW_PROJECT_U8500_SSG2:
82b0f4b7c576d2 Lee Jones     2013-09-17  108  			sgaclk_parent = "soc0_pll";
82b0f4b7c576d2 Lee Jones     2013-09-17  109  			break;
82b0f4b7c576d2 Lee Jones     2013-09-17  110  		default:
82b0f4b7c576d2 Lee Jones     2013-09-17  111  			break;
82b0f4b7c576d2 Lee Jones     2013-09-17  112  		}
82b0f4b7c576d2 Lee Jones     2013-09-17  113  	}
82b0f4b7c576d2 Lee Jones     2013-09-17  114  
82b0f4b7c576d2 Lee Jones     2013-09-17  115  	if (sgaclk_parent)
82b0f4b7c576d2 Lee Jones     2013-09-17  116  		clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
82b0f4b7c576d2 Lee Jones     2013-09-17  117  					PRCMU_SGACLK, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  118  	else
66f4ae777d0c2c Stephen Boyd  2016-03-01  119  		clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  120  	prcmu_clk[PRCMU_SGACLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  121  
66f4ae777d0c2c Stephen Boyd  2016-03-01  122  	clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  123  	prcmu_clk[PRCMU_UARTCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  124  
66f4ae777d0c2c Stephen Boyd  2016-03-01  125  	clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  126  	prcmu_clk[PRCMU_MSP02CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  127  
66f4ae777d0c2c Stephen Boyd  2016-03-01  128  	clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  129  	prcmu_clk[PRCMU_MSP1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  130  
66f4ae777d0c2c Stephen Boyd  2016-03-01  131  	clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  132  	prcmu_clk[PRCMU_I2CCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  133  
66f4ae777d0c2c Stephen Boyd  2016-03-01  134  	clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  135  	prcmu_clk[PRCMU_SLIMCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  136  
66f4ae777d0c2c Stephen Boyd  2016-03-01  137  	clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  138  	prcmu_clk[PRCMU_PER1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  139  
66f4ae777d0c2c Stephen Boyd  2016-03-01  140  	clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  141  	prcmu_clk[PRCMU_PER2CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  142  
66f4ae777d0c2c Stephen Boyd  2016-03-01  143  	clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  144  	prcmu_clk[PRCMU_PER3CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  145  
66f4ae777d0c2c Stephen Boyd  2016-03-01  146  	clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  147  	prcmu_clk[PRCMU_PER5CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  148  
66f4ae777d0c2c Stephen Boyd  2016-03-01  149  	clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  150  	prcmu_clk[PRCMU_PER6CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  151  
66f4ae777d0c2c Stephen Boyd  2016-03-01  152  	clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  153  	prcmu_clk[PRCMU_PER7CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  154  
82b0f4b7c576d2 Lee Jones     2013-09-17  155  	clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  156  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  157  	prcmu_clk[PRCMU_LCDCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  158  
66f4ae777d0c2c Stephen Boyd  2016-03-01  159  	clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  160  	prcmu_clk[PRCMU_BMLCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  161  
82b0f4b7c576d2 Lee Jones     2013-09-17  162  	clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  163  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  164  	prcmu_clk[PRCMU_HSITXCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  165  
82b0f4b7c576d2 Lee Jones     2013-09-17  166  	clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  167  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  168  	prcmu_clk[PRCMU_HSIRXCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  169  
82b0f4b7c576d2 Lee Jones     2013-09-17  170  	clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  171  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  172  	prcmu_clk[PRCMU_HDMICLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  173  
66f4ae777d0c2c Stephen Boyd  2016-03-01  174  	clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  175  	prcmu_clk[PRCMU_APEATCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  176  
a6ae41b54cb077 Linus Walleij 2015-04-20  177  	clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  178  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  179  	prcmu_clk[PRCMU_APETRACECLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  180  
66f4ae777d0c2c Stephen Boyd  2016-03-01  181  	clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  182  	prcmu_clk[PRCMU_MCDECLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  183  
66f4ae777d0c2c Stephen Boyd  2016-03-01  184  	clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  185  	prcmu_clk[PRCMU_IPI2CCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  186  
66f4ae777d0c2c Stephen Boyd  2016-03-01  187  	clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  188  	prcmu_clk[PRCMU_DSIALTCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  189  
66f4ae777d0c2c Stephen Boyd  2016-03-01  190  	clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  191  	prcmu_clk[PRCMU_DMACLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  192  
66f4ae777d0c2c Stephen Boyd  2016-03-01  193  	clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  194  	prcmu_clk[PRCMU_B2R2CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  195  
82b0f4b7c576d2 Lee Jones     2013-09-17  196  	clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
66f4ae777d0c2c Stephen Boyd  2016-03-01  197  				CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  198  	prcmu_clk[PRCMU_TVCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  199  
66f4ae777d0c2c Stephen Boyd  2016-03-01  200  	clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  201  	prcmu_clk[PRCMU_SSPCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  202  
66f4ae777d0c2c Stephen Boyd  2016-03-01  203  	clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  204  	prcmu_clk[PRCMU_RNGCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  205  
66f4ae777d0c2c Stephen Boyd  2016-03-01  206  	clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  207  	prcmu_clk[PRCMU_UICCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  208  
66f4ae777d0c2c Stephen Boyd  2016-03-01  209  	clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
f9fcb8e8c8f40c Lee Jones     2013-09-17  210  	prcmu_clk[PRCMU_TIMCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  211  
689a318c166774 Linus Walleij 2017-01-13  212  	clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
689a318c166774 Linus Walleij 2017-01-13  213  	prcmu_clk[PRCMU_SYSCLK] = clk;
689a318c166774 Linus Walleij 2017-01-13  214  
82b0f4b7c576d2 Lee Jones     2013-09-17  215  	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
66f4ae777d0c2c Stephen Boyd  2016-03-01  216  					100000000, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  217  	prcmu_clk[PRCMU_SDMMCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  218  
82b0f4b7c576d2 Lee Jones     2013-09-17  219  	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  220  				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  221  	prcmu_clk[PRCMU_PLLDSI] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  222  
82b0f4b7c576d2 Lee Jones     2013-09-17  223  	clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
82b0f4b7c576d2 Lee Jones     2013-09-17  224  				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  225  	prcmu_clk[PRCMU_DSI0CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  226  
82b0f4b7c576d2 Lee Jones     2013-09-17  227  	clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
82b0f4b7c576d2 Lee Jones     2013-09-17  228  				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  229  	prcmu_clk[PRCMU_DSI1CLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  230  
82b0f4b7c576d2 Lee Jones     2013-09-17  231  	clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  232  				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  233  	prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  234  
82b0f4b7c576d2 Lee Jones     2013-09-17  235  	clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  236  				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  237  	prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  238  
82b0f4b7c576d2 Lee Jones     2013-09-17  239  	clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
82b0f4b7c576d2 Lee Jones     2013-09-17  240  				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
f9fcb8e8c8f40c Lee Jones     2013-09-17  241  	prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  242  
82b0f4b7c576d2 Lee Jones     2013-09-17  243  	clk = clk_reg_prcmu_scalable_rate("armss", NULL,
66f4ae777d0c2c Stephen Boyd  2016-03-01  244  				PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
257015a20c92a4 Lee Jones     2013-09-18  245  	prcmu_clk[PRCMU_ARMSS] = clk;
82b0f4b7c576d2 Lee Jones     2013-09-17  246  
4e33466095e045 Lee Jones     2013-09-17  247  	twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
82b0f4b7c576d2 Lee Jones     2013-09-17  248  				CLK_IGNORE_UNUSED, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  249  
82b0f4b7c576d2 Lee Jones     2013-09-17  250  	/*
82b0f4b7c576d2 Lee Jones     2013-09-17  251  	 * FIXME: Add special handled PRCMU clocks here:
82b0f4b7c576d2 Lee Jones     2013-09-17  252  	 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
82b0f4b7c576d2 Lee Jones     2013-09-17  253  	 * 2. ab9540_clkout1yuv, see clkout0yuv
82b0f4b7c576d2 Lee Jones     2013-09-17  254  	 */
82b0f4b7c576d2 Lee Jones     2013-09-17  255  
82b0f4b7c576d2 Lee Jones     2013-09-17  256  	/* PRCC P-clocks */
5dc0fe199b3589 Linus Walleij 2015-07-30  257  	clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  258  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  259  	PRCC_PCLK_STORE(clk, 1, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  260  
5dc0fe199b3589 Linus Walleij 2015-07-30  261  	clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  262  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  263  	PRCC_PCLK_STORE(clk, 1, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  264  
5dc0fe199b3589 Linus Walleij 2015-07-30  265  	clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  266  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  267  	PRCC_PCLK_STORE(clk, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  268  
5dc0fe199b3589 Linus Walleij 2015-07-30  269  	clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  270  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  271  	PRCC_PCLK_STORE(clk, 1, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  272  
5dc0fe199b3589 Linus Walleij 2015-07-30  273  	clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  274  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  275  	PRCC_PCLK_STORE(clk, 1, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  276  
5dc0fe199b3589 Linus Walleij 2015-07-30  277  	clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  278  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  279  	PRCC_PCLK_STORE(clk, 1, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  280  
5dc0fe199b3589 Linus Walleij 2015-07-30  281  	clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  282  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  283  	PRCC_PCLK_STORE(clk, 1, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  284  
5dc0fe199b3589 Linus Walleij 2015-07-30  285  	clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  286  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  287  	PRCC_PCLK_STORE(clk, 1, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  288  
5dc0fe199b3589 Linus Walleij 2015-07-30  289  	clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  290  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  291  	PRCC_PCLK_STORE(clk, 1, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  292  
5dc0fe199b3589 Linus Walleij 2015-07-30  293  	clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  294  				BIT(9), 0);
2d0803001f0736 Lee Jones     2013-09-17  295  	PRCC_PCLK_STORE(clk, 1, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  296  
5dc0fe199b3589 Linus Walleij 2015-07-30  297  	clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  298  				BIT(10), 0);
2d0803001f0736 Lee Jones     2013-09-17  299  	PRCC_PCLK_STORE(clk, 1, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  300  
5dc0fe199b3589 Linus Walleij 2015-07-30  301  	clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  302  				BIT(11), 0);
2d0803001f0736 Lee Jones     2013-09-17  303  	PRCC_PCLK_STORE(clk, 1, 11);
82b0f4b7c576d2 Lee Jones     2013-09-17  304  
5dc0fe199b3589 Linus Walleij 2015-07-30  305  	clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  306  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  307  	PRCC_PCLK_STORE(clk, 2, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  308  
5dc0fe199b3589 Linus Walleij 2015-07-30  309  	clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  310  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  311  	PRCC_PCLK_STORE(clk, 2, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  312  
5dc0fe199b3589 Linus Walleij 2015-07-30  313  	clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  314  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  315  	PRCC_PCLK_STORE(clk, 2, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  316  
5dc0fe199b3589 Linus Walleij 2015-07-30  317  	clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  318  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  319  	PRCC_PCLK_STORE(clk, 2, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  320  
5dc0fe199b3589 Linus Walleij 2015-07-30  321  	clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  322  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  323  	PRCC_PCLK_STORE(clk, 2, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  324  
5dc0fe199b3589 Linus Walleij 2015-07-30  325  	clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  326  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  327  	PRCC_PCLK_STORE(clk, 2, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  328  
5dc0fe199b3589 Linus Walleij 2015-07-30  329  	clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  330  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  331  	PRCC_PCLK_STORE(clk, 2, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  332  
5dc0fe199b3589 Linus Walleij 2015-07-30  333  	clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  334  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  335  	PRCC_PCLK_STORE(clk, 2, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  336  
5dc0fe199b3589 Linus Walleij 2015-07-30  337  	clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  338  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  339  	PRCC_PCLK_STORE(clk, 2, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  340  
5dc0fe199b3589 Linus Walleij 2015-07-30  341  	clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  342  				BIT(9), 0);
2d0803001f0736 Lee Jones     2013-09-17  343  	PRCC_PCLK_STORE(clk, 2, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  344  
5dc0fe199b3589 Linus Walleij 2015-07-30  345  	clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  346  				BIT(10), 0);
2d0803001f0736 Lee Jones     2013-09-17  347  	PRCC_PCLK_STORE(clk, 2, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  348  
5dc0fe199b3589 Linus Walleij 2015-07-30  349  	clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  350  				BIT(11), 0);
f5ff9a115ec633 Linus Walleij 2013-10-18  351  	PRCC_PCLK_STORE(clk, 2, 11);
82b0f4b7c576d2 Lee Jones     2013-09-17  352  
5dc0fe199b3589 Linus Walleij 2015-07-30  353  	clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  354  				BIT(12), 0);
2d0803001f0736 Lee Jones     2013-09-17  355  	PRCC_PCLK_STORE(clk, 2, 12);
82b0f4b7c576d2 Lee Jones     2013-09-17  356  
5dc0fe199b3589 Linus Walleij 2015-07-30  357  	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  358  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  359  	PRCC_PCLK_STORE(clk, 3, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  360  
5dc0fe199b3589 Linus Walleij 2015-07-30  361  	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  362  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  363  	PRCC_PCLK_STORE(clk, 3, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  364  
5dc0fe199b3589 Linus Walleij 2015-07-30  365  	clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  366  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  367  	PRCC_PCLK_STORE(clk, 3, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  368  
5dc0fe199b3589 Linus Walleij 2015-07-30  369  	clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  370  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  371  	PRCC_PCLK_STORE(clk, 3, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  372  
5dc0fe199b3589 Linus Walleij 2015-07-30  373  	clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  374  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  375  	PRCC_PCLK_STORE(clk, 3, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  376  
5dc0fe199b3589 Linus Walleij 2015-07-30  377  	clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  378  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  379  	PRCC_PCLK_STORE(clk, 3, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  380  
5dc0fe199b3589 Linus Walleij 2015-07-30  381  	clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  382  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  383  	PRCC_PCLK_STORE(clk, 3, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  384  
5dc0fe199b3589 Linus Walleij 2015-07-30  385  	clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  386  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  387  	PRCC_PCLK_STORE(clk, 3, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  388  
5dc0fe199b3589 Linus Walleij 2015-07-30  389  	clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  390  				BIT(8), 0);
2d0803001f0736 Lee Jones     2013-09-17  391  	PRCC_PCLK_STORE(clk, 3, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  392  
5dc0fe199b3589 Linus Walleij 2015-07-30  393  	clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  394  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  395  	PRCC_PCLK_STORE(clk, 5, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  396  
5dc0fe199b3589 Linus Walleij 2015-07-30  397  	clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  398  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  399  	PRCC_PCLK_STORE(clk, 5, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  400  
5dc0fe199b3589 Linus Walleij 2015-07-30  401  	clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  402  				BIT(0), 0);
2d0803001f0736 Lee Jones     2013-09-17  403  	PRCC_PCLK_STORE(clk, 6, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  404  
5dc0fe199b3589 Linus Walleij 2015-07-30  405  	clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  406  				BIT(1), 0);
2d0803001f0736 Lee Jones     2013-09-17  407  	PRCC_PCLK_STORE(clk, 6, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  408  
5dc0fe199b3589 Linus Walleij 2015-07-30  409  	clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  410  				BIT(2), 0);
2d0803001f0736 Lee Jones     2013-09-17  411  	PRCC_PCLK_STORE(clk, 6, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  412  
5dc0fe199b3589 Linus Walleij 2015-07-30  413  	clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  414  				BIT(3), 0);
2d0803001f0736 Lee Jones     2013-09-17  415  	PRCC_PCLK_STORE(clk, 6, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  416  
5dc0fe199b3589 Linus Walleij 2015-07-30  417  	clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  418  				BIT(4), 0);
2d0803001f0736 Lee Jones     2013-09-17  419  	PRCC_PCLK_STORE(clk, 6, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  420  
5dc0fe199b3589 Linus Walleij 2015-07-30  421  	clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  422  				BIT(5), 0);
2d0803001f0736 Lee Jones     2013-09-17  423  	PRCC_PCLK_STORE(clk, 6, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  424  
5dc0fe199b3589 Linus Walleij 2015-07-30  425  	clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  426  				BIT(6), 0);
2d0803001f0736 Lee Jones     2013-09-17  427  	PRCC_PCLK_STORE(clk, 6, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  428  
5dc0fe199b3589 Linus Walleij 2015-07-30  429  	clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
82b0f4b7c576d2 Lee Jones     2013-09-17  430  				BIT(7), 0);
2d0803001f0736 Lee Jones     2013-09-17  431  	PRCC_PCLK_STORE(clk, 6, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  432  
82b0f4b7c576d2 Lee Jones     2013-09-17  433  	/* PRCC K-clocks
82b0f4b7c576d2 Lee Jones     2013-09-17  434  	 *
82b0f4b7c576d2 Lee Jones     2013-09-17  435  	 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
82b0f4b7c576d2 Lee Jones     2013-09-17  436  	 * by enabling just the K-clock, even if it is not a valid parent to
82b0f4b7c576d2 Lee Jones     2013-09-17  437  	 * the K-clock. Until drivers get fixed we might need some kind of
82b0f4b7c576d2 Lee Jones     2013-09-17  438  	 * "parent muxed join".
82b0f4b7c576d2 Lee Jones     2013-09-17  439  	 */
82b0f4b7c576d2 Lee Jones     2013-09-17  440  
82b0f4b7c576d2 Lee Jones     2013-09-17  441  	/* Periph1 */
82b0f4b7c576d2 Lee Jones     2013-09-17  442  	clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  443  			bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  444  	PRCC_KCLK_STORE(clk, 1, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  445  
82b0f4b7c576d2 Lee Jones     2013-09-17  446  	clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  447  			bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  448  	PRCC_KCLK_STORE(clk, 1, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  449  
82b0f4b7c576d2 Lee Jones     2013-09-17  450  	clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  451  			bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  452  	PRCC_KCLK_STORE(clk, 1, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  453  
82b0f4b7c576d2 Lee Jones     2013-09-17  454  	clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  455  			bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  456  	PRCC_KCLK_STORE(clk, 1, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  457  
82b0f4b7c576d2 Lee Jones     2013-09-17  458  	clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  459  			bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  460  	PRCC_KCLK_STORE(clk, 1, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  461  
82b0f4b7c576d2 Lee Jones     2013-09-17  462  	clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  463  			bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  464  	PRCC_KCLK_STORE(clk, 1, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  465  
82b0f4b7c576d2 Lee Jones     2013-09-17  466  	clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  467  			bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  468  	PRCC_KCLK_STORE(clk, 1, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  469  
82b0f4b7c576d2 Lee Jones     2013-09-17  470  	clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  471  			bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  472  	PRCC_KCLK_STORE(clk, 1, 8);
82b0f4b7c576d2 Lee Jones     2013-09-17  473  
82b0f4b7c576d2 Lee Jones     2013-09-17  474  	clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  475  			bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  476  	PRCC_KCLK_STORE(clk, 1, 9);
82b0f4b7c576d2 Lee Jones     2013-09-17  477  
82b0f4b7c576d2 Lee Jones     2013-09-17  478  	clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  479  			bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  480  	PRCC_KCLK_STORE(clk, 1, 10);
82b0f4b7c576d2 Lee Jones     2013-09-17  481  
82b0f4b7c576d2 Lee Jones     2013-09-17  482  	/* Periph2 */
82b0f4b7c576d2 Lee Jones     2013-09-17  483  	clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  484  			bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  485  	PRCC_KCLK_STORE(clk, 2, 0);
82b0f4b7c576d2 Lee Jones     2013-09-17  486  
82b0f4b7c576d2 Lee Jones     2013-09-17  487  	clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  488  			bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  489  	PRCC_KCLK_STORE(clk, 2, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  490  
82b0f4b7c576d2 Lee Jones     2013-09-17  491  	clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
5dc0fe199b3589 Linus Walleij 2015-07-30  492  			bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  493  	PRCC_KCLK_STORE(clk, 2, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  494  
82b0f4b7c576d2 Lee Jones     2013-09-17  495  	clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  496  			bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  497  	PRCC_KCLK_STORE(clk, 2, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  498  
82b0f4b7c576d2 Lee Jones     2013-09-17  499  	clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  500  			bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  501  	PRCC_KCLK_STORE(clk, 2, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  502  
82b0f4b7c576d2 Lee Jones     2013-09-17  503  	/* Note that rate is received from parent. */
82b0f4b7c576d2 Lee Jones     2013-09-17  504  	clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  505  			bases[CLKRST2_INDEX], BIT(6),
82b0f4b7c576d2 Lee Jones     2013-09-17  506  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc Lee Jones     2013-09-17  507  	PRCC_KCLK_STORE(clk, 2, 6);
89da2dfafc9ffc Lee Jones     2013-09-17  508  
82b0f4b7c576d2 Lee Jones     2013-09-17  509  	clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  510  			bases[CLKRST2_INDEX], BIT(7),
82b0f4b7c576d2 Lee Jones     2013-09-17  511  			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
89da2dfafc9ffc Lee Jones     2013-09-17  512  	PRCC_KCLK_STORE(clk, 2, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  513  
82b0f4b7c576d2 Lee Jones     2013-09-17  514  	/* Periph3 */
82b0f4b7c576d2 Lee Jones     2013-09-17  515  	clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  516  			bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  517  	PRCC_KCLK_STORE(clk, 3, 1);
82b0f4b7c576d2 Lee Jones     2013-09-17  518  
82b0f4b7c576d2 Lee Jones     2013-09-17  519  	clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  520  			bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  521  	PRCC_KCLK_STORE(clk, 3, 2);
82b0f4b7c576d2 Lee Jones     2013-09-17  522  
82b0f4b7c576d2 Lee Jones     2013-09-17  523  	clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  524  			bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  525  	PRCC_KCLK_STORE(clk, 3, 3);
82b0f4b7c576d2 Lee Jones     2013-09-17  526  
82b0f4b7c576d2 Lee Jones     2013-09-17  527  	clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  528  			bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  529  	PRCC_KCLK_STORE(clk, 3, 4);
82b0f4b7c576d2 Lee Jones     2013-09-17  530  
82b0f4b7c576d2 Lee Jones     2013-09-17  531  	clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
5dc0fe199b3589 Linus Walleij 2015-07-30  532  			bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  533  	PRCC_KCLK_STORE(clk, 3, 5);
82b0f4b7c576d2 Lee Jones     2013-09-17  534  
82b0f4b7c576d2 Lee Jones     2013-09-17  535  	clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  536  			bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  537  	PRCC_KCLK_STORE(clk, 3, 6);
82b0f4b7c576d2 Lee Jones     2013-09-17  538  
82b0f4b7c576d2 Lee Jones     2013-09-17  539  	clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  540  			bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  541  	PRCC_KCLK_STORE(clk, 3, 7);
82b0f4b7c576d2 Lee Jones     2013-09-17  542  
82b0f4b7c576d2 Lee Jones     2013-09-17  543  	/* Periph6 */
82b0f4b7c576d2 Lee Jones     2013-09-17  544  	clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
5dc0fe199b3589 Linus Walleij 2015-07-30  545  			bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
89da2dfafc9ffc Lee Jones     2013-09-17  546  	PRCC_KCLK_STORE(clk, 6, 0);
dec759d8ef01b3 Lee Jones     2013-09-17  547  
dec759d8ef01b3 Lee Jones     2013-09-17 @548  	for_each_child_of_node(np, child) {

:::::: The code at line 548 was first introduced by commit
:::::: dec759d8ef01b3edd5ceb9832ce2338c6c396d11 clk: ux500: Provide u8500_clk with skeleton Device Tree support

:::::: TO: Lee Jones <lee.jones@linaro.org>
:::::: CC: Linus Walleij <linus.walleij@linaro.org>

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2022-05-08  2:42 drivers/clk/ux500/u8500_of_clk.c:548 u8500_clk_init() warn: possible memory leak of 'rstc' kernel test robot
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