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Tue, 10 May 2022 15:46:50 -0500 From: David Zhang To: Subject: [PATCH v2 19/19] drm/amd/display: PSR-SU rate control support in DC Date: Tue, 10 May 2022 16:45:08 -0400 Message-ID: <20220510204508.506089-20-dingchen.zhang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510204508.506089-1-dingchen.zhang@amd.com> References: <20220510204508.506089-1-dingchen.zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ec8314f0-25bc-43b3-1386-08da32c636c9 X-MS-TrafficTypeDiagnostic: BY5PR12MB4321:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Us88Z/k9w6dIwVTJh2gtcMFXGuZO3D0CkLavwlr7mv7b1J3gz8JPD8RgZhgIv8GOdTxMx8NP95oaSFAUtbA9Ery9XyPS4RfvUGPu6HOFBKEzSahGSek0K+4IejoWj1uYadbF2WsPFNZyzZDjA+plz9wAJxxWsSjW8z265bW8pOc8DoVzf4oTXM8Tk1i7eaP0lhrHK4DVJ+RicCdqpUMRnW6qP6I+M8H4WMJjxQTPFB4O0EHftseS9uP264aIJegAct8kxBDxlumU9eYdZJi/4X+RmTsSytl/vpO8+rnSFhRckhgF5Jc2yLxbKWXc9RnidfEMEikX56yZB9dj4IhUoHgebGbIfe+4g2ewt98v2lIKfwvk0bNl4Pw7dzhOkH5PCGruuaellsAyPb3dkZtIGL6Gg5ExLBykXGzWjroRylP5Y+sUZCXzhlMjegfj2mHqEhN0XG/omjZhBphTeBQz2UCJ5N8ZFdopSvfV6VxcgmbZSm/jvNiEDlkierP6G6/RXZ4w3N7xlhkIBmpQXp55tzYfPeHyjPppVgoSpCcFrk0OtyGpv9bSadC1ul8Mt4yN7haNeWzMTnZ0W27jJCZQblHGt882s3lxoenK5sIyEvyTwVamWQG9ubnrVoQ7Sd4pTIm+dF9Gp6KBpjx7A+SXJrjNWyvlL5JYM6Aox8kiI4i+Waodtmh6D2N0utYNohmd+xHdLa3kRqp1EsG3TPQCSw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(2616005)(356005)(82310400005)(36756003)(26005)(5660300002)(83380400001)(8936002)(1076003)(70586007)(316002)(47076005)(6666004)(508600001)(70206006)(426003)(86362001)(8676002)(4326008)(54906003)(6916009)(336012)(81166007)(7696005)(186003)(36860700001)(2906002)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2022 20:46:52.8532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec8314f0-25bc-43b3-1386-08da32c636c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4321 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stylon.wang@amd.com, David Zhang , Sunpeng.Li@amd.com, Harry.Wentland@amd.com, qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com, roman.li@amd.com, solomon.chiu@amd.com, jerry.zuo@amd.com, Aurabindo.Pillai@amd.com, wayne.lin@amd.com, Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com, pavle.kotarac@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [why & how] We need to add the necessary DC codes to support PSR-SU rate control (RC). Signed-off-by: David Zhang --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 14 +++++++++++ drivers/gpu/drm/amd/display/dc/dc_link.h | 3 +++ drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h | 2 ++ .../drm/amd/display/dc/inc/hw/link_encoder.h | 8 +++++++ 6 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 259745074ebb..08dedc16a9c5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1765,6 +1765,7 @@ static bool dc_link_construct_legacy(struct dc_link *link, */ program_hpd_filter(link); + link->psr_settings.psr_vtotal_control_support = false; link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); @@ -3377,6 +3378,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency) *residency = 0; } +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) +{ + struct dc *dc = link->ctx->dc; + struct dmub_psr *psr = dc->res_pool->psr; + + if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support) + return false; + + psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su); + + return true; +} + const struct dc_link_status *dc_link_get_status(const struct dc_link *link) { return &link->link_status; diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h index 5e7f70840e1a..4e15e68375da 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -100,6 +100,7 @@ struct psr_settings { bool psr_feature_enabled; // PSR is supported by sink bool psr_allow_active; // PSR is currently active enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD + bool psr_vtotal_control_support; // Vtotal control is supported by sink /* These parameters are calculated in Driver, * based on display timing and Sink capabilities. @@ -326,6 +327,8 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency); void dc_link_blank_all_dp_displays(struct dc *dc); void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init); +bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su); /* Request DC to detect if there is a Panel connected. * boot - If this call is during initial boot. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 26b62f50ac4e..fa735d5f730f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -684,6 +684,7 @@ struct psr_config { /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; unsigned int line_time_in_us; + uint8_t rate_control_caps; }; union dmcu_psr_level { @@ -794,6 +795,7 @@ struct psr_context { /* psr2 selective update y granularity capability */ uint8_t su_y_granularity; unsigned int line_time_in_us; + uint8_t rate_control_caps; }; struct colorspace_transform { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 9ca0cbb0af9b..0df06740ec39 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_ dc_dmub_srv_wait_idle(dc->dmub_srv); } +/** + * Set PSR vtotal requirement for FreeSync PSR. + */ +static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su) +{ + union dmub_rb_cmd cmd; + struct dc_context *dc = dmub->ctx; + + memset(&cmd, 0, sizeof(cmd)); + cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR; + cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE; + cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data); + cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle; + cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su; + + dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dc->dmub_srv); + dc_dmub_srv_wait_idle(dc->dmub_srv); +} + /* * Set PSR power optimization flags. */ @@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->line_capture_indication = 0; copy_settings_data->line_time_in_us = psr_context->line_time_in_us; + copy_settings_data->rate_control_caps = psr_context->rate_control_caps; copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled); copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; @@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = { .psr_set_level = dmub_psr_set_level, .psr_force_static = dmub_psr_force_static, .psr_get_residency = dmub_psr_get_residency, + .psr_set_sink_vtotal_in_psr_active = dmub_psr_set_sink_vtotal_in_psr_active, .psr_set_power_opt = dmub_psr_set_power_opt, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h index 01acc01cc191..74005b9d352a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h @@ -46,6 +46,8 @@ struct dmub_psr_funcs { void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst); void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst); + void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub, + uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su); void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 66132f3cac42..c89643eaa0f4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -101,6 +101,14 @@ union dpcd_alpm_configuration { unsigned char raw; }; +union dpcd_sink_active_vtotal_control_mode { + struct { + unsigned char ENABLE : 1; + unsigned char RESERVED : 7; + } bits; + unsigned char raw; +}; + union psr_error_status { struct { unsigned char LINK_CRC_ERROR :1; -- 2.25.1