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* [PATCH v2 0/3] Clear TLB caches in all tiles when object is removed
@ 2022-05-10 21:33 ` Andi Shyti
  0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel
  Cc: Tvrtko Ursulin, Andi Shyti, Matthew Auld, Andi Shyti, Chris Wilson

Hi,

The real fix is in patch 2. The rest is a helper that adds
the with_intel_gt_pm_if_awake() (from Chris) and one more check
on the status of the engine before accessing it for clearing the
TLB.

Andi

Andi Shyti (2):
  drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
  drm/i915/gt: Skip TLB invalidation if the engine is not awake

Chris Wilson (1):
  drm/i915/gt: Ignore TLB invalidations on idle engines

 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 drivers/gpu/drm/i915/gt/intel_gt.c        |  3 +++
 drivers/gpu/drm/i915/gt/intel_gt_pm.h     |  4 ++++
 3 files changed, 16 insertions(+), 3 deletions(-)

-- 
2.36.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [Intel-gfx] [PATCH v2 0/3] Clear TLB caches in all tiles when object is removed
@ 2022-05-10 21:33 ` Andi Shyti
  0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel; +Cc: Matthew Auld, Chris Wilson

Hi,

The real fix is in patch 2. The rest is a helper that adds
the with_intel_gt_pm_if_awake() (from Chris) and one more check
on the status of the engine before accessing it for clearing the
TLB.

Andi

Andi Shyti (2):
  drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
  drm/i915/gt: Skip TLB invalidation if the engine is not awake

Chris Wilson (1):
  drm/i915/gt: Ignore TLB invalidations on idle engines

 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 drivers/gpu/drm/i915/gt/intel_gt.c        |  3 +++
 drivers/gpu/drm/i915/gt/intel_gt_pm.h     |  4 ++++
 3 files changed, 16 insertions(+), 3 deletions(-)

-- 
2.36.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines
  2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
@ 2022-05-10 21:33   ` Andi Shyti
  -1 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel
  Cc: Tvrtko Ursulin, Andi Shyti, Matthew Auld, Andi Shyti, Chris Wilson

From: Chris Wilson <chris@chris-wilson.co.uk>

As an extension of the current skip TLB invalidations if the device is
powered down, we recognised that prior to any engine activity, all the
TLBs are explicitly invalidated. Thus anytime we know the engine is
asleep, we can skip invalidating the TLBs on that engine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48cc..2654133b39f22 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,6 +55,10 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
 	for (tmp = 1, intel_gt_pm_get(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
+#define with_intel_gt_pm_if_awake(gt, wf) \
+	for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \
+	     intel_gt_pm_put(gt), tmp = 0)
+
 static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)
 {
 	return intel_wakeref_wait_for_idle(&gt->wakeref);
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [Intel-gfx] [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines
@ 2022-05-10 21:33   ` Andi Shyti
  0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel; +Cc: Matthew Auld, Chris Wilson

From: Chris Wilson <chris@chris-wilson.co.uk>

As an extension of the current skip TLB invalidations if the device is
powered down, we recognised that prior to any engine activity, all the
TLBs are explicitly invalidated. Thus anytime we know the engine is
asleep, we can skip invalidating the TLBs on that engine.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index bc898df7a48cc..2654133b39f22 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,6 +55,10 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
 	for (tmp = 1, intel_gt_pm_get(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
+#define with_intel_gt_pm_if_awake(gt, wf) \
+	for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \
+	     intel_gt_pm_put(gt), tmp = 0)
+
 static inline int intel_gt_pm_wait_for_idle(struct intel_gt *gt)
 {
 	return intel_wakeref_wait_for_idle(&gt->wakeref);
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
  2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
@ 2022-05-10 21:33   ` Andi Shyti
  -1 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel
  Cc: Tvrtko Ursulin, Andi Shyti, Matthew Auld, Andi Shyti, Chris Wilson

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h     |  2 +-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..37d23e328bd0c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -13,6 +13,7 @@
 #include "i915_gem_mman.h"
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
 
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 				 struct sg_table *pages,
@@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			int tmp;
+
+			with_intel_gt_pm_if_awake(gt, tmp)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 2654133b39f22..3b1fbce7ea369 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,7 +55,7 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
 	for (tmp = 1, intel_gt_pm_get(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
-#define with_intel_gt_pm_if_awake(gt, wf) \
+#define with_intel_gt_pm_if_awake(gt, tmp) \
 	for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [Intel-gfx] [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj
@ 2022-05-10 21:33   ` Andi Shyti
  0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel; +Cc: Matthew Auld, Chris Wilson

During object cleanup we invalidate the TLBs but we do it only
for gt0. Invalidate the caches for all the tiles.

Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 12 +++++++++---
 drivers/gpu/drm/i915/gt/intel_gt_pm.h     |  2 +-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 97c820eee115a..37d23e328bd0c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -13,6 +13,7 @@
 #include "i915_gem_mman.h"
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_pm.h"
 
 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
 				 struct sg_table *pages,
@@ -217,10 +218,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
 
 	if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
 		struct drm_i915_private *i915 = to_i915(obj->base.dev);
-		intel_wakeref_t wakeref;
+		struct intel_gt *gt;
+		int i;
 
-		with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
-			intel_gt_invalidate_tlbs(to_gt(i915));
+		for_each_gt(gt, i915, i) {
+			int tmp;
+
+			with_intel_gt_pm_if_awake(gt, tmp)
+				intel_gt_invalidate_tlbs(gt);
+		}
 	}
 
 	return pages;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
index 2654133b39f22..3b1fbce7ea369 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.h
@@ -55,7 +55,7 @@ static inline void intel_gt_pm_might_put(struct intel_gt *gt)
 	for (tmp = 1, intel_gt_pm_get(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
-#define with_intel_gt_pm_if_awake(gt, wf) \
+#define with_intel_gt_pm_if_awake(gt, tmp) \
 	for (tmp = 1, intel_gt_pm_get_if_awake(gt); tmp; \
 	     intel_gt_pm_put(gt), tmp = 0)
 
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake
  2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
@ 2022-05-10 21:33   ` Andi Shyti
  -1 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel
  Cc: Tvrtko Ursulin, Andi Shyti, Matthew Auld, Andi Shyti, Chris Wilson

We want to check if the engine is awake first before invalidating
its cache.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501b..de26fbe6b71dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1219,6 +1219,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 		const unsigned int timeout_ms = 4;
 		struct reg_and_bit rb;
 
+		if (!intel_engine_pm_is_awake(engine))
+			continue;
+
 		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 		if (!i915_mmio_reg_offset(rb.reg))
 			continue;
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake
@ 2022-05-10 21:33   ` Andi Shyti
  0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2022-05-10 21:33 UTC (permalink / raw)
  To: Intel GFX, DRI Devel; +Cc: Matthew Auld, Chris Wilson

We want to check if the engine is awake first before invalidating
its cache.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501b..de26fbe6b71dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1219,6 +1219,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 		const unsigned int timeout_ms = 4;
 		struct reg_and_bit rb;
 
+		if (!intel_engine_pm_is_awake(engine))
+			continue;
+
 		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 		if (!i915_mmio_reg_offset(rb.reg))
 			continue;
-- 
2.36.0


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Clear TLB caches in all tiles when object is removed
  2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
                   ` (3 preceding siblings ...)
  (?)
@ 2022-05-10 22:21 ` Patchwork
  -1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-05-10 22:21 UTC (permalink / raw)
  To: Andi Shyti; +Cc: intel-gfx

== Series Details ==

Series: Clear TLB caches in all tiles when object is removed
URL   : https://patchwork.freedesktop.org/series/103835/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/gt/intel_gt.o
drivers/gpu/drm/i915/gt/intel_gt.c: In function ‘intel_gt_invalidate_tlbs’:
drivers/gpu/drm/i915/gt/intel_gt.c:1222:8: error: implicit declaration of function ‘intel_engine_pm_is_awake’; did you mean ‘intel_gt_pm_is_awake’? [-Werror=implicit-function-declaration]
   if (!intel_engine_pm_is_awake(engine))
        ^~~~~~~~~~~~~~~~~~~~~~~~
        intel_gt_pm_is_awake
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/gt/intel_gt.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/intel_gt.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1834: recipe for target 'drivers' failed
make: *** [drivers] Error 2



^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-05-10 22:21 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 21:33 [PATCH v2 0/3] Clear TLB caches in all tiles when object is removed Andi Shyti
2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Andi Shyti
2022-05-10 21:33   ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj Andi Shyti
2022-05-10 21:33   ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Andi Shyti
2022-05-10 21:33   ` [Intel-gfx] " Andi Shyti
2022-05-10 22:21 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Clear TLB caches in all tiles when object is removed Patchwork

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