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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
	Andi Shyti <andi@etezian.org>,
	Matthew Auld <matthew.auld@intel.com>,
	Andi Shyti <andi.shyti@linux.intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake
Date: Tue, 10 May 2022 23:33:04 +0200	[thread overview]
Message-ID: <20220510213304.101055-4-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com>

We want to check if the engine is awake first before invalidating
its cache.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501b..de26fbe6b71dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1219,6 +1219,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 		const unsigned int timeout_ms = 4;
 		struct reg_and_bit rb;
 
+		if (!intel_engine_pm_is_awake(engine))
+			continue;
+
 		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 		if (!i915_mmio_reg_offset(rb.reg))
 			continue;
-- 
2.36.0


WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>,
	DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Matthew Auld <matthew.auld@intel.com>,
	Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake
Date: Tue, 10 May 2022 23:33:04 +0200	[thread overview]
Message-ID: <20220510213304.101055-4-andi.shyti@linux.intel.com> (raw)
In-Reply-To: <20220510213304.101055-1-andi.shyti@linux.intel.com>

We want to check if the engine is awake first before invalidating
its cache.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501b..de26fbe6b71dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1219,6 +1219,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
 		const unsigned int timeout_ms = 4;
 		struct reg_and_bit rb;
 
+		if (!intel_engine_pm_is_awake(engine))
+			continue;
+
 		rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num);
 		if (!i915_mmio_reg_offset(rb.reg))
 			continue;
-- 
2.36.0


  parent reply	other threads:[~2022-05-10 21:34 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-10 21:33 [PATCH v2 0/3] Clear TLB caches in all tiles when object is removed Andi Shyti
2022-05-10 21:33 ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` [PATCH v2 1/3] drm/i915/gt: Ignore TLB invalidations on idle engines Andi Shyti
2022-05-10 21:33   ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` [PATCH v2 2/3] drm/i915/gem: Flush TLBs for all the tiles when clearing an obj Andi Shyti
2022-05-10 21:33   ` [Intel-gfx] " Andi Shyti
2022-05-10 21:33 ` Andi Shyti [this message]
2022-05-10 21:33   ` [Intel-gfx] [PATCH v2 3/3] drm/i915/gt: Skip TLB invalidation if the engine is not awake Andi Shyti
2022-05-10 22:21 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Clear TLB caches in all tiles when object is removed Patchwork

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