From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH 06/12] riscv: prevent compressed instructions in alternatives Date: Wed, 11 May 2022 21:29:15 +0200 [thread overview] Message-ID: <20220511192921.2223629-7-heiko@sntech.de> (raw) In-Reply-To: <20220511192921.2223629-1-heiko@sntech.de> Instructions are opportunistically compressed by the RISC-V assembler when possible, but in alternatives-blocks both the old and new content need to be the same size, so having the toolchain do somewhat random optimizations will cause strange side-effects like "attempt to move .org backwards" compile-time errors. Already a simple "and" used in alternatives assembly will cause these mismatched code sizes. So prevent compressed instructions to be generated in alternatives- code and use option-push and -pop to only limit this to the relevant code blocks Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- arch/riscv/include/asm/alternative-macros.h | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 8c2bbc7bbe50..e13b1f6bb400 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -21,7 +21,11 @@ .popsection .subsection 1 888 : + .option push + .option norvc + .option norelax \new_c + .option pop 889 : .previous .org . - (889b - 888b) + (887b - 886b) @@ -31,7 +35,11 @@ .macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable 886 : + .option push + .option norvc + .option norelax \old_c + .option pop 887 : ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c .endm @@ -42,7 +50,11 @@ .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ new_c_2, vendor_id_2, errata_id_2, enable_2 886 : + .option push + .option norvc + .option norelax \old_c + .option pop 887 : ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1 ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2 @@ -76,7 +88,11 @@ ".popsection\n" \ ".subsection 1\n" \ "888 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ new_c "\n" \ + ".option pop\n" \ "889 :\n" \ ".previous\n" \ ".org . - (887b - 886b) + (889b - 888b)\n" \ @@ -85,7 +101,11 @@ #define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ "886 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ old_c "\n" \ + ".option pop\n" \ "887 :\n" \ ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) @@ -97,7 +117,11 @@ new_c_2, vendor_id_2, errata_id_2, \ enable_2) \ "886 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ old_c "\n" \ + ".option pop\n" \ "887 :\n" \ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \ ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2) -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH 06/12] riscv: prevent compressed instructions in alternatives Date: Wed, 11 May 2022 21:29:15 +0200 [thread overview] Message-ID: <20220511192921.2223629-7-heiko@sntech.de> (raw) In-Reply-To: <20220511192921.2223629-1-heiko@sntech.de> Instructions are opportunistically compressed by the RISC-V assembler when possible, but in alternatives-blocks both the old and new content need to be the same size, so having the toolchain do somewhat random optimizations will cause strange side-effects like "attempt to move .org backwards" compile-time errors. Already a simple "and" used in alternatives assembly will cause these mismatched code sizes. So prevent compressed instructions to be generated in alternatives- code and use option-push and -pop to only limit this to the relevant code blocks Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- arch/riscv/include/asm/alternative-macros.h | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 8c2bbc7bbe50..e13b1f6bb400 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -21,7 +21,11 @@ .popsection .subsection 1 888 : + .option push + .option norvc + .option norelax \new_c + .option pop 889 : .previous .org . - (889b - 888b) + (887b - 886b) @@ -31,7 +35,11 @@ .macro __ALTERNATIVE_CFG old_c, new_c, vendor_id, errata_id, enable 886 : + .option push + .option norvc + .option norelax \old_c + .option pop 887 : ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c .endm @@ -42,7 +50,11 @@ .macro __ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ new_c_2, vendor_id_2, errata_id_2, enable_2 886 : + .option push + .option norvc + .option norelax \old_c + .option pop 887 : ALT_NEW_CONTENT \vendor_id_1, \errata_id_1, \enable_1, \new_c_1 ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2 @@ -76,7 +88,11 @@ ".popsection\n" \ ".subsection 1\n" \ "888 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ new_c "\n" \ + ".option pop\n" \ "889 :\n" \ ".previous\n" \ ".org . - (887b - 886b) + (889b - 888b)\n" \ @@ -85,7 +101,11 @@ #define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ "886 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ old_c "\n" \ + ".option pop\n" \ "887 :\n" \ ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) @@ -97,7 +117,11 @@ new_c_2, vendor_id_2, errata_id_2, \ enable_2) \ "886 :\n" \ + ".option push\n" \ + ".option norvc\n" \ + ".option norelax\n" \ old_c "\n" \ + ".option pop\n" \ "887 :\n" \ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \ ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2) -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-11 19:30 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 19:29 [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 01/12] riscv: integrate alternatives better into the main architecture Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:45 ` Guo Ren 2022-05-16 6:45 ` Guo Ren 2022-05-11 19:29 ` [PATCH 02/12] riscv: allow different stages with alternatives Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:51 ` Guo Ren 2022-05-16 6:51 ` Guo Ren 2022-05-11 19:29 ` [PATCH 03/12] riscv: implement module alternatives Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:02 ` Christoph Hellwig 2022-05-16 6:02 ` Christoph Hellwig 2022-05-16 6:54 ` Guo Ren 2022-05-16 6:54 ` Guo Ren 2022-05-11 19:29 ` [PATCH 04/12] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:54 ` Guo Ren 2022-05-16 6:54 ` Guo Ren 2022-05-11 19:29 ` [PATCH 05/12] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-11 19:29 ` Heiko Stuebner [this message] 2022-05-11 19:29 ` [PATCH 06/12] riscv: prevent compressed instructions in alternatives Heiko Stuebner 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-11 19:29 ` [PATCH 07/12] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 08/12] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-23 14:03 ` Alexandre Ghiti 2022-05-23 14:03 ` Alexandre Ghiti 2022-05-25 15:22 ` Heiko Stübner 2022-05-25 15:22 ` Heiko Stübner 2022-05-28 8:15 ` Alexandre Ghiti 2022-05-28 8:15 ` Alexandre Ghiti 2022-05-11 19:29 ` [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:10 ` Christoph Hellwig 2022-05-16 6:10 ` Christoph Hellwig 2022-05-16 9:09 ` Philipp Tomsich 2022-05-16 9:09 ` Philipp Tomsich 2022-05-16 10:30 ` Heiko Stübner 2022-05-16 10:30 ` Heiko Stübner 2022-05-11 19:29 ` [PATCH 10/12] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 11/12] riscv: don't use global static vars to store alternative data Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:15 ` Christoph Hellwig 2022-05-16 6:15 ` Christoph Hellwig 2022-05-11 19:29 ` [PATCH 12/12] riscv: add memory-type errata for T-Head Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-13 13:37 ` Guo Ren 2022-05-13 13:37 ` Guo Ren 2022-05-13 3:32 ` [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt 2022-05-13 3:32 ` Palmer Dabbelt 2022-05-13 21:41 ` Heiko Stuebner 2022-05-13 21:41 ` Heiko Stuebner
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