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From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org,
	anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org,
	cmuellner@linux.com, philipp.tomsich@vrull.eu,
	robh+dt@kernel.org, krzk+dt@kernel.org,
	devicetree@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size
Date: Wed, 11 May 2022 23:41:30 +0200	[thread overview]
Message-ID: <20220511214132.2281431-2-heiko@sntech.de> (raw)
In-Reply-To: <20220511214132.2281431-1-heiko@sntech.de>

The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.

So add the necessary property for the system to know the core's
block-size.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b179bfd155a3 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,13 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  riscv,cbom-block-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Blocksize in bytes for the Zicbom cache operations. The block
+      size is a property of the core itself and does not necessarily
+      match other software defined cache sizes.
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture
-- 
2.35.1


WARNING: multiple messages have this Message-ID
From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org,
	anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org,
	cmuellner@linux.com, philipp.tomsich@vrull.eu,
	robh+dt@kernel.org, krzk+dt@kernel.org,
	devicetree@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size
Date: Wed, 11 May 2022 23:41:30 +0200	[thread overview]
Message-ID: <20220511214132.2281431-2-heiko@sntech.de> (raw)
In-Reply-To: <20220511214132.2281431-1-heiko@sntech.de>

The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.

So add the necessary property for the system to know the core's
block-size.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b179bfd155a3 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,13 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  riscv,cbom-block-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Blocksize in bytes for the Zicbom cache operations. The block
+      size is a property of the core itself and does not necessarily
+      match other software defined cache sizes.
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture
-- 
2.35.1


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http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-05-11 21:41 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11 21:41 [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-05-11 21:41 ` Heiko Stuebner
2022-05-11 21:41 ` Heiko Stuebner [this message]
2022-05-11 21:41   ` [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-05-12  4:18   ` Anup Patel
2022-05-12  4:18     ` Anup Patel
2022-05-13 10:28     ` Christoph Müllner
2022-05-13 10:28       ` Christoph Müllner
2022-05-18  0:25   ` Rob Herring
2022-05-18  0:25     ` Rob Herring
2022-05-18  8:22     ` Philipp Tomsich
2022-05-18  8:22       ` Philipp Tomsich
2022-05-18  9:02       ` Heiko Stübner
2022-05-18  9:02         ` Heiko Stübner
2022-05-18  9:10         ` Anup Patel
2022-05-18  9:10           ` Anup Patel
2022-05-18  9:20           ` Philipp Tomsich
2022-05-18  9:20             ` Philipp Tomsich
2022-05-25 15:14     ` Heiko Stübner
2022-05-25 15:14       ` Heiko Stübner
2022-05-11 21:41 ` [PATCH v2 2/3] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-05-11 21:41   ` Heiko Stuebner
2022-05-12  4:19   ` Anup Patel
2022-05-12  4:19     ` Anup Patel
2022-05-13 13:38     ` Guo Ren
2022-05-13 13:38       ` Guo Ren
2022-05-16  6:00   ` Christoph Hellwig
2022-05-16  6:00     ` Christoph Hellwig
2022-05-11 21:41 ` [PATCH v2 3/3] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-05-11 21:41   ` Heiko Stuebner
2022-05-12  4:40   ` Anup Patel
2022-05-12  4:40     ` Anup Patel
2022-05-13 13:37     ` Guo Ren
2022-05-13 13:37       ` Guo Ren

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