All of lore.kernel.org
 help / color / mirror / Atom feed
From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function
Date: Wed, 11 May 2022 14:59:45 -0700	[thread overview]
Message-ID: <20220511215956.2351243-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220511215956.2351243-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92e1..ee3a35afa256 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -72,6 +72,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 #if !defined(CONFIG_USER_ONLY)
     CPUState *cs = env_cpu(env);
     RISCVCPU *cpu = RISCV_CPU(cs);
+    int ctr_index;
 
     if (!cpu->cfg.ext_counters) {
         /* The Counters extensions is not enabled */
@@ -99,8 +100,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
-                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+            ctr_index = csrno - CSR_CYCLE;
+            if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                 get_field(env->mcounteren, 1 << ctr_index)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -126,8 +128,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                 }
                 break;
             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
-                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                ctr_index = csrno - CSR_CYCLEH;
+                if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                     get_field(env->mcounteren, 1 << ctr_index)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.25.1


  reply	other threads:[~2022-05-11 22:00 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-11 21:59 [PATCH v8 00/12] Improve PMU support Atish Patra
2022-05-11 21:59 ` Atish Patra [this message]
2022-05-11 21:59 ` [PATCH v8 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-05-11 21:59 ` [PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-05-11 21:59 ` [PATCH v8 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-05-11 21:59 ` [PATCH v8 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-05-11 21:59 ` [PATCH v8 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-05-11 21:59 ` [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-05-13  6:29   ` Frank Chang
2022-05-13 15:58     ` Atish Kumar Patra
2022-05-14  7:46       ` Frank Chang
2022-05-18  6:07         ` Atish Patra
2022-05-11 21:59 ` [PATCH v8 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-05-11 21:59 ` [PATCH v8 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-05-11 21:59 ` [PATCH v8 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-05-11 21:59 ` [PATCH v8 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-05-11 21:59 ` [PATCH v8 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220511215956.2351243-2-atishp@rivosinc.com \
    --to=atishp@rivosinc.com \
    --cc=alistair.francis@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=bmeng.cn@gmail.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.