From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6DC21C433F5 for ; Fri, 13 May 2022 23:00:26 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EF46083C36; Sat, 14 May 2022 01:00:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="J7lBZZ32"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9974D82064; Sat, 14 May 2022 01:00:18 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CBCDD82064 for ; Sat, 14 May 2022 01:00:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C44C46113A; Fri, 13 May 2022 23:00:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2E79C34100; Fri, 13 May 2022 23:00:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652482810; bh=FrGZxkCpMyqShxyqGGSz/5H2qJZ7LxEAqsEm5qXfDcM=; h=Date:From:To:Subject:From; b=J7lBZZ32a3t7zPY5BMkSMYBLVveSy/l1VeeRxod/OWLlYhtNbvL5OEAYD2jkr6mFA UspbYjn0fHV52V6c5igu5ieUS3p29R8a9gZxc+P/7L+8E7zsmX9ZHJgPU+cqKOuckB Hn4afbbmsidyZ3MSAnLb3TViGSxnxVe8TmT57zyVQI0K21WNjI6+a+fD6r1yH4sJy0 YaMxzWp+OGqYiDGEx5AtI320QBqO2fhWxdVIl7XvQjHbV9EldNHp8utVyX1xijCFa2 rkCWzN0mNdLfP4hf/EA4pW702iTTpuATW81hg0tcnObUBCEjrSnoj8oTnfLyKub3GL rJ4E3ZFjqZ7qw== Received: by pali.im (Postfix) id 4E6502B90; Sat, 14 May 2022 01:00:06 +0200 (CEST) Date: Sat, 14 May 2022 01:00:06 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Tom Rini , Simon Glass , u-boot@lists.denx.de Subject: Broken support for 4GB DDR on 32-bit platforms Message-ID: <20220513230006.ep5qdhuu6k5ado2l@pali> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hello! I tried to enable support for 2GB+ of DDR memory (with 4GB DDR3) on powerpc P2020 board in 32-bit addressing mode and U-Boot crashed during startup. I figured out that issue is not powerpc specific, but rather generic to all 32-bit platforms. U-Boot stores memory size into phys_size_t type (gd->ram_size) and last mapped memory address increased by one byte into phys_addr_t type (gd->ram_top). Despite size 4GB fits into 32-bit addressing mode, it does not fit into above two variables, and it overflows to zero. U-Boot then see zero RAM size and crashes. I tried to workaround this issue by changing both phys_size_t and phys_addr_t types to 64-bit. But it did not helped because U-Boot on many places cast gd->ram_size or gd->ram_top to ulong type, which is 32-bit on 32-bit platforms. Next I changed ulong parameters of board_get_usable_ram_top() function to u64. This still was not enough because config value CONFIG_MAX_MEM_MAPPED is ignored on one important place -- in function get_effective_memsize(). This config value takes effect only when also CONFIG_VERY_BIG_RAM is set. Finally With this change I was able to start U-Boot with more than 2GB of DDR memory inserted in SODIMM slot on P2020. How to fix issues with gd->ram_size and gd->ram_top? That +1 byte is really stupid limitation. Changing phys_size_t and phys_addr_t types unconditionally to 64-bit? Or something else? And what is the purpose of CONFIG_VERY_BIG_RAM config option? Why is CONFIG_MAX_MEM_MAPPED check skipped in get_effective_memsize() function, but is not skipped on many more places?