[PATCH v3 0/8] arm64: dts: qcom: initial Inforce IFC6560 board support

[PATCH v3 0/8] arm64: dts: qcom: initial Inforce IFC6560 board support

[Dmitry Baryshkov]

This work is largely based on the previous work by Bjorn Andersson ([1])

Changes since v2:
- Removed useless enablement of mdp node from the board file. It is
  already enabled in the SoC dtsi file.

Changes since v1 (mostly based on Kondrad's review):
- Also disabled dsi0/dsi0 phy in sdm630.dtsi
- Removed the clock from BAM DMA devices rather than disabling them
  completely
- Replaced numbers with symbolic names for interconnects in sdm630.dtsi
- Switched to "qcom,sda660" as a fallback compatible string
- Added dt-bindings for the qcom,sda660 compat
- Removed extra nesting level from the adsp firmware path
- Replaced numbers with proper symbolic names in the board file
- Added chassis-type property
- Changed the order of blsp entries in the board file
- Removed spurious newlines
- Changed the order of regulator properties
- Changed the DSI data-lines to list all four lanes. Still use just
  three lanes for the adv bridge (and describe the reason in the
  comment)

Changes since Bjorn's v2:
- Disable dsi1, dsi1 phy, GPU by default in sdm660.dtsi/sdm630.dtsi
- Fix qusb2phy ref clock
- Added USB2 host support to sdm630.dtsi
- Renamed DTS to follow SoC-vendor-board pattern
- Fixed vph_pwr voltage
- Removed extra/unrelated comments
- Added keys, USB2, USB3,
- Added configuration for the attached HDMI bridge
- Enabled MDP, MDSS and DSI0/DSI0 PHY devices
- Removed uart pinctrl and /reserved-mem nodes (present in main dtsi
  file)
- Added card detection for the SDCC2
- Disabled BLSP BAM DMA devices, they make the board reset during boot

[1] https://lore.kernel.org/linux-arm-msm/20210825221110.1498718-1-bjorn.andersson@linaro.org/#t

Dmitry Baryshkov (8):
  arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default
  arm64: dts: qcom: sdm630: disable dsi1/dsi1_phy by default
  arm64: dts: qcom: sdm630: disable GPU by default
  arm64: dts: qcom: sdm630: fix the qusb2phy ref clock
  arm64: dts: qcom: sdm630: add second (HS) USB host support
  arm64: dts: qcom: sdm630: use defined symbols for interconnects
  arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support
  dt-bindings: arm: qcom: document sda660 SoC and ifc6560 board

 .../devicetree/bindings/arm/qcom.yaml         |   6 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sda660-inforce-ifc6560.dts  | 455 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sdm630.dtsi          |  85 +++-
 arch/arm64/boot/dts/qcom/sdm660.dtsi          |   3 +
 5 files changed, 538 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts

-- 
2.35.1

[PATCH v3 1/8] arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default

[Dmitry Baryshkov]

Follow the typical practice and keep DSI1/DSI1 PHY disabled by default.
They should be enabled in the board DT files. No existing boards use
them at this moment.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm660.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi
index eccf6fde16b4..023b0ac4118c 100644
--- a/arch/arm64/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi
@@ -192,6 +192,8 @@ dsi1: dsi@c996000 {
 		phys = <&dsi1_phy>;
 		phy-names = "dsi";
 
+		status = "disabled";
+
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -225,6 +227,7 @@ dsi1_phy: dsi-phy@c996400 {
 
 		clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 		clock-names = "iface", "ref";
+		status = "disabled";
 	};
 };
 
-- 
2.35.1

[PATCH v3 2/8] arm64: dts: qcom: sdm630: disable dsi1/dsi1_phy by default

[Dmitry Baryshkov]

Follow the typical practice and keep DSI0/DSI0 PHY disabled by default.
They should be enabled in the board DT files. No existing boards use
them at this moment.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 240293592ef9..8697d40e9b74 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1559,6 +1559,8 @@ dsi0: dsi@c994000 {
 				phys = <&dsi0_phy>;
 				phy-names = "dsi";
 
+				status = "disabled";
+
 				ports {
 					#address-cells = <1>;
 					#size-cells = <0>;
@@ -1592,6 +1594,7 @@ dsi0_phy: dsi-phy@c994400 {
 
 				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
 				clock-names = "iface", "ref";
+				status = "disabled";
 			};
 		};
 
-- 
2.35.1

[PATCH v3 3/8] arm64: dts: qcom: sdm630: disable GPU by default

[Dmitry Baryshkov]

The SoC's device tree file disables gpucc and adreno's SMMU by default.
So let's disable the GPU too. Moreover it looks like SMMU might be not
usable without additional patches (which means that GPU is unusable
too). No board uses GPU at this moment.

Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration")
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 8697d40e9b74..e8bb170e8b2f 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1050,6 +1050,8 @@ adreno_gpu: gpu@5000000 {
 
 			operating-points-v2 = <&gpu_sdm630_opp_table>;
 
+			status = "disabled";
+
 			gpu_sdm630_opp_table: opp-table {
 				compatible  = "operating-points-v2";
 				opp-775000000 {
-- 
2.35.1

[PATCH v3 4/8] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock

[Dmitry Baryshkov]

According to the downstram DT file, the qusb2phy ref clock should be
GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK.

Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration")
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index e8bb170e8b2f..cca56f2fad96 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 {
 			#phy-cells = <0>;
 
 			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
-				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
+				<&gcc GCC_RX0_USB2_CLKREF_CLK>;
 			clock-names = "cfg_ahb", "ref";
 
 			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
-- 
2.35.1

[PATCH v3 5/8] arm64: dts: qcom: sdm630: add second (HS) USB host support

[Dmitry Baryshkov]

Add DT entries for the second DWC3 USB host, which is limited to the
USB2.0 (HighSpeed), and the corresponding QUSB PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index cca56f2fad96..17a1877587cf 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 {
 			status = "disabled";
 		};
 
+		qusb2phy1: phy@c014000 {
+			compatible = "qcom,sdm660-qusb2-phy";
+			reg = <0x0c014000 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+			nvmem-cells = <&qusb2_hstx_trim>;
+			status = "disabled";
+		};
+
 		sdhc_2: sdhci@c084000 {
 			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0c084000 0x1000>;
@@ -1375,6 +1389,47 @@ opp-384000000 {
 			};
 		};
 
+		usb2: usb@c2f8800 {
+			compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
+			reg = <0x0c2f8800 0x400>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
+				 <&gcc GCC_USB20_MASTER_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB20_SLEEP_CLK>;
+			clock-names = "cfg_noc", "core",
+				      "mock_utmi", "sleep";
+
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <60000000>;
+
+			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hs_phy_irq";
+
+			qcom,select-utmi-as-pipe-clk;
+
+			resets = <&gcc GCC_USB_20_BCR>;
+
+			usb2_dwc3: usb@c200000 {
+				compatible = "snps,dwc3";
+				reg = <0x0c200000 0xc8d0>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+
+				/* This is the HS-only host */
+				maximum-speed = "high-speed";
+				phys = <&qusb2phy1>;
+				phy-names = "usb2-phy";
+				snps,hird-threshold = /bits/ 8 <0>;
+			};
+		};
+
 		mmcc: clock-controller@c8c0000 {
 			compatible = "qcom,mmcc-sdm630";
 			reg = <0x0c8c0000 0x40000>;
-- 
2.35.1

[PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects

[Dmitry Baryshkov]

Replace numeric values with the symbolic names defined in the bindings
header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 17a1877587cf..01a1a1703568 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interconnect/qcom,sdm660.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 {
 			nvmem-cells = <&gpu_speed_bin>;
 			nvmem-cell-names = "speed_bin";
 
-			interconnects = <&gnoc 1 &bimc 5>;
+			interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>;
 			interconnect-names = "gfx-mem";
 
 			operating-points-v2 = <&gpu_sdm630_opp_table>;
@@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 {
 					<&xo_board>;
 			clock-names = "core", "iface", "xo";
 
-			interconnects = <&a2noc 3 &a2noc 10>,
-					<&gnoc 0 &cnoc 28>;
+			interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>,
+					<&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>;
 			operating-points-v2 = <&sdhc2_opp_table>;
 
 			pinctrl-names = "default", "sleep";
@@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 {
 				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
 			clock-names = "core", "iface", "xo", "ice";
 
-			interconnects = <&a2noc 2 &a2noc 10>,
-					<&gnoc 0 &cnoc 27>;
+			interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>,
+					<&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>;
 			interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
 			operating-points-v2 = <&sdhc1_opp_table>;
 			pinctrl-names = "default", "sleep";
@@ -1525,9 +1526,9 @@ mdp: mdp@c901000 {
 					      "core",
 					      "vsync";
 
-				interconnects = <&mnoc 2 &bimc 5>,
-						<&mnoc 3 &bimc 5>,
-						<&gnoc 0 &mnoc 17>;
+				interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>,
+						<&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>,
+						<&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>;
 				interconnect-names = "mdp0-mem",
 						     "mdp1-mem",
 						     "rotator-mem";
@@ -2034,7 +2035,7 @@ camss: camss@ca00000 {
 				"cphy_csid1",
 				"cphy_csid2",
 				"cphy_csid3";
-			interconnects = <&mnoc 5 &bimc 5>;
+			interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>;
 			interconnect-names = "vfe-mem";
 			iommus = <&mmss_smmu 0xc00>,
 				 <&mmss_smmu 0xc01>,
@@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 {
 				 <&mmcc VIDEO_AXI_CLK>,
 				 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
 			clock-names = "core", "iface", "bus", "bus_throttle";
-			interconnects = <&gnoc 0 &mnoc 13>,
-					<&mnoc 4 &bimc 5>;
+			interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>,
+					<&mnoc MASTER_VENUS &bimc SLAVE_EBI>;
 			interconnect-names = "cpu-cfg", "video-mem";
 			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 			iommus = <&mmss_smmu 0x400>,
-- 
2.35.1

[PATCH v3 7/8] arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support

[Dmitry Baryshkov]

The IFC6560 is a board from Inforce Computing, built around the SDA660
SoC. This patch describes core clocks, some regulators from the two
PMICs, debug uart, storage, bluetooth and audio DSP remoteproc.

The regulator settings are inherited from prior work by Konrad Dybcio
and AngeloGioacchino Del Regno.

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sda660-inforce-ifc6560.dts  | 455 ++++++++++++++++++
 2 files changed, 456 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f9e6343acd03..5f717fe0e8d0 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sda660-inforce-ifc6560.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-ganges-kirin.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-discovery.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-pioneer.dtb
diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
new file mode 100644
index 000000000000..ade5c27dafcf
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Ltd.
+ * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
+ * Copyright (c) 2020, AngeloGioacchino Del Regno
+ *                     <angelogioacchino.delregno@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "pm660.dtsi"
+#include "pm660l.dtsi"
+
+/ {
+	model = "Inforce 6560 Single Board Computer";
+	compatible = "inforce,ifc6560", "qcom,sda660";
+	chassis-type = "embedded"; /* SBC */
+
+	aliases {
+		serial0 = &blsp1_uart2;
+		serial1 = &blsp2_uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		volup {
+			label = "Volume Up";
+			gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <15>;
+		};
+	};
+
+	/*
+	 * Until we hook up type-c detection, we
+	 * have to stick with this. But it works.
+	 */
+	extcon_usb: extcon-usb {
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>;
+	};
+
+	hdmi-out {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con: endpoint {
+				remote-endpoint = <&adv7533_out>;
+			};
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3800000>;
+		regulator-max-microvolt = <3800000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	v3p3_bck_bst: v3p3-bck-bst-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "v3p3_bck_bst";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		vin-supply = <&vph_pwr>;
+	};
+
+	v1p2_ldo: v1p2-ldo-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "v1p2_ldo";
+
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+
+		vin-supply = <&vph_pwr>;
+	};
+
+	v5p0_boost: v5p0-boost-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "v5p0_boost";
+
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		vin-supply = <&vph_pwr>;
+	};
+};
+
+&adsp_pil {
+	firmware-name = "qcom/ifc6560/adsp.mbn";
+};
+
+&blsp1_dma {
+	/*
+	 * The board will lock up if we toggle the BLSP clock, unless the
+	 * BAM DMA interconnects support is in place.
+	 */
+	/delete-property/ clocks;
+};
+
+&blsp_i2c6 {
+	status = "okay";
+
+	adv7533: hdmi@39 {
+		compatible = "adi,adv7535";
+		reg = <0x39>, <0x66>;
+		reg-names = "main", "edid";
+
+		interrupt-parent = <&pm660l_gpios>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+		clocks = <&rpmcc RPM_SMD_BB_CLK2>;
+		clock-names = "cec";
+		/*
+		 * Limit to 3 lanes to prevent the bridge from changing amount
+		 * of lanes in the fly. MSM DSI host doesn't like that.
+		 */
+		adi,dsi-lanes = <3>;
+		avdd-supply = <&vreg_l13a_1p8>;
+		dvdd-supply = <&vreg_l13a_1p8>;
+		pvdd-supply = <&vreg_l13a_1p8>;
+		a2vdd-supply = <&vreg_l13a_1p8>;
+		v3p3-supply = <&v3p3_bck_bst>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				adv7533_in: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				adv7533_out: endpoint {
+					remote-endpoint = <&hdmi_con>;
+				};
+			};
+		};
+	};
+};
+
+&blsp1_uart2 {
+	status = "okay";
+};
+
+&blsp2_dma {
+	/*
+	 * The board will lock up if we toggle the BLSP clock, unless the
+	 * BAM DMA interconnects support is in place.
+	 */
+	/delete-property/ clocks;
+};
+
+&blsp2_uart1 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn3990-bt";
+
+		vddio-supply = <&vreg_l13a_1p8>;
+		vddxo-supply = <&vreg_l9a_1p8>;
+		vddrf-supply = <&vreg_l6a_1p3>;
+		vddch0-supply = <&vreg_l19a_3p3>;
+		max-speed = <3200000>;
+	};
+};
+
+&dsi0 {
+	status = "okay";
+	vdda-supply = <&vreg_l1a_1p225>;
+};
+
+&dsi0_out {
+	remote-endpoint = <&adv7533_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&dsi0_phy {
+	status = "okay";
+	vcca-supply = <&vreg_l1b_0p925>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mmss_smmu {
+	status = "okay";
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	status = "okay";
+
+	linux,code = <KEY_VOLUMEUP>;
+};
+
+&qusb2phy {
+	status = "okay";
+
+	vdd-supply = <&vreg_l1b_0p925>;
+	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
+};
+
+&qusb2phy1 {
+	status = "okay";
+
+	vdd-supply = <&vreg_l1b_0p925>;
+	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
+};
+
+&rpm_requests {
+	pm660-regulators {
+		compatible = "qcom,rpm-pm660-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_s6-supply = <&vph_pwr>;
+
+		vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>;
+		vdd_l2_l3-supply = <&vreg_s2b_1p05>;
+		vdd_l5-supply = <&vreg_s2b_1p05>;
+		vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>;
+		vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>;
+
+		vreg_s4a_2p04: s4 {
+			regulator-min-microvolt = <1805000>;
+			regulator-max-microvolt = <2040000>;
+			regulator-enable-ramp-delay = <200>;
+			regulator-ramp-delay = <0>;
+			regulator-always-on;
+		};
+
+		vreg_s5a_1p35: s5 {
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1350000>;
+			regulator-enable-ramp-delay = <200>;
+			regulator-ramp-delay = <0>;
+		};
+
+		vreg_l1a_1p225: l1 {
+			regulator-min-microvolt = <1150000>;
+			regulator-max-microvolt = <1250000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l6a_1p3: l6 {
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1368000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l8a_1p8: l8 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-system-load = <325000>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l9a_1p8: l9 {
+			regulator-min-microvolt = <1804000>;
+			regulator-max-microvolt = <1896000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l13a_1p8: l13 {
+			/* This gives power to the LPDDR4: never turn it off! */
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1944000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+
+		vreg_l19a_3p3: l19 {
+			regulator-min-microvolt = <3312000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-allow-set-load;
+		};
+	};
+
+	pm660l-regulators {
+		compatible = "qcom,rpm-pm660l-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3_s4-supply = <&vph_pwr>;
+		vdd_s5-supply = <&vph_pwr>;
+		vdd_s6-supply = <&vph_pwr>;
+
+		vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>;
+		vdd_l2-supply = <&vreg_bob>;
+		vdd_l3_l5_l7_l8-supply = <&vreg_bob>;
+		vdd_l4_l6-supply = <&vreg_bob>;
+		vdd_bob-supply = <&vph_pwr>;
+
+		vreg_s2b_1p05: s2 {
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1050000>;
+			regulator-enable-ramp-delay = <200>;
+			regulator-ramp-delay = <0>;
+		};
+
+		vreg_l1b_0p925: l1 {
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <925000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l2b_2p95: l2 {
+			regulator-min-microvolt = <1648000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l4b_2p95: l4 {
+			regulator-min-microvolt = <2944000>;
+			regulator-max-microvolt = <2952000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+
+			regulator-min-microamp = <200>;
+			regulator-max-microamp = <600000>;
+			regulator-system-load = <570000>;
+			regulator-allow-set-load;
+		};
+
+		/*
+		 * Downstream specifies a range of 1721-3600mV,
+		 * but the only assigned consumers are SDHCI2 VMMC
+		 * and Coresight QPDI that both request pinned 2.95V.
+		 * Tighten the range to 1.8-3.328 (closest to 3.3) to
+		 * make the mmc driver happy.
+		 */
+		vreg_l5b_2p95: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3328000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-system-load = <800000>;
+			regulator-ramp-delay = <0>;
+			regulator-allow-set-load;
+		};
+
+		vreg_l7b_3p125: l7 {
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3125000>;
+			regulator-enable-ramp-delay = <250>;
+		};
+
+		vreg_l8b_3p3: l8 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <3400000>;
+			regulator-enable-ramp-delay = <250>;
+			regulator-ramp-delay = <0>;
+		};
+
+		vreg_bob: bob {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3624000>;
+			regulator-enable-ramp-delay = <500>;
+			regulator-ramp-delay = <0>;
+		};
+	};
+};
+
+&sdhc_1 {
+	status = "okay";
+	supports-cqe;
+
+	vmmc-supply = <&vreg_l4b_2p95>;
+	vqmmc-supply = <&vreg_l8a_1p8>;
+
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&sdhc_2 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>;
+	pinctrl1 = <&sdc2_state_off &sdc2_card_det_n>;
+
+	vmmc-supply = <&vreg_l5b_2p95>;
+	vqmmc-supply = <&vreg_l2b_2p95>;
+
+	cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+	no-sdio;
+	no-emmc;
+};
+
+&tlmm {
+	gpio-reserved-ranges = <0 4>, <8 4>;
+
+	sdc2_card_det_n: sd-card-det-n {
+		pins = "gpio54";
+		function = "gpio";
+		bias-pull-up;
+	};
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc3 {
+	dr_mode = "peripheral";
+	extcon = <&extcon_usb>;
+};
-- 
2.35.1

[PATCH v3 8/8] dt-bindings: arm: qcom: document sda660 SoC and ifc6560 board

[Dmitry Baryshkov]

Add binding documentation for the Inforce IFC6560 board which uses
Snapdragon SDA660.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 129cdd246223..ac4ee0f874ea 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -41,6 +41,7 @@ description: |
         sa8155p
         sc7180
         sc7280
+        sda660
         sdm630
         sdm632
         sdm660
@@ -225,6 +226,11 @@ properties:
               - google,senor
           - const: qcom,sc7280
 
+      - items:
+          - enum:
+              - inforce,ifc6560
+          - const: qcom,sda660
+
       - items:
           - enum:
               - fairphone,fp3
-- 
2.35.1

Re: [PATCH v3 2/8] arm64: dts: qcom: sdm630: disable dsi1/dsi1_phy by default

[Marijn Suijten]

Title copy-paste error: it should read dsi0/dsi0_phy.  Can you also
reorder this patch together with the dsi1/dsi1_phy one, and perhaps they
should just be squashed?  Otherwise, does a Suggested-by: make sense
here?

- Marijn

On 2022-05-14 02:45:12, Dmitry Baryshkov wrote:
> Follow the typical practice and keep DSI0/DSI0 PHY disabled by default.
> They should be enabled in the board DT files. No existing boards use
> them at this moment.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index 240293592ef9..8697d40e9b74 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -1559,6 +1559,8 @@ dsi0: dsi@c994000 {
>  				phys = <&dsi0_phy>;
>  				phy-names = "dsi";
>  
> +				status = "disabled";
> +
>  				ports {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> @@ -1592,6 +1594,7 @@ dsi0_phy: dsi-phy@c994400 {
>  
>  				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
>  				clock-names = "iface", "ref";
> +				status = "disabled";
>  			};
>  		};
>  
> -- 
> 2.35.1
> 

Re: [PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects

[Marijn Suijten]

On 2022-05-14 02:45:16, Dmitry Baryshkov wrote:
> Replace numeric values with the symbolic names defined in the bindings
> header.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Seems there is one off-by-one copy-paste error.  With that addressed:

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++-----------
>  1 file changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index 17a1877587cf..01a1a1703568 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -8,6 +8,7 @@
>  #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
>  #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
>  #include <dt-bindings/clock/qcom,rpmcc.h>
> +#include <dt-bindings/interconnect/qcom,sdm660.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 {
>  			nvmem-cells = <&gpu_speed_bin>;
>  			nvmem-cell-names = "speed_bin";
>  
> -			interconnects = <&gnoc 1 &bimc 5>;
> +			interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>;

From qcom,sdm660.h:

    /* GNOC */
    #define MASTER_APSS_PROC		0
    #define SLAVE_GNOC_BIMC			1
    #define SLAVE_GNOC_SNOC			2

Seems like the left side should be SLAVE_GNOC_BIMC?  Unless this
semantic change is intended, in which case it should be clearly
documented in its own commit with a Fixes tag.

The rest looks correct.

- Marijn

>  			interconnect-names = "gfx-mem";
>  
>  			operating-points-v2 = <&gpu_sdm630_opp_table>;
> @@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 {
>  					<&xo_board>;
>  			clock-names = "core", "iface", "xo";
>  
> -			interconnects = <&a2noc 3 &a2noc 10>,
> -					<&gnoc 0 &cnoc 28>;
> +			interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>,
> +					<&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>;
>  			operating-points-v2 = <&sdhc2_opp_table>;
>  
>  			pinctrl-names = "default", "sleep";
> @@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 {
>  				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
>  			clock-names = "core", "iface", "xo", "ice";
>  
> -			interconnects = <&a2noc 2 &a2noc 10>,
> -					<&gnoc 0 &cnoc 27>;
> +			interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>,
> +					<&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>;
>  			interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
>  			operating-points-v2 = <&sdhc1_opp_table>;
>  			pinctrl-names = "default", "sleep";
> @@ -1525,9 +1526,9 @@ mdp: mdp@c901000 {
>  					      "core",
>  					      "vsync";
>  
> -				interconnects = <&mnoc 2 &bimc 5>,
> -						<&mnoc 3 &bimc 5>,
> -						<&gnoc 0 &mnoc 17>;
> +				interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>,
> +						<&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>,
> +						<&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>;
>  				interconnect-names = "mdp0-mem",
>  						     "mdp1-mem",
>  						     "rotator-mem";
> @@ -2034,7 +2035,7 @@ camss: camss@ca00000 {
>  				"cphy_csid1",
>  				"cphy_csid2",
>  				"cphy_csid3";
> -			interconnects = <&mnoc 5 &bimc 5>;
> +			interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>;
>  			interconnect-names = "vfe-mem";
>  			iommus = <&mmss_smmu 0xc00>,
>  				 <&mmss_smmu 0xc01>,
> @@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 {
>  				 <&mmcc VIDEO_AXI_CLK>,
>  				 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
>  			clock-names = "core", "iface", "bus", "bus_throttle";
> -			interconnects = <&gnoc 0 &mnoc 13>,
> -					<&mnoc 4 &bimc 5>;
> +			interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>,
> +					<&mnoc MASTER_VENUS &bimc SLAVE_EBI>;
>  			interconnect-names = "cpu-cfg", "video-mem";
>  			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
>  			iommus = <&mmss_smmu 0x400>,
> -- 
> 2.35.1
> 

Re: [PATCH v3 3/8] arm64: dts: qcom: sdm630: disable GPU by default

[Marijn Suijten]

On 2022-05-14 02:45:13, Dmitry Baryshkov wrote:
> The SoC's device tree file disables gpucc and adreno's SMMU by default.
> So let's disable the GPU too. Moreover it looks like SMMU might be not
> usable without additional patches (which means that GPU is unusable
> too). No board uses GPU at this moment.
> 
> Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration")
> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index 8697d40e9b74..e8bb170e8b2f 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -1050,6 +1050,8 @@ adreno_gpu: gpu@5000000 {
>  
>  			operating-points-v2 = <&gpu_sdm630_opp_table>;
>  
> +			status = "disabled";
> +
>  			gpu_sdm630_opp_table: opp-table {
>  				compatible  = "operating-points-v2";
>  				opp-775000000 {
> -- 
> 2.35.1
> 

Re: [PATCH v3 4/8] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock

[Marijn Suijten]

On 2022-05-14 02:45:14, Dmitry Baryshkov wrote:
> According to the downstram DT file, the qusb2phy ref clock should be
> GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK.
> 
> Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration")
> Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

One nit below.

> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index e8bb170e8b2f..cca56f2fad96 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 {
>  			#phy-cells = <0>;
>  
>  			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> -				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
> +				<&gcc GCC_RX0_USB2_CLKREF_CLK>;

While at it, should this patch fix the indentation or shall I or you do
a one-off patch correcting the entire file (either before or after your
series)?

- Marijn

>  			clock-names = "cfg_ahb", "ref";
>  
>  			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> -- 
> 2.35.1
> 

Re: [PATCH v3 5/8] arm64: dts: qcom: sdm630: add second (HS) USB host support

[Marijn Suijten]

On 2022-05-14 02:45:15, Dmitry Baryshkov wrote:
> Add DT entries for the second DWC3 USB host, which is limited to the
> USB2.0 (HighSpeed), and the corresponding QUSB PHY.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

Some minor style nits below.

> ---
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> index cca56f2fad96..17a1877587cf 100644
> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> @@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 {
>  			status = "disabled";
>  		};
>  
> +		qusb2phy1: phy@c014000 {

Should we rename qusb2phy to qusb2phy0?

> +			compatible = "qcom,sdm660-qusb2-phy";
> +			reg = <0x0c014000 0x180>;
> +			#phy-cells = <0>;
> +
> +			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> +				<&gcc GCC_RX1_USB2_CLKREF_CLK>;

Should use the correct indentation from the get-go?

> +			clock-names = "cfg_ahb", "ref";
> +
> +			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
> +			nvmem-cells = <&qusb2_hstx_trim>;
> +			status = "disabled";
> +		};
> +
>  		sdhc_2: sdhci@c084000 {
>  			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
>  			reg = <0x0c084000 0x1000>;
> @@ -1375,6 +1389,47 @@ opp-384000000 {
>  			};
>  		};
>  
> +		usb2: usb@c2f8800 {
> +			compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
> +			reg = <0x0c2f8800 0x400>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
> +				 <&gcc GCC_USB20_MASTER_CLK>,
> +				 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +				 <&gcc GCC_USB20_SLEEP_CLK>;
> +			clock-names = "cfg_noc", "core",
> +				      "mock_utmi", "sleep";

This fits on one line and stays at 79 characters.

- Marijn

> +
> +			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
> +					  <&gcc GCC_USB20_MASTER_CLK>;
> +			assigned-clock-rates = <19200000>, <60000000>;
> +
> +			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hs_phy_irq";
> +
> +			qcom,select-utmi-as-pipe-clk;
> +
> +			resets = <&gcc GCC_USB_20_BCR>;
> +
> +			usb2_dwc3: usb@c200000 {
> +				compatible = "snps,dwc3";
> +				reg = <0x0c200000 0xc8d0>;
> +				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> +				snps,dis_u2_susphy_quirk;
> +				snps,dis_enblslpm_quirk;
> +
> +				/* This is the HS-only host */
> +				maximum-speed = "high-speed";
> +				phys = <&qusb2phy1>;
> +				phy-names = "usb2-phy";
> +				snps,hird-threshold = /bits/ 8 <0>;
> +			};
> +		};
> +
>  		mmcc: clock-controller@c8c0000 {
>  			compatible = "qcom,mmcc-sdm630";
>  			reg = <0x0c8c0000 0x40000>;
> -- 
> 2.35.1
> 

Re: [PATCH v3 7/8] arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support

[Marijn Suijten]

On 2022-05-14 02:45:17, Dmitry Baryshkov wrote:
> The IFC6560 is a board from Inforce Computing, built around the SDA660
> SoC. This patch describes core clocks, some regulators from the two
> PMICs, debug uart, storage, bluetooth and audio DSP remoteproc.
> 
> The regulator settings are inherited from prior work by Konrad Dybcio
> and AngeloGioacchino Del Regno.
> 
> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/Makefile             |   1 +
>  .../boot/dts/qcom/sda660-inforce-ifc6560.dts  | 455 ++++++++++++++++++
>  2 files changed, 456 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index f9e6343acd03..5f717fe0e8d0 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= sda660-inforce-ifc6560.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-ganges-kirin.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-discovery.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-pioneer.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
> new file mode 100644
> index 000000000000..ade5c27dafcf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, Linaro Ltd.
> + * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
> + * Copyright (c) 2020, AngeloGioacchino Del Regno
> + *                     <angelogioacchino.delregno@somainline.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "sdm660.dtsi"
> +#include "pm660.dtsi"
> +#include "pm660l.dtsi"
> +
> +/ {
> +	model = "Inforce 6560 Single Board Computer";
> +	compatible = "inforce,ifc6560", "qcom,sda660";
> +	chassis-type = "embedded"; /* SBC */
> +
> +	aliases {
> +		serial0 = &blsp1_uart2;
> +		serial1 = &blsp2_uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		volup {
> +			label = "Volume Up";
> +			gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_VOLUMEUP>;
> +			debounce-interval = <15>;
> +		};
> +	};
> +
> +	/*
> +	 * Until we hook up type-c detection, we
> +	 * have to stick with this. But it works.
> +	 */
> +	extcon_usb: extcon-usb {
> +		compatible = "linux,extcon-usb-gpio";
> +		id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	hdmi-out {
> +		compatible = "hdmi-connector";
> +		type = "a";
> +
> +		port {
> +			hdmi_con: endpoint {
> +				remote-endpoint = <&adv7533_out>;
> +			};
> +		};
> +	};
> +
> +	vph_pwr: vph-pwr-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vph_pwr";
> +		regulator-min-microvolt = <3800000>;
> +		regulator-max-microvolt = <3800000>;
> +
> +		regulator-always-on;
> +		regulator-boot-on;
> +	};
> +
> +	v3p3_bck_bst: v3p3-bck-bst-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "v3p3_bck_bst";
> +
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +
> +		vin-supply = <&vph_pwr>;
> +	};
> +
> +	v1p2_ldo: v1p2-ldo-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "v1p2_ldo";
> +
> +		regulator-min-microvolt = <1200000>;
> +		regulator-max-microvolt = <1200000>;
> +
> +		vin-supply = <&vph_pwr>;
> +	};
> +
> +	v5p0_boost: v5p0-boost-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "v5p0_boost";
> +
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +
> +		vin-supply = <&vph_pwr>;
> +	};
> +};
> +
> +&adsp_pil {
> +	firmware-name = "qcom/ifc6560/adsp.mbn";
> +};
> +
> +&blsp1_dma {
> +	/*
> +	 * The board will lock up if we toggle the BLSP clock, unless the
> +	 * BAM DMA interconnects support is in place.
> +	 */
> +	/delete-property/ clocks;
> +};
> +
> +&blsp_i2c6 {
> +	status = "okay";
> +
> +	adv7533: hdmi@39 {
> +		compatible = "adi,adv7535";
> +		reg = <0x39>, <0x66>;
> +		reg-names = "main", "edid";
> +
> +		interrupt-parent = <&pm660l_gpios>;
> +		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
> +
> +		clocks = <&rpmcc RPM_SMD_BB_CLK2>;
> +		clock-names = "cec";
> +		/*
> +		 * Limit to 3 lanes to prevent the bridge from changing amount
> +		 * of lanes in the fly. MSM DSI host doesn't like that.
> +		 */
> +		adi,dsi-lanes = <3>;
> +		avdd-supply = <&vreg_l13a_1p8>;
> +		dvdd-supply = <&vreg_l13a_1p8>;
> +		pvdd-supply = <&vreg_l13a_1p8>;
> +		a2vdd-supply = <&vreg_l13a_1p8>;
> +		v3p3-supply = <&v3p3_bck_bst>;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +
> +				adv7533_in: endpoint {
> +					remote-endpoint = <&dsi0_out>;
> +				};
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +
> +				adv7533_out: endpoint {
> +					remote-endpoint = <&hdmi_con>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&blsp1_uart2 {
> +	status = "okay";
> +};
> +
> +&blsp2_dma {
> +	/*
> +	 * The board will lock up if we toggle the BLSP clock, unless the
> +	 * BAM DMA interconnects support is in place.
> +	 */
> +	/delete-property/ clocks;
> +};
> +
> +&blsp2_uart1 {
> +	status = "okay";
> +
> +	bluetooth {
> +		compatible = "qcom,wcn3990-bt";
> +
> +		vddio-supply = <&vreg_l13a_1p8>;
> +		vddxo-supply = <&vreg_l9a_1p8>;
> +		vddrf-supply = <&vreg_l6a_1p3>;
> +		vddch0-supply = <&vreg_l19a_3p3>;
> +		max-speed = <3200000>;
> +	};
> +};
> +
> +&dsi0 {
> +	status = "okay";
> +	vdda-supply = <&vreg_l1a_1p225>;
> +};
> +
> +&dsi0_out {
> +	remote-endpoint = <&adv7533_in>;
> +	data-lanes = <0 1 2 3>;
> +};
> +
> +&dsi0_phy {
> +	status = "okay";
> +	vcca-supply = <&vreg_l1b_0p925>;

@Konrad: It looks like we have this regulator downstream in mdss_dsi but
not in the upstream DT, is it missing by accident?

> +};
> +
> +&mdss {
> +	status = "okay";
> +};
> +
> +&mmss_smmu {
> +	status = "okay";
> +};
> +
> +&pon_pwrkey {
> +	status = "okay";
> +};
> +
> +&pon_resin {
> +	status = "okay";
> +
> +	linux,code = <KEY_VOLUMEUP>;
> +};
> +
> +&qusb2phy {
> +	status = "okay";
> +
> +	vdd-supply = <&vreg_l1b_0p925>;
> +	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
> +};
> +
> +&qusb2phy1 {
> +	status = "okay";
> +
> +	vdd-supply = <&vreg_l1b_0p925>;
> +	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
> +};
> +
> +&rpm_requests {
> +	pm660-regulators {
> +		compatible = "qcom,rpm-pm660-regulators";
> +
> +		vdd_s1-supply = <&vph_pwr>;
> +		vdd_s2-supply = <&vph_pwr>;
> +		vdd_s3-supply = <&vph_pwr>;
> +		vdd_s4-supply = <&vph_pwr>;
> +		vdd_s5-supply = <&vph_pwr>;
> +		vdd_s6-supply = <&vph_pwr>;
> +
> +		vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>;
> +		vdd_l2_l3-supply = <&vreg_s2b_1p05>;
> +		vdd_l5-supply = <&vreg_s2b_1p05>;
> +		vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>;
> +		vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>;
> +
> +		vreg_s4a_2p04: s4 {
> +			regulator-min-microvolt = <1805000>;
> +			regulator-max-microvolt = <2040000>;
> +			regulator-enable-ramp-delay = <200>;
> +			regulator-ramp-delay = <0>;
> +			regulator-always-on;
> +		};
> +
> +		vreg_s5a_1p35: s5 {
> +			regulator-min-microvolt = <1224000>;
> +			regulator-max-microvolt = <1350000>;
> +			regulator-enable-ramp-delay = <200>;
> +			regulator-ramp-delay = <0>;
> +		};
> +
> +		vreg_l1a_1p225: l1 {
> +			regulator-min-microvolt = <1150000>;
> +			regulator-max-microvolt = <1250000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l6a_1p3: l6 {
> +			regulator-min-microvolt = <1304000>;
> +			regulator-max-microvolt = <1368000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l8a_1p8: l8 {
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1800000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-system-load = <325000>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l9a_1p8: l9 {
> +			regulator-min-microvolt = <1804000>;
> +			regulator-max-microvolt = <1896000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l13a_1p8: l13 {
> +			/* This gives power to the LPDDR4: never turn it off! */
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <1944000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +		};
> +
> +		vreg_l19a_3p3: l19 {
> +			regulator-min-microvolt = <3312000>;
> +			regulator-max-microvolt = <3400000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-allow-set-load;
> +		};
> +	};
> +
> +	pm660l-regulators {
> +		compatible = "qcom,rpm-pm660l-regulators";
> +
> +		vdd_s1-supply = <&vph_pwr>;
> +		vdd_s2-supply = <&vph_pwr>;
> +		vdd_s3_s4-supply = <&vph_pwr>;
> +		vdd_s5-supply = <&vph_pwr>;
> +		vdd_s6-supply = <&vph_pwr>;
> +
> +		vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>;
> +		vdd_l2-supply = <&vreg_bob>;
> +		vdd_l3_l5_l7_l8-supply = <&vreg_bob>;
> +		vdd_l4_l6-supply = <&vreg_bob>;
> +		vdd_bob-supply = <&vph_pwr>;
> +
> +		vreg_s2b_1p05: s2 {
> +			regulator-min-microvolt = <1050000>;
> +			regulator-max-microvolt = <1050000>;
> +			regulator-enable-ramp-delay = <200>;
> +			regulator-ramp-delay = <0>;
> +		};
> +
> +		vreg_l1b_0p925: l1 {
> +			regulator-min-microvolt = <800000>;
> +			regulator-max-microvolt = <925000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l2b_2p95: l2 {
> +			regulator-min-microvolt = <1648000>;
> +			regulator-max-microvolt = <3100000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l4b_2p95: l4 {
> +			regulator-min-microvolt = <2944000>;
> +			regulator-max-microvolt = <2952000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +
> +			regulator-min-microamp = <200>;
> +			regulator-max-microamp = <600000>;
> +			regulator-system-load = <570000>;
> +			regulator-allow-set-load;
> +		};
> +
> +		/*
> +		 * Downstream specifies a range of 1721-3600mV,
> +		 * but the only assigned consumers are SDHCI2 VMMC
> +		 * and Coresight QPDI that both request pinned 2.95V.
> +		 * Tighten the range to 1.8-3.328 (closest to 3.3) to
> +		 * make the mmc driver happy.
> +		 */
> +		vreg_l5b_2p95: l5 {
> +			regulator-min-microvolt = <1800000>;
> +			regulator-max-microvolt = <3328000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-system-load = <800000>;
> +			regulator-ramp-delay = <0>;
> +			regulator-allow-set-load;
> +		};
> +
> +		vreg_l7b_3p125: l7 {
> +			regulator-min-microvolt = <2700000>;
> +			regulator-max-microvolt = <3125000>;
> +			regulator-enable-ramp-delay = <250>;
> +		};
> +
> +		vreg_l8b_3p3: l8 {
> +			regulator-min-microvolt = <2800000>;
> +			regulator-max-microvolt = <3400000>;
> +			regulator-enable-ramp-delay = <250>;
> +			regulator-ramp-delay = <0>;
> +		};
> +
> +		vreg_bob: bob {
> +			regulator-min-microvolt = <3300000>;
> +			regulator-max-microvolt = <3624000>;
> +			regulator-enable-ramp-delay = <500>;
> +			regulator-ramp-delay = <0>;
> +		};
> +	};
> +};
> +
> +&sdhc_1 {
> +	status = "okay";
> +	supports-cqe;
> +
> +	vmmc-supply = <&vreg_l4b_2p95>;
> +	vqmmc-supply = <&vreg_l8a_1p8>;
> +
> +	mmc-ddr-1_8v;
> +	mmc-hs400-1_8v;
> +	mmc-hs400-enhanced-strobe;
> +};
> +
> +&sdhc_2 {
> +	status = "okay";
> +
> +	pinctrl-names = "default";

Missing , "sleep".

> +	pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>;
> +	pinctrl1 = <&sdc2_state_off &sdc2_card_det_n>;

Missing hyphen.

> +
> +	vmmc-supply = <&vreg_l5b_2p95>;
> +	vqmmc-supply = <&vreg_l2b_2p95>;
> +
> +	cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
> +	no-sdio;
> +	no-emmc;
> +};
> +
> +&tlmm {
> +	gpio-reserved-ranges = <0 4>, <8 4>;
> +
> +	sdc2_card_det_n: sd-card-det-n {
> +		pins = "gpio54";
> +		function = "gpio";
> +		bias-pull-up;
> +	};

It seems this pin is also already declared in sdc2-on/off in
sdm630.dtsi, with the same bias-pull-up in the -on case.  However, the
-off case sets bias-disable, won't that conflict?  (not in this moment,
because the clashing pinctrl pairs are "unused" with the typos above).

I have always been under the impression this GPIO is board-specific and
should be moved out of sdm630.dtsi into board-specific DTs, is that
true?

- Marijn

> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> +
> +&usb2_dwc3 {
> +	dr_mode = "host";
> +};
> +
> +&usb3 {
> +	status = "okay";
> +};
> +
> +&usb3_dwc3 {
> +	dr_mode = "peripheral";
> +	extcon = <&extcon_usb>;
> +};
> -- 
> 2.35.1
> 

Re: [PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects

[Dmitry Baryshkov]

On Sat, 14 May 2022 at 12:45, Marijn Suijten
<marijn.suijten@somainline.org> wrote:
>
> On 2022-05-14 02:45:16, Dmitry Baryshkov wrote:
> > Replace numeric values with the symbolic names defined in the bindings
> > header.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Seems there is one off-by-one copy-paste error.  With that addressed:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> > ---
> >  arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++-----------
> >  1 file changed, 12 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > index 17a1877587cf..01a1a1703568 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > @@ -8,6 +8,7 @@
> >  #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
> >  #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
> >  #include <dt-bindings/clock/qcom,rpmcc.h>
> > +#include <dt-bindings/interconnect/qcom,sdm660.h>
> >  #include <dt-bindings/power/qcom-rpmpd.h>
> >  #include <dt-bindings/gpio/gpio.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 {
> >                       nvmem-cells = <&gpu_speed_bin>;
> >                       nvmem-cell-names = "speed_bin";
> >
> > -                     interconnects = <&gnoc 1 &bimc 5>;
> > +                     interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>;
>
> From qcom,sdm660.h:
>
>     /* GNOC */
>     #define MASTER_APSS_PROC            0
>     #define SLAVE_GNOC_BIMC                     1
>     #define SLAVE_GNOC_SNOC                     2
>
> Seems like the left side should be SLAVE_GNOC_BIMC?  Unless this
> semantic change is intended, in which case it should be clearly
> documented in its own commit with a Fixes tag.

I don't think there can be a slave on the left side of the ICC path.
But nice catch anyway. Downstream uses MSM_BUS_MASTER_GRAPHICS_3D
here, which corresponds to <&bimc MASTER_OXILI>.
Could you please double check this?

>
> The rest looks correct.
>
> - Marijn
>
> >                       interconnect-names = "gfx-mem";
> >
> >                       operating-points-v2 = <&gpu_sdm630_opp_table>;
> > @@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 {
> >                                       <&xo_board>;
> >                       clock-names = "core", "iface", "xo";
> >
> > -                     interconnects = <&a2noc 3 &a2noc 10>,
> > -                                     <&gnoc 0 &cnoc 28>;
> > +                     interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>,
> > +                                     <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>;
> >                       operating-points-v2 = <&sdhc2_opp_table>;
> >
> >                       pinctrl-names = "default", "sleep";
> > @@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 {
> >                                <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> >                       clock-names = "core", "iface", "xo", "ice";
> >
> > -                     interconnects = <&a2noc 2 &a2noc 10>,
> > -                                     <&gnoc 0 &cnoc 27>;
> > +                     interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>,
> > +                                     <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>;
> >                       interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
> >                       operating-points-v2 = <&sdhc1_opp_table>;
> >                       pinctrl-names = "default", "sleep";
> > @@ -1525,9 +1526,9 @@ mdp: mdp@c901000 {
> >                                             "core",
> >                                             "vsync";
> >
> > -                             interconnects = <&mnoc 2 &bimc 5>,
> > -                                             <&mnoc 3 &bimc 5>,
> > -                                             <&gnoc 0 &mnoc 17>;
> > +                             interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>,
> > +                                             <&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>,
> > +                                             <&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>;
> >                               interconnect-names = "mdp0-mem",
> >                                                    "mdp1-mem",
> >                                                    "rotator-mem";
> > @@ -2034,7 +2035,7 @@ camss: camss@ca00000 {
> >                               "cphy_csid1",
> >                               "cphy_csid2",
> >                               "cphy_csid3";
> > -                     interconnects = <&mnoc 5 &bimc 5>;
> > +                     interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>;
> >                       interconnect-names = "vfe-mem";
> >                       iommus = <&mmss_smmu 0xc00>,
> >                                <&mmss_smmu 0xc01>,
> > @@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 {
> >                                <&mmcc VIDEO_AXI_CLK>,
> >                                <&mmcc THROTTLE_VIDEO_AXI_CLK>;
> >                       clock-names = "core", "iface", "bus", "bus_throttle";
> > -                     interconnects = <&gnoc 0 &mnoc 13>,
> > -                                     <&mnoc 4 &bimc 5>;
> > +                     interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>,
> > +                                     <&mnoc MASTER_VENUS &bimc SLAVE_EBI>;
> >                       interconnect-names = "cpu-cfg", "video-mem";
> >                       interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> >                       iommus = <&mmss_smmu 0x400>,
> > --
> > 2.35.1
> >



-- 
With best wishes
Dmitry

Re: [PATCH v3 2/8] arm64: dts: qcom: sdm630: disable dsi1/dsi1_phy by default

[Dmitry Baryshkov]

On 14/05/2022 12:37, Marijn Suijten wrote:
> Title copy-paste error: it should read dsi0/dsi0_phy.  Can you also
> reorder this patch together with the dsi1/dsi1_phy one, and perhaps they
> should just be squashed?  Otherwise, does a Suggested-by: make sense
> here?

Yes, it does. Please excuse me.

> 
> - Marijn
> 
> On 2022-05-14 02:45:12, Dmitry Baryshkov wrote:
>> Follow the typical practice and keep DSI0/DSI0 PHY disabled by default.
>> They should be enabled in the board DT files. No existing boards use
>> them at this moment.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> index 240293592ef9..8697d40e9b74 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> @@ -1559,6 +1559,8 @@ dsi0: dsi@c994000 {
>>   				phys = <&dsi0_phy>;
>>   				phy-names = "dsi";
>>   
>> +				status = "disabled";
>> +
>>   				ports {
>>   					#address-cells = <1>;
>>   					#size-cells = <0>;
>> @@ -1592,6 +1594,7 @@ dsi0_phy: dsi-phy@c994400 {
>>   
>>   				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
>>   				clock-names = "iface", "ref";
>> +				status = "disabled";
>>   			};
>>   		};
>>   
>> -- 
>> 2.35.1
>>


-- 
With best wishes
Dmitry

Re: [PATCH v3 4/8] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock

[Dmitry Baryshkov]

On 14/05/2022 12:56, Marijn Suijten wrote:
> On 2022-05-14 02:45:14, Dmitry Baryshkov wrote:
>> According to the downstram DT file, the qusb2phy ref clock should be
>> GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK.
>>
>> Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration")
>> Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> 
> One nit below.
> 
>> ---
>>   arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> index e8bb170e8b2f..cca56f2fad96 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
>> @@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 {
>>   			#phy-cells = <0>;
>>   
>>   			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
>> -				<&gcc GCC_RX1_USB2_CLKREF_CLK>;
>> +				<&gcc GCC_RX0_USB2_CLKREF_CLK>;
> 
> While at it, should this patch fix the indentation or shall I or you do
> a one-off patch correcting the entire file (either before or after your
> series)?

I'd prefer to land these two series, after that we can indent the rest.

> 
> - Marijn
> 
>>   			clock-names = "cfg_ahb", "ref";
>>   
>>   			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>> -- 
>> 2.35.1
>>


-- 
With best wishes
Dmitry

Re: [PATCH v3 7/8] arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support

[Dmitry Baryshkov]

On 14/05/2022 13:31, Marijn Suijten wrote:
> On 2022-05-14 02:45:17, Dmitry Baryshkov wrote:
>> The IFC6560 is a board from Inforce Computing, built around the SDA660
>> SoC. This patch describes core clocks, some regulators from the two
>> PMICs, debug uart, storage, bluetooth and audio DSP remoteproc.
>>
>> The regulator settings are inherited from prior work by Konrad Dybcio
>> and AngeloGioacchino Del Regno.
>>
>> Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile             |   1 +
>>   .../boot/dts/qcom/sda660-inforce-ifc6560.dts  | 455 ++++++++++++++++++
>>   2 files changed, 456 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index f9e6343acd03..5f717fe0e8d0 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-herobrine-herobrine-r1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-idp2.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sc7280-crd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= sda660-inforce-ifc6560.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-ganges-kirin.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-discovery.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= sdm630-sony-xperia-nile-pioneer.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
>> new file mode 100644
>> index 000000000000..ade5c27dafcf
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
>> @@ -0,0 +1,455 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2021, Linaro Ltd.
>> + * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
>> + * Copyright (c) 2020, AngeloGioacchino Del Regno
>> + *                     <angelogioacchino.delregno@somainline.org>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "sdm660.dtsi"
>> +#include "pm660.dtsi"
>> +#include "pm660l.dtsi"
>> +
>> +/ {
>> +	model = "Inforce 6560 Single Board Computer";
>> +	compatible = "inforce,ifc6560", "qcom,sda660";
>> +	chassis-type = "embedded"; /* SBC */
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +		serial1 = &blsp2_uart1;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	gpio-keys {
>> +		compatible = "gpio-keys";
>> +
>> +		volup {
>> +			label = "Volume Up";
>> +			gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
>> +			linux,code = <KEY_VOLUMEUP>;
>> +			debounce-interval = <15>;
>> +		};
>> +	};
>> +
>> +	/*
>> +	 * Until we hook up type-c detection, we
>> +	 * have to stick with this. But it works.
>> +	 */
>> +	extcon_usb: extcon-usb {
>> +		compatible = "linux,extcon-usb-gpio";
>> +		id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>;
>> +	};
>> +
>> +	hdmi-out {
>> +		compatible = "hdmi-connector";
>> +		type = "a";
>> +
>> +		port {
>> +			hdmi_con: endpoint {
>> +				remote-endpoint = <&adv7533_out>;
>> +			};
>> +		};
>> +	};
>> +
>> +	vph_pwr: vph-pwr-regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "vph_pwr";
>> +		regulator-min-microvolt = <3800000>;
>> +		regulator-max-microvolt = <3800000>;
>> +
>> +		regulator-always-on;
>> +		regulator-boot-on;
>> +	};
>> +
>> +	v3p3_bck_bst: v3p3-bck-bst-regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "v3p3_bck_bst";
>> +
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +
>> +		vin-supply = <&vph_pwr>;
>> +	};
>> +
>> +	v1p2_ldo: v1p2-ldo-regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "v1p2_ldo";
>> +
>> +		regulator-min-microvolt = <1200000>;
>> +		regulator-max-microvolt = <1200000>;
>> +
>> +		vin-supply = <&vph_pwr>;
>> +	};
>> +
>> +	v5p0_boost: v5p0-boost-regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "v5p0_boost";
>> +
>> +		regulator-min-microvolt = <5000000>;
>> +		regulator-max-microvolt = <5000000>;
>> +
>> +		vin-supply = <&vph_pwr>;
>> +	};
>> +};
>> +
>> +&adsp_pil {
>> +	firmware-name = "qcom/ifc6560/adsp.mbn";
>> +};
>> +
>> +&blsp1_dma {
>> +	/*
>> +	 * The board will lock up if we toggle the BLSP clock, unless the
>> +	 * BAM DMA interconnects support is in place.
>> +	 */
>> +	/delete-property/ clocks;
>> +};
>> +
>> +&blsp_i2c6 {
>> +	status = "okay";
>> +
>> +	adv7533: hdmi@39 {
>> +		compatible = "adi,adv7535";
>> +		reg = <0x39>, <0x66>;
>> +		reg-names = "main", "edid";
>> +
>> +		interrupt-parent = <&pm660l_gpios>;
>> +		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
>> +
>> +		clocks = <&rpmcc RPM_SMD_BB_CLK2>;
>> +		clock-names = "cec";
>> +		/*
>> +		 * Limit to 3 lanes to prevent the bridge from changing amount
>> +		 * of lanes in the fly. MSM DSI host doesn't like that.
>> +		 */
>> +		adi,dsi-lanes = <3>;
>> +		avdd-supply = <&vreg_l13a_1p8>;
>> +		dvdd-supply = <&vreg_l13a_1p8>;
>> +		pvdd-supply = <&vreg_l13a_1p8>;
>> +		a2vdd-supply = <&vreg_l13a_1p8>;
>> +		v3p3-supply = <&v3p3_bck_bst>;
>> +
>> +		ports {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			port@0 {
>> +				reg = <0>;
>> +
>> +				adv7533_in: endpoint {
>> +					remote-endpoint = <&dsi0_out>;
>> +				};
>> +			};
>> +
>> +			port@1 {
>> +				reg = <1>;
>> +
>> +				adv7533_out: endpoint {
>> +					remote-endpoint = <&hdmi_con>;
>> +				};
>> +			};
>> +		};
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	status = "okay";
>> +};
>> +
>> +&blsp2_dma {
>> +	/*
>> +	 * The board will lock up if we toggle the BLSP clock, unless the
>> +	 * BAM DMA interconnects support is in place.
>> +	 */
>> +	/delete-property/ clocks;
>> +};
>> +
>> +&blsp2_uart1 {
>> +	status = "okay";
>> +
>> +	bluetooth {
>> +		compatible = "qcom,wcn3990-bt";
>> +
>> +		vddio-supply = <&vreg_l13a_1p8>;
>> +		vddxo-supply = <&vreg_l9a_1p8>;
>> +		vddrf-supply = <&vreg_l6a_1p3>;
>> +		vddch0-supply = <&vreg_l19a_3p3>;
>> +		max-speed = <3200000>;
>> +	};
>> +};
>> +
>> +&dsi0 {
>> +	status = "okay";
>> +	vdda-supply = <&vreg_l1a_1p225>;
>> +};
>> +
>> +&dsi0_out {
>> +	remote-endpoint = <&adv7533_in>;
>> +	data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&dsi0_phy {
>> +	status = "okay";
>> +	vcca-supply = <&vreg_l1b_0p925>;
> 
> @Konrad: It looks like we have this regulator downstream in mdss_dsi but
> not in the upstream DT, is it missing by accident?
> 
>> +};
>> +
>> +&mdss {
>> +	status = "okay";
>> +};
>> +
>> +&mmss_smmu {
>> +	status = "okay";
>> +};
>> +
>> +&pon_pwrkey {
>> +	status = "okay";
>> +};
>> +
>> +&pon_resin {
>> +	status = "okay";
>> +
>> +	linux,code = <KEY_VOLUMEUP>;
>> +};
>> +
>> +&qusb2phy {
>> +	status = "okay";
>> +
>> +	vdd-supply = <&vreg_l1b_0p925>;
>> +	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
>> +};
>> +
>> +&qusb2phy1 {
>> +	status = "okay";
>> +
>> +	vdd-supply = <&vreg_l1b_0p925>;
>> +	vdda-phy-dpdm-supply = <&vreg_l7b_3p125>;
>> +};
>> +
>> +&rpm_requests {
>> +	pm660-regulators {
>> +		compatible = "qcom,rpm-pm660-regulators";
>> +
>> +		vdd_s1-supply = <&vph_pwr>;
>> +		vdd_s2-supply = <&vph_pwr>;
>> +		vdd_s3-supply = <&vph_pwr>;
>> +		vdd_s4-supply = <&vph_pwr>;
>> +		vdd_s5-supply = <&vph_pwr>;
>> +		vdd_s6-supply = <&vph_pwr>;
>> +
>> +		vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>;
>> +		vdd_l2_l3-supply = <&vreg_s2b_1p05>;
>> +		vdd_l5-supply = <&vreg_s2b_1p05>;
>> +		vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>;
>> +		vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>;
>> +
>> +		vreg_s4a_2p04: s4 {
>> +			regulator-min-microvolt = <1805000>;
>> +			regulator-max-microvolt = <2040000>;
>> +			regulator-enable-ramp-delay = <200>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-always-on;
>> +		};
>> +
>> +		vreg_s5a_1p35: s5 {
>> +			regulator-min-microvolt = <1224000>;
>> +			regulator-max-microvolt = <1350000>;
>> +			regulator-enable-ramp-delay = <200>;
>> +			regulator-ramp-delay = <0>;
>> +		};
>> +
>> +		vreg_l1a_1p225: l1 {
>> +			regulator-min-microvolt = <1150000>;
>> +			regulator-max-microvolt = <1250000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l6a_1p3: l6 {
>> +			regulator-min-microvolt = <1304000>;
>> +			regulator-max-microvolt = <1368000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l8a_1p8: l8 {
>> +			regulator-min-microvolt = <1800000>;
>> +			regulator-max-microvolt = <1800000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-system-load = <325000>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l9a_1p8: l9 {
>> +			regulator-min-microvolt = <1804000>;
>> +			regulator-max-microvolt = <1896000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l13a_1p8: l13 {
>> +			/* This gives power to the LPDDR4: never turn it off! */
>> +			regulator-min-microvolt = <1800000>;
>> +			regulator-max-microvolt = <1944000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-always-on;
>> +			regulator-boot-on;
>> +		};
>> +
>> +		vreg_l19a_3p3: l19 {
>> +			regulator-min-microvolt = <3312000>;
>> +			regulator-max-microvolt = <3400000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-allow-set-load;
>> +		};
>> +	};
>> +
>> +	pm660l-regulators {
>> +		compatible = "qcom,rpm-pm660l-regulators";
>> +
>> +		vdd_s1-supply = <&vph_pwr>;
>> +		vdd_s2-supply = <&vph_pwr>;
>> +		vdd_s3_s4-supply = <&vph_pwr>;
>> +		vdd_s5-supply = <&vph_pwr>;
>> +		vdd_s6-supply = <&vph_pwr>;
>> +
>> +		vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>;
>> +		vdd_l2-supply = <&vreg_bob>;
>> +		vdd_l3_l5_l7_l8-supply = <&vreg_bob>;
>> +		vdd_l4_l6-supply = <&vreg_bob>;
>> +		vdd_bob-supply = <&vph_pwr>;
>> +
>> +		vreg_s2b_1p05: s2 {
>> +			regulator-min-microvolt = <1050000>;
>> +			regulator-max-microvolt = <1050000>;
>> +			regulator-enable-ramp-delay = <200>;
>> +			regulator-ramp-delay = <0>;
>> +		};
>> +
>> +		vreg_l1b_0p925: l1 {
>> +			regulator-min-microvolt = <800000>;
>> +			regulator-max-microvolt = <925000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l2b_2p95: l2 {
>> +			regulator-min-microvolt = <1648000>;
>> +			regulator-max-microvolt = <3100000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l4b_2p95: l4 {
>> +			regulator-min-microvolt = <2944000>;
>> +			regulator-max-microvolt = <2952000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +
>> +			regulator-min-microamp = <200>;
>> +			regulator-max-microamp = <600000>;
>> +			regulator-system-load = <570000>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		/*
>> +		 * Downstream specifies a range of 1721-3600mV,
>> +		 * but the only assigned consumers are SDHCI2 VMMC
>> +		 * and Coresight QPDI that both request pinned 2.95V.
>> +		 * Tighten the range to 1.8-3.328 (closest to 3.3) to
>> +		 * make the mmc driver happy.
>> +		 */
>> +		vreg_l5b_2p95: l5 {
>> +			regulator-min-microvolt = <1800000>;
>> +			regulator-max-microvolt = <3328000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-system-load = <800000>;
>> +			regulator-ramp-delay = <0>;
>> +			regulator-allow-set-load;
>> +		};
>> +
>> +		vreg_l7b_3p125: l7 {
>> +			regulator-min-microvolt = <2700000>;
>> +			regulator-max-microvolt = <3125000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +		};
>> +
>> +		vreg_l8b_3p3: l8 {
>> +			regulator-min-microvolt = <2800000>;
>> +			regulator-max-microvolt = <3400000>;
>> +			regulator-enable-ramp-delay = <250>;
>> +			regulator-ramp-delay = <0>;
>> +		};
>> +
>> +		vreg_bob: bob {
>> +			regulator-min-microvolt = <3300000>;
>> +			regulator-max-microvolt = <3624000>;
>> +			regulator-enable-ramp-delay = <500>;
>> +			regulator-ramp-delay = <0>;
>> +		};
>> +	};
>> +};
>> +
>> +&sdhc_1 {
>> +	status = "okay";
>> +	supports-cqe;
>> +
>> +	vmmc-supply = <&vreg_l4b_2p95>;
>> +	vqmmc-supply = <&vreg_l8a_1p8>;
>> +
>> +	mmc-ddr-1_8v;
>> +	mmc-hs400-1_8v;
>> +	mmc-hs400-enhanced-strobe;
>> +};
>> +
>> +&sdhc_2 {
>> +	status = "okay";
>> +
>> +	pinctrl-names = "default";
> 
> Missing , "sleep".
> 
>> +	pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>;
>> +	pinctrl1 = <&sdc2_state_off &sdc2_card_det_n>;
> 
> Missing hyphen.

Thanks.

> 
>> +
>> +	vmmc-supply = <&vreg_l5b_2p95>;
>> +	vqmmc-supply = <&vreg_l2b_2p95>;
>> +
>> +	cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
>> +	no-sdio;
>> +	no-emmc;
>> +};
>> +
>> +&tlmm {
>> +	gpio-reserved-ranges = <0 4>, <8 4>;
>> +
>> +	sdc2_card_det_n: sd-card-det-n {
>> +		pins = "gpio54";
>> +		function = "gpio";
>> +		bias-pull-up;
>> +	};
> 
> It seems this pin is also already declared in sdc2-on/off in
> sdm630.dtsi, with the same bias-pull-up in the -on case.  However, the
> -off case sets bias-disable, won't that conflict?  (not in this moment,
> because the clashing pinctrl pairs are "unused" with the typos above).

Ugh. Yes, there should be just one of them

> 
> I have always been under the impression this GPIO is board-specific and
> should be moved out of sdm630.dtsi into board-specific DTs, is that
> true?

Yes, it is true. That's why I didn't expect that it is already defined.
Also the bias and the drive-strength are also expected to go to the 
board files. Let me take a glance and fix that.

> 
> - Marijn
> 
>> +};
>> +
>> +&usb2 {
>> +	status = "okay";
>> +};
>> +
>> +&usb2_dwc3 {
>> +	dr_mode = "host";
>> +};
>> +
>> +&usb3 {
>> +	status = "okay";
>> +};
>> +
>> +&usb3_dwc3 {
>> +	dr_mode = "peripheral";
>> +	extcon = <&extcon_usb>;
>> +};
>> -- 
>> 2.35.1
>>


-- 
With best wishes
Dmitry

Re: [PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects

[Marijn Suijten]

On 2022-05-14 15:51:55, Dmitry Baryshkov wrote:
> On Sat, 14 May 2022 at 12:45, Marijn Suijten
> <marijn.suijten@somainline.org> wrote:
> >
> > On 2022-05-14 02:45:16, Dmitry Baryshkov wrote:
> > > Replace numeric values with the symbolic names defined in the bindings
> > > header.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > Seems there is one off-by-one copy-paste error.  With that addressed:
> >
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> >
> > > ---
> > >  arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++-----------
> > >  1 file changed, 12 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > index 17a1877587cf..01a1a1703568 100644
> > > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > @@ -8,6 +8,7 @@
> > >  #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
> > >  #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
> > >  #include <dt-bindings/clock/qcom,rpmcc.h>
> > > +#include <dt-bindings/interconnect/qcom,sdm660.h>
> > >  #include <dt-bindings/power/qcom-rpmpd.h>
> > >  #include <dt-bindings/gpio/gpio.h>
> > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 {
> > >                       nvmem-cells = <&gpu_speed_bin>;
> > >                       nvmem-cell-names = "speed_bin";
> > >
> > > -                     interconnects = <&gnoc 1 &bimc 5>;
> > > +                     interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>;
> >
> > From qcom,sdm660.h:
> >
> >     /* GNOC */
> >     #define MASTER_APSS_PROC            0
> >     #define SLAVE_GNOC_BIMC                     1
> >     #define SLAVE_GNOC_SNOC                     2
> >
> > Seems like the left side should be SLAVE_GNOC_BIMC?  Unless this
> > semantic change is intended, in which case it should be clearly
> > documented in its own commit with a Fixes tag.
> 
> I don't think there can be a slave on the left side of the ICC path.
> But nice catch anyway. Downstream uses MSM_BUS_MASTER_GRAPHICS_3D
> here, which corresponds to <&bimc MASTER_OXILI>.
> Could you please double check this?

Agreed, my downstream source for this device also uses
MSM_BUS_MASTER_GRAPHICS_3D=26 with mas_rpm_id=ICBID_MASTER_GFX3D=6, and 
on the right-side MSM_BUS_SLAVE_EBI_CH0=512 which resolves to
slv_rpm_id=ICBID_SLAVE_EBI1=0.  Both on &bimc.

Have you double-checked all the other interconnect paths in this file?

- Marijn

> >
> > The rest looks correct.
> >
> > - Marijn
> [..]

Re: [PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects

[Dmitry Baryshkov]

On Sun, 15 May 2022 at 17:44, Marijn Suijten
<marijn.suijten@somainline.org> wrote:
>
> On 2022-05-14 15:51:55, Dmitry Baryshkov wrote:
> > On Sat, 14 May 2022 at 12:45, Marijn Suijten
> > <marijn.suijten@somainline.org> wrote:
> > >
> > > On 2022-05-14 02:45:16, Dmitry Baryshkov wrote:
> > > > Replace numeric values with the symbolic names defined in the bindings
> > > > header.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > >
> > > Seems there is one off-by-one copy-paste error.  With that addressed:
> > >
> > > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> > >
> > > > ---
> > > >  arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++-----------
> > > >  1 file changed, 12 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > > index 17a1877587cf..01a1a1703568 100644
> > > > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
> > > > @@ -8,6 +8,7 @@
> > > >  #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
> > > >  #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
> > > >  #include <dt-bindings/clock/qcom,rpmcc.h>
> > > > +#include <dt-bindings/interconnect/qcom,sdm660.h>
> > > >  #include <dt-bindings/power/qcom-rpmpd.h>
> > > >  #include <dt-bindings/gpio/gpio.h>
> > > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 {
> > > >                       nvmem-cells = <&gpu_speed_bin>;
> > > >                       nvmem-cell-names = "speed_bin";
> > > >
> > > > -                     interconnects = <&gnoc 1 &bimc 5>;
> > > > +                     interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>;
> > >
> > > From qcom,sdm660.h:
> > >
> > >     /* GNOC */
> > >     #define MASTER_APSS_PROC            0
> > >     #define SLAVE_GNOC_BIMC                     1
> > >     #define SLAVE_GNOC_SNOC                     2
> > >
> > > Seems like the left side should be SLAVE_GNOC_BIMC?  Unless this
> > > semantic change is intended, in which case it should be clearly
> > > documented in its own commit with a Fixes tag.
> >
> > I don't think there can be a slave on the left side of the ICC path.
> > But nice catch anyway. Downstream uses MSM_BUS_MASTER_GRAPHICS_3D
> > here, which corresponds to <&bimc MASTER_OXILI>.
> > Could you please double check this?
>
> Agreed, my downstream source for this device also uses
> MSM_BUS_MASTER_GRAPHICS_3D=26 with mas_rpm_id=ICBID_MASTER_GFX3D=6, and
> on the right-side MSM_BUS_SLAVE_EBI_CH0=512 which resolves to
> slv_rpm_id=ICBID_SLAVE_EBI1=0.  Both on &bimc.
>
> Have you double-checked all the other interconnect paths in this file?

Hmmmmm.

SDHCs also seem to be incorrect. For sdhc_1 downstream uses
<MSM_BUS_MASTER_SDCC_1 MSM_BUS_SLAVE_EBI_CH0>,
<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_SDCC_1>.
For the upstream kernel this translates to <&a2noc MASTER_SDCC_1 &bimc
SLAVE_EBI>, <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1> (while we have
<&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>, <&gnoc
MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>). Same applies for the sdhc2.

AngeloGioacchino, since SDHC interconnects were added by you, could
you please check?

For camss I suppose that downstream uses MASTER_CPP rather than
MASTER_VFE. If I'm not mistaken.

For venus the downstream path is equivalent <&mnoc MASTER_VENUS &bimc
SLAVE_EBI> (which we have here). vidc describes <&gnoc
MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>. So venus cfg looks correct.

>
> - Marijn
>
> > >
> > > The rest looks correct.
> > >
> > > - Marijn
> > [..]



-- 
With best wishes
Dmitry