[PATCH v2 0/6] arm64: dts: qcom: Fix 'sdhci' nodes for 'make dtbs_check'

[PATCH v2 0/6] arm64: dts: qcom: Fix 'sdhci' nodes for 'make dtbs_check'

[Bhupesh Sharma]

Changes since v1:
----------------
- v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20220429214420.854335-1-bhupesh.sharma@linaro.org/
- Fixed Bjorn's comments received on v1.
- Added 3 more dts fix-up patches [PATCH 1/6], [PATCH 5/6]
  and [PATCH 6/6] in v2.

Since the change to convert the Qualcomm 'sdhci-msm' device-tree binding
to yaml format has been accepted in linux-next and a fix for the same
was sent as per Rob's review comments, 'make dtbs_check' now
reports several issues with sdhci nodes used across qcom dts files.

This patchset fixes the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>

Bhupesh Sharma (6):
  arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
  arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes
  arm64: dts: qcom: Fix node names for sdhci 'opp-table' nodes (across
    dts files)
  arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci
    nodes
  arm64: dts: qcom: Fix 'reg-names' for sdhci nodes
  arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

 arch/arm/boot/dts/qcom-apq8084.dtsi   |  4 ++--
 arch/arm/boot/dts/qcom-ipq4019.dtsi   |  2 +-
 arch/arm/boot/dts/qcom-msm8226.dtsi   |  6 +++---
 arch/arm/boot/dts/qcom-msm8974.dtsi   |  6 +++---
 arch/arm/boot/dts/qcom-sdx55.dtsi     |  2 +-
 arch/arm/boot/dts/qcom-sdx65.dtsi     |  2 +-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++------
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 16 ++++++++--------
 arch/arm64/boot/dts/qcom/msm8953.dtsi |  4 ++--
 arch/arm64/boot/dts/qcom/msm8994.dtsi | 18 +++++++++---------
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  4 ++--
 arch/arm64/boot/dts/qcom/msm8998.dtsi |  2 +-
 arch/arm64/boot/dts/qcom/qcs404.dtsi  | 10 +++++-----
 arch/arm64/boot/dts/qcom/sc7180.dtsi  | 22 +++++++++++-----------
 arch/arm64/boot/dts/qcom/sc7280.dtsi  | 18 +++++++++---------
 arch/arm64/boot/dts/qcom/sdm630.dtsi  | 25 ++++++++++++++-----------
 arch/arm64/boot/dts/qcom/sdm845.dtsi  |  2 +-
 arch/arm64/boot/dts/qcom/sm6125.dtsi  |  8 ++++----
 arch/arm64/boot/dts/qcom/sm6350.dtsi  | 10 +++++-----
 arch/arm64/boot/dts/qcom/sm8150.dtsi  |  4 ++--
 arch/arm64/boot/dts/qcom/sm8250.dtsi  |  4 ++--
 21 files changed, 92 insertions(+), 89 deletions(-)

-- 
2.35.3

[PATCH v2 1/6] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8084.dtsi   | 4 ++--
 arch/arm/boot/dts/qcom-ipq4019.dtsi   | 2 +-
 arch/arm/boot/dts/qcom-msm8226.dtsi   | 6 +++---
 arch/arm/boot/dts/qcom-msm8974.dtsi   | 6 +++---
 arch/arm/boot/dts/qcom-sdx55.dtsi     | 2 +-
 arch/arm/boot/dts/qcom-sdx65.dtsi     | 2 +-
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/qcs404.dtsi  | 2 +-
 arch/arm64/boot/dts/qcom/sc7180.dtsi  | 4 ++--
 arch/arm64/boot/dts/qcom/sc7280.dtsi  | 4 ++--
 arch/arm64/boot/dts/qcom/sdm630.dtsi  | 4 ++--
 arch/arm64/boot/dts/qcom/sdm845.dtsi  | 2 +-
 arch/arm64/boot/dts/qcom/sm6125.dtsi  | 4 ++--
 arch/arm64/boot/dts/qcom/sm6350.dtsi  | 4 ++--
 arch/arm64/boot/dts/qcom/sm8150.dtsi  | 2 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi  | 2 +-
 21 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index da50a1a0197f..ca630ca2d9cd 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -419,7 +419,7 @@ blsp2_uart2: serial@f995e000 {
 			status = "disabled";
 		};
 
-		sdhci@f9824900 {
+		mmc@f9824900 {
 			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -432,7 +432,7 @@ sdhci@f9824900 {
 			status = "disabled";
 		};
 
-		sdhci@f98a4900 {
+		mmc@f98a4900 {
 			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index c5da723f7674..a2632349cec4 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -221,7 +221,7 @@ vqmmc: regulator@1948000 {
 			status = "disabled";
 		};
 
-		sdhci: sdhci@7824900 {
+		sdhci: mmc@7824900 {
 			compatible = "qcom,sdhci-msm-v4";
 			reg = <0x7824900 0x11c>, <0x7824000 0x800>;
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 28eca15b5712..0b5effdb269a 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -134,7 +134,7 @@ apcs: syscon@f9011000 {
 			reg = <0xf9011000 0x1000>;
 		};
 
-		sdhc_1: sdhci@f9824900 {
+		sdhc_1: mmc@f9824900 {
 			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -150,7 +150,7 @@ sdhc_1: sdhci@f9824900 {
 			status = "disabled";
 		};
 
-		sdhc_2: sdhci@f98a4900 {
+		sdhc_2: mmc@f98a4900 {
 			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -166,7 +166,7 @@ sdhc_2: sdhci@f98a4900 {
 			status = "disabled";
 		};
 
-		sdhc_3: sdhci@f9864900 {
+		sdhc_3: mmc@f9864900 {
 			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 814ad0b46232..637877e5c5d8 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -436,7 +436,7 @@ acc3: clock-controller@f90b8000 {
 			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 		};
 
-		sdhc_1: sdhci@f9824900 {
+		sdhc_1: mmc@f9824900 {
 			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -453,7 +453,7 @@ sdhc_1: sdhci@f9824900 {
 			status = "disabled";
 		};
 
-		sdhc_3: sdhci@f9864900 {
+		sdhc_3: mmc@f9864900 {
 			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -472,7 +472,7 @@ sdhc_3: sdhci@f9864900 {
 			status = "disabled";
 		};
 
-		sdhc_2: sdhci@f98a4900 {
+		sdhc_2: mmc@f98a4900 {
 			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 1c2b208a5670..4c76c7758637 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -388,7 +388,7 @@ tcsr: syscon@1fcb000 {
 			reg = <0x01fc0000 0x1000>;
 		};
 
-		sdhc_1: sdhci@8804000 {
+		sdhc_1: mmc@8804000 {
 			compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x08804000 0x1000>;
 			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index df6f9d6288fe..5b8e8620a1e1 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -143,7 +143,7 @@ tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
-		sdhc_1: sdhci@8804000 {
+		sdhc_1: mmc@8804000 {
 			compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x08804000 0x1000>;
 			reg-names = "hc_mem";
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 4c38b15c6fd4..9dff30c8fc85 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -375,7 +375,7 @@ spmi_bus: spmi@200f000 {
 			cell-index = <0>;
 		};
 
-		sdhc_1: sdhci@7824900 {
+		sdhc_1: mmc@7824900 {
 			compatible = "qcom,sdhci-msm-v4";
 			reg = <0x7824900 0x500>, <0x7824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 05472510e29d..aadefb38a7cf 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1464,7 +1464,7 @@ lpass_codec: audio-codec@771c000 {
 			#sound-dai-cells = <1>;
 		};
 
-		sdhc_1: sdhci@7824000 {
+		sdhc_1: mmc@7824000 {
 			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -1482,7 +1482,7 @@ sdhc_1: sdhci@7824000 {
 			status = "disabled";
 		};
 
-		sdhc_2: sdhci@7864000 {
+		sdhc_2: mmc@7864000 {
 			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index ffc3ec2cd3bc..1bc0ef476cdb 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -795,7 +795,7 @@ usb3_dwc3: usb@7000000 {
 			};
 		};
 
-		sdhc_1: sdhci@7824900 {
+		sdhc_1: mmc@7824900 {
 			compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
 
 			reg = <0x7824900 0x500>, <0x7824000 0x800>;
@@ -855,7 +855,7 @@ opp-384000000 {
 			};
 		};
 
-		sdhc_2: sdhci@7864900 {
+		sdhc_2: mmc@7864900 {
 			compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
 
 			reg = <0x7864900 0x500>, <0x7864000 0x800>;
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 0318d42c5736..99230e8d643f 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -461,7 +461,7 @@ usb@f9200000 {
 			};
 		};
 
-		sdhc1: sdhci@f9824900 {
+		sdhc1: mmc@f9824900 {
 			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -484,7 +484,7 @@ sdhc1: sdhci@f9824900 {
 			status = "disabled";
 		};
 
-		sdhc2: sdhci@f98a4900 {
+		sdhc2: mmc@f98a4900 {
 			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 9932186f7ceb..e6fa71f14240 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2804,7 +2804,7 @@ hsusb_phy2: phy@7412000 {
 			status = "disabled";
 		};
 
-		sdhc1: sdhci@7464900 {
+		sdhc1: mmc@7464900 {
 			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0x07464900 0x11c>, <0x07464000 0x800>;
 			reg-names = "hc_mem", "core_mem";
@@ -2827,7 +2827,7 @@ sdhc1: sdhci@7464900 {
 			status = "disabled";
 		};
 
-		sdhc2: sdhci@74a4900 {
+		sdhc2: mmc@74a4900 {
 			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
 			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 758c45bbbe78..a49a13441661 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2102,7 +2102,7 @@ qusb2phy: phy@c012000 {
 			nvmem-cells = <&qusb2_hstx_trim>;
 		};
 
-		sdhc2: sdhci@c0a4900 {
+		sdhc2: mmc@c0a4900 {
 			compatible = "qcom,sdhci-msm-v4";
 			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
 			reg-names = "hc_mem", "core_mem";
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index d912166b7552..97c4e6c6f6c8 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -789,7 +789,7 @@ pcie_phy: phy@7786000 {
 			status = "disabled";
 		};
 
-		sdcc1: sdcc@7804000 {
+		sdcc1: mmc@7804000 {
 			compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
 			reg-names = "hc", "cqhci";
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 5dcaac23a138..4a316c50484d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -693,7 +693,7 @@ gpu_speed_bin: gpu_speed_bin@1d2 {
 			};
 		};
 
-		sdhc_1: sdhci@7c4000 {
+		sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x7c4000 0 0x1000>,
 				<0 0x07c5000 0 0x1000>;
@@ -2578,7 +2578,7 @@ apss_merge_funnel_in: endpoint {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..f1e86effa063 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -857,7 +857,7 @@ gpu_speed_bin: gpu_speed_bin@1e9 {
 			};
 		};
 
-		sdhc_1: sdhci@7c4000 {
+		sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
@@ -2936,7 +2936,7 @@ apss_merge_funnel_in: endpoint {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index b72e8e6c52f3..cadc920bcd9c 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1272,7 +1272,7 @@ qusb2phy: phy@c012000 {
 			status = "disabled";
 		};
 
-		sdhc_2: sdhci@c084000 {
+		sdhc_2: mmc@c084000 {
 			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0c084000 0x1000>;
 			reg-names = "hc";
@@ -1322,7 +1322,7 @@ opp-200000000 {
 			};
 		};
 
-		sdhc_1: sdhci@c0c4000 {
+		sdhc_1: mmc@c0c4000 {
 			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0c0c4000 0x1000>,
 			      <0x0c0c5000 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0692ae0e60a4..85baec57b993 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3551,7 +3551,7 @@ apss_merge_funnel_in: endpoint {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 135e6e0da27a..77bff81af433 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -435,7 +435,7 @@ rpm_msg_ram: sram@45f0000 {
 			reg = <0x045f0000 0x7000>;
 		};
 
-		sdhc_1: sdhci@4744000 {
+		sdhc_1: mmc@4744000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
 			reg-names = "hc", "core";
@@ -456,7 +456,7 @@ sdhc_1: sdhci@4744000 {
 			status = "disabled";
 		};
 
-		sdhc_2: sdhci@4784000 {
+		sdhc_2: mmc@4784000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04784000 0x1000>;
 			reg-names = "hc";
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index d4f8f33f3f0c..13c7ae2e379e 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -472,7 +472,7 @@ rng: rng@793000 {
 			clock-names = "core";
 		};
 
-		sdhc_1: sdhci@7c4000 {
+		sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x007c4000 0 0x1000>,
 				<0 0x007c5000 0 0x1000>,
@@ -921,7 +921,7 @@ compute-cb@8 {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 8ea44c4b56b4..a2a1c77c0428 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3543,7 +3543,7 @@ usb_2_ssphy: phy@88eb200 {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index cf0c97bd5ad3..6c06e3b2ad2d 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2917,7 +2917,7 @@ usb_2_ssphy: phy@88eb200 {
 			};
 		};
 
-		sdhc_2: sdhci@8804000 {
+		sdhc_2: mmc@8804000 {
 			compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
 
-- 
2.35.3

[PATCH v2 2/6] arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'interconnect-names' used for sdhci nodes.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index cadc920bcd9c..34b177f0ce87 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1289,6 +1289,7 @@ sdhc_2: mmc@c084000 {
 
 			interconnects = <&a2noc 3 &a2noc 10>,
 					<&gnoc 0 &cnoc 28>;
+			interconnect-names = "sdhc-ddr","cpu-sdhc";
 			operating-points-v2 = <&sdhc2_opp_table>;
 
 			pinctrl-names = "default", "sleep";
@@ -1341,7 +1342,7 @@ sdhc_1: mmc@c0c4000 {
 
 			interconnects = <&a2noc 2 &a2noc 10>,
 					<&gnoc 0 &cnoc 27>;
-			interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
 			operating-points-v2 = <&sdhc1_opp_table>;
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&sdc1_state_on>;
-- 
2.35.3

[PATCH v2 3/6] arm64: dts: qcom: Fix node names for sdhci 'opp-table' nodes (across dts files)

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
node names for sdhci 'opp-table' nodes, as it doesn't seem to like
any 'preceding text or numbers' before 'opp-table' pattern in the
node names.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 4a316c50484d..df0006d4a560 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -725,7 +725,7 @@ sdhc_1: mmc@7c4000 {
 
 			status = "disabled";
 
-			sdhc1_opp_table: sdhc1-opp-table {
+			sdhc1_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-100000000 {
@@ -2602,7 +2602,7 @@ sdhc_2: mmc@8804000 {
 
 			status = "disabled";
 
-			sdhc2_opp_table: sdhc2-opp-table {
+			sdhc2_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-100000000 {
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 13c7ae2e379e..1b1eb884136b 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -497,7 +497,7 @@ sdhc_1: mmc@7c4000 {
 
 			status = "disabled";
 
-			sdhc1_opp_table: sdhc1-opp-table {
+			sdhc1_opp_table: opp-table-sdhc1 {
 				compatible = "operating-points-v2";
 
 				opp-19200000 {
@@ -941,7 +941,7 @@ sdhc_2: mmc@8804000 {
 
 			status = "disabled";
 
-			sdhc2_opp_table: sdhc2-opp-table {
+			sdhc2_opp_table: opp-table-sdhc2 {
 				compatible = "operating-points-v2";
 
 				opp-100000000 {
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index a2a1c77c0428..e6b309e9c05b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3563,7 +3563,7 @@ sdhc_2: mmc@8804000 {
 
 			status = "disabled";
 
-			sdhc2_opp_table: sdhc2-opp-table {
+			sdhc2_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-19200000 {
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 6c06e3b2ad2d..9b6dea34cd69 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2937,7 +2937,7 @@ sdhc_2: mmc@8804000 {
 
 			status = "disabled";
 
-			sdhc2_opp_table: sdhc2-opp-table {
+			sdhc2_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-19200000 {
-- 
2.35.3

[PATCH v2 4/6] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'clocks' & 'clock-names' for sdhci nodes:

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:0: 'iface' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:1: 'core' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:2: 'xo' was expected

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi |  8 ++++----
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 ++++++------
 arch/arm64/boot/dts/qcom/msm8994.dtsi | 14 +++++++-------
 arch/arm64/boot/dts/qcom/qcs404.dtsi  |  6 +++---
 arch/arm64/boot/dts/qcom/sc7180.dtsi  | 12 ++++++------
 arch/arm64/boot/dts/qcom/sc7280.dtsi  | 12 ++++++------
 arch/arm64/boot/dts/qcom/sdm630.dtsi  | 14 ++++++++------
 7 files changed, 40 insertions(+), 38 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 9dff30c8fc85..ab2a1e7955b5 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -384,10 +384,10 @@ sdhc_1: mmc@7824900 {
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&xo>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
-				 <&gcc GCC_SDCC1_APPS_CLK>;
-			clock-names = "xo", "iface", "core";
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo>;
+			clock-names = "iface", "core", "xo";
 			max-frequency = <384000000>;
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index aadefb38a7cf..9cd7c625d331 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1472,10 +1472,10 @@ sdhc_1: mmc@7824000 {
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 			mmc-ddr-1_8v;
 			bus-width = <8>;
 			non-removable;
@@ -1490,10 +1490,10 @@ sdhc_2: mmc@7864000 {
 			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
-			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-				 <&gcc GCC_SDCC2_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
 				 <&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 			bus-width = <4>;
 			status = "disabled";
 		};
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 99230e8d643f..362960d3fd18 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -470,10 +470,10 @@ sdhc1: mmc@f9824900 {
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-			         <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
@@ -493,10 +493,10 @@ sdhc2: mmc@f98a4900 {
 				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-				<&gcc GCC_SDCC2_AHB_CLK>,
-				<&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
 
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 97c4e6c6f6c8..86dbf8ea04bc 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -798,10 +798,10 @@ sdcc1: mmc@7804000 {
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 
 			status = "disabled";
 		};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index df0006d4a560..9076892ff4f8 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -704,10 +704,10 @@ sdhc_1: mmc@7c4000 {
 					<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -2587,10 +2587,10 @@ sdhc_2: mmc@8804000 {
 					<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-				 <&gcc GCC_SDCC2_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 
 			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f1e86effa063..e63d1a4499f8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -873,10 +873,10 @@ sdhc_1: mmc@7c4000 {
 				     <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 			interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -2950,10 +2950,10 @@ sdhc_2: mmc@8804000 {
 				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-				 <&gcc GCC_SDCC2_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
 			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 34b177f0ce87..6d872e2f400a 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1282,10 +1282,12 @@ sdhc_2: mmc@c084000 {
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			bus-width = <4>;
-			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-					<&gcc GCC_SDCC2_AHB_CLK>,
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+					<&gcc GCC_SDCC2_APPS_CLK>,
 					<&xo_board>;
-			clock-names = "core", "iface", "xo";
+			clock-names = "iface", "core", "xo";
+
 
 			interconnects = <&a2noc 3 &a2noc 10>,
 					<&gnoc 0 &cnoc 28>;
@@ -1334,11 +1336,11 @@ sdhc_1: mmc@c0c4000 {
 					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "hc_irq", "pwr_irq";
 
-			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-				 <&gcc GCC_SDCC1_AHB_CLK>,
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo_board>,
 				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
-			clock-names = "core", "iface", "xo", "ice";
+			clock-names = "iface", "core", "xo", "ice";
 
 			interconnects = <&a2noc 2 &a2noc 10>,
 					<&gnoc 0 &cnoc 27>;
-- 
2.35.3

[PATCH v2 5/6] arm64: dts: qcom: Fix 'reg-names' for sdhci nodes

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'reg-names' as various possible combinations
are possible for different qcom SoC dts files.

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 86dbf8ea04bc..45044083faf0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -792,7 +792,7 @@ pcie_phy: phy@7786000 {
 		sdcc1: mmc@7804000 {
 			compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 9076892ff4f8..08f2decc7f4f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -697,7 +697,7 @@ sdhc_1: mmc@7c4000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x7c4000 0 0x1000>,
 				<0 0x07c5000 0 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			iommus = <&apps_smmu 0x60 0x0>;
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e63d1a4499f8..eaaccf0184af 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -866,7 +866,7 @@ sdhc_1: mmc@7c4000 {
 
 			reg = <0 0x007c4000 0 0x1000>,
 			      <0 0x007c5000 0 0x1000>;
-			reg-names = "hc", "cqhci";
+			reg-names = "hc_mem", "cqe_mem";
 
 			iommus = <&apps_smmu 0xc0 0x0>;
 			interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 6d872e2f400a..77dc985b3634 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -1275,7 +1275,7 @@ qusb2phy: phy@c012000 {
 		sdhc_2: mmc@c084000 {
 			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x0c084000 0x1000>;
-			reg-names = "hc";
+			reg-names = "hc_mem";
 
 			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -1330,7 +1330,7 @@ sdhc_1: mmc@c0c4000 {
 			reg = <0x0c0c4000 0x1000>,
 			      <0x0c0c5000 0x1000>,
 			      <0x0c0c8000 0x8000>;
-			reg-names = "hc", "cqhci", "ice";
+			reg-names = "hc_mem", "cqe_mem", "ice_mem";
 
 			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 77bff81af433..94e427abbfd2 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 {
 		sdhc_1: mmc@4744000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
-			reg-names = "hc", "core";
+			reg-names = "hc_mem", "core_mem";
 
 			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +459,7 @@ sdhc_1: mmc@4744000 {
 		sdhc_2: mmc@4784000 {
 			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0x04784000 0x1000>;
-			reg-names = "hc";
+			reg-names = "hc_mem";
 
 			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 1b1eb884136b..6d959aa0ea94 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -477,7 +477,7 @@ sdhc_1: mmc@7c4000 {
 			reg = <0 0x007c4000 0 0x1000>,
 				<0 0x007c5000 0 0x1000>,
 				<0 0x007c8000 0 0x8000>;
-			reg-names = "hc", "cqhci", "ice";
+			reg-names = "hc_mem", "cqe_mem", "ice_mem";
 
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.35.3

[PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

[Bhupesh Sharma]

Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
'max-frequency' value for ipq8074 sdhci node:

 arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
  max-frequency:0:0: 384000000 is greater than the maximum of 200000000

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index ab2a1e7955b5..b2d71af9b419 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 {
 				 <&gcc GCC_SDCC1_APPS_CLK>,
 				 <&xo>;
 			clock-names = "iface", "core", "xo";
-			max-frequency = <384000000>;
+			max-frequency = <200000000>;
 			mmc-ddr-1_8v;
 			mmc-hs200-1_8v;
 			mmc-hs400-1_8v;
-- 
2.35.3

Re: [PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

[Bjorn Andersson]

On Sat 14 May 16:54 CDT 2022, Bhupesh Sharma wrote:

> Since the Qualcomm sdhci-msm device-tree binding has been converted
> to yaml format, 'make dtbs_check' reports issues with
> 'max-frequency' value for ipq8074 sdhci node:
> 
>  arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
>   max-frequency:0:0: 384000000 is greater than the maximum of 200000000
> 
> Fix the same.
> 
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index ab2a1e7955b5..b2d71af9b419 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 {
>  				 <&gcc GCC_SDCC1_APPS_CLK>,
>  				 <&xo>;
>  			clock-names = "iface", "core", "xo";
> -			max-frequency = <384000000>;
> +			max-frequency = <200000000>;

This might match the binding, but someone put 384000000 there for a
reason. Perhaps the binding needs to be updated instead?

Regards,
Bjorn

>  			mmc-ddr-1_8v;
>  			mmc-hs200-1_8v;
>  			mmc-hs400-1_8v;
> -- 
> 2.35.3
> 

Re: (subset) [PATCH v2 0/6] arm64: dts: qcom: Fix 'sdhci' nodes for 'make dtbs_check'

[Bjorn Andersson]

On Sun, 15 May 2022 03:24:18 +0530, Bhupesh Sharma wrote:
> Changes since v1:
> ----------------
> - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20220429214420.854335-1-bhupesh.sharma@linaro.org/
> - Fixed Bjorn's comments received on v1.
> - Added 3 more dts fix-up patches [PATCH 1/6], [PATCH 5/6]
>   and [PATCH 6/6] in v2.
> 
> [...]

Applied, thanks!

[1/6] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
      commit: 2477d81901a23ad80045798edbeb7f91b5ff6143
[2/6] arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes
      commit: 40940823cb582acc13f5fda5688a5287893b3281
[3/6] arm64: dts: qcom: Fix node names for sdhci 'opp-table' nodes (across dts files)
      (no commit info)
[4/6] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes
      commit: 4ff12270dbbe245cf92c0247bcc1a2bfbc03639c
[5/6] arm64: dts: qcom: Fix 'reg-names' for sdhci nodes
      commit: afcbe252e9c19161e4d4c95f33faaf592f1de086

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>

Re: [PATCH v2 5/6] arm64: dts: qcom: Fix 'reg-names' for sdhci nodes

[Doug Anderson]

Hi,

On Sat, May 14, 2022 at 2:55 PM Bhupesh Sharma
<bhupesh.sharma@linaro.org> wrote:
>
> Since the Qualcomm sdhci-msm device-tree binding has been converted
> to yaml format, 'make dtbs_check' reports a number of issues with
> ordering of 'reg-names' as various possible combinations
> are possible for different qcom SoC dts files.
>
> Fix the same by updating the offending 'dts' files.
>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +-
>  arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
>  arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++--
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
>  6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 86dbf8ea04bc..45044083faf0 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -792,7 +792,7 @@ pcie_phy: phy@7786000 {
>                 sdcc1: mmc@7804000 {
>                         compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
>                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";
>
>                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 9076892ff4f8..08f2decc7f4f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -697,7 +697,7 @@ sdhc_1: mmc@7c4000 {
>                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
>                         reg = <0 0x7c4000 0 0x1000>,
>                                 <0 0x07c5000 0 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";
>
>                         iommus = <&apps_smmu 0x60 0x0>;
>                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e63d1a4499f8..eaaccf0184af 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -866,7 +866,7 @@ sdhc_1: mmc@7c4000 {
>
>                         reg = <0 0x007c4000 0 0x1000>,
>                               <0 0x007c5000 0 0x1000>;
> -                       reg-names = "hc", "cqhci";
> +                       reg-names = "hc_mem", "cqe_mem";

Yer breakin' mah build!

The second register here (and probably all boards) needs to be
"cqhci". See the line in the driver that looks like:

/* check and setup CMDQ interface */
cqhci_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
                                           "cqhci");

For history, see commit d3392339cae9 ("mmc: cqhci: Update cqhci memory
ioresource name") and commit d79100c91ae5 ("dt-bindings: mmc:
sdhci-msm: Add CQE reg map").

The problem here is not the device trees but the yaml. When you
convert from .txt to .yaml you're not allowed to just rewrite the
binding. It should also be noted that the "_mem" suffix was explicitly
requested to be removed.

Revert posted at:
https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid

Re: [PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

[Bhupesh Sharma]

On 7/1/22 4:24 AM, Bjorn Andersson wrote:
> On Sat 14 May 16:54 CDT 2022, Bhupesh Sharma wrote:
>
>> Since the Qualcomm sdhci-msm device-tree binding has been converted
>> to yaml format, 'make dtbs_check' reports issues with
>> 'max-frequency' value for ipq8074 sdhci node:
>>
>>   arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
>>    max-frequency:0:0: 384000000 is greater than the maximum of 200000000
>>
>> Fix the same.
>>
>> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index ab2a1e7955b5..b2d71af9b419 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 {
>>   				 <&gcc GCC_SDCC1_APPS_CLK>,
>>   				 <&xo>;
>>   			clock-names = "iface", "core", "xo";
>> -			max-frequency = <384000000>;
>> +			max-frequency = <200000000>;
> This might match the binding, but someone put 384000000 there for a
> reason. Perhaps the binding needs to be updated instead?

I was waiting for getting access to ipq8074 reference manual / documentation.
I double-checked and it seems SDCC1 on this SoC does support a max frequency
of 384 MHz which is strange as the SDCC2 supports 200 MHz as max frequency
instead.

Also the eMMC and MMC controllers on other SoCs (i.MX etx( usually support only
a max frequency of 200 MHz, so may be we need an exceptional addition to the
binding documentation here.

@Ulf - what's your view on updating the binding documentation here? I can
send a v3 accordingly.

Thanks,
Bhupesh

>>   			mmc-ddr-1_8v;
>>   			mmc-hs200-1_8v;
>>   			mmc-hs400-1_8v;
>> -- 
>> 2.35.3
>>

Re: [PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

[Ulf Hansson]

On Mon, 18 Jul 2022 at 10:47, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>
> On 7/1/22 4:24 AM, Bjorn Andersson wrote:
> > On Sat 14 May 16:54 CDT 2022, Bhupesh Sharma wrote:
> >
> >> Since the Qualcomm sdhci-msm device-tree binding has been converted
> >> to yaml format, 'make dtbs_check' reports issues with
> >> 'max-frequency' value for ipq8074 sdhci node:
> >>
> >>   arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
> >>    max-frequency:0:0: 384000000 is greater than the maximum of 200000000
> >>
> >> Fix the same.
> >>
> >> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> >> Cc: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> >> ---
> >>   arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> >> index ab2a1e7955b5..b2d71af9b419 100644
> >> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> >> @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 {
> >>                               <&gcc GCC_SDCC1_APPS_CLK>,
> >>                               <&xo>;
> >>                      clock-names = "iface", "core", "xo";
> >> -                    max-frequency = <384000000>;
> >> +                    max-frequency = <200000000>;
> > This might match the binding, but someone put 384000000 there for a
> > reason. Perhaps the binding needs to be updated instead?
>
> I was waiting for getting access to ipq8074 reference manual / documentation.
> I double-checked and it seems SDCC1 on this SoC does support a max frequency
> of 384 MHz which is strange as the SDCC2 supports 200 MHz as max frequency
> instead.

I guess it depends on what the property is being used for from the mmc
host driver perspective. So, to answer the question, we probably need
to look at the code in the host driver to best understand what to do
here.

>
> Also the eMMC and MMC controllers on other SoCs (i.MX etx( usually support only
> a max frequency of 200 MHz, so may be we need an exceptional addition to the
> binding documentation here.
>
> @Ulf - what's your view on updating the binding documentation here? I can
> send a v3 accordingly.

The point with the property is to let host controllers specify whether
there is an upper limit of the frequency that it can support. No
matter what, the mmc core will not use a frequency greater than stated
by the eMMC/SD/SDIO specs.

For eMMC, 200MHz is the maximum frequency.

For SD/SDIO cards, the SDR104 mode has 208MHz. So it seems like we
need an update to the binding, no matter what. :-)

I have no strong opinions around this, but perhaps just raising the
limit of the binding to cover the qcom case makes best sense.

Kind regards
Uffe

Re: [PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node

[Bhupesh Sharma]

Hi Ulf,


On 7/18/22 6:21 PM, Ulf Hansson wrote:
> On Mon, 18 Jul 2022 at 10:47, Bhupesh Sharma <bhupesh.sharma@linaro.org> wrote:
>>
>> On 7/1/22 4:24 AM, Bjorn Andersson wrote:
>>> On Sat 14 May 16:54 CDT 2022, Bhupesh Sharma wrote:
>>>
>>>> Since the Qualcomm sdhci-msm device-tree binding has been converted
>>>> to yaml format, 'make dtbs_check' reports issues with
>>>> 'max-frequency' value for ipq8074 sdhci node:
>>>>
>>>>    arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900:
>>>>     max-frequency:0:0: 384000000 is greater than the maximum of 200000000
>>>>
>>>> Fix the same.
>>>>
>>>> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
>>>> Cc: Rob Herring <robh@kernel.org>
>>>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>>>> index ab2a1e7955b5..b2d71af9b419 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>>>> @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 {
>>>>                                <&gcc GCC_SDCC1_APPS_CLK>,
>>>>                                <&xo>;
>>>>                       clock-names = "iface", "core", "xo";
>>>> -                    max-frequency = <384000000>;
>>>> +                    max-frequency = <200000000>;
>>> This might match the binding, but someone put 384000000 there for a
>>> reason. Perhaps the binding needs to be updated instead?
>>
>> I was waiting for getting access to ipq8074 reference manual / documentation.
>> I double-checked and it seems SDCC1 on this SoC does support a max frequency
>> of 384 MHz which is strange as the SDCC2 supports 200 MHz as max frequency
>> instead.
> 
> I guess it depends on what the property is being used for from the mmc
> host driver perspective. So, to answer the question, we probably need
> to look at the code in the host driver to best understand what to do
> here.
> 
>>
>> Also the eMMC and MMC controllers on other SoCs (i.MX etx( usually support only
>> a max frequency of 200 MHz, so may be we need an exceptional addition to the
>> binding documentation here.
>>
>> @Ulf - what's your view on updating the binding documentation here? I can
>> send a v3 accordingly.
> 
> The point with the property is to let host controllers specify whether
> there is an upper limit of the frequency that it can support. No
> matter what, the mmc core will not use a frequency greater than stated
> by the eMMC/SD/SDIO specs.
> 
> For eMMC, 200MHz is the maximum frequency.
> 
> For SD/SDIO cards, the SDR104 mode has 208MHz. So it seems like we
> need an update to the binding, no matter what. :-)
> 
> I have no strong opinions around this, but perhaps just raising the
> limit of the binding to cover the qcom case makes best sense.

Thanks for your inputs. I will send a v3 version with the udpated
binding soon.

Regards,
Bhupesh