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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default
Date: Tue, 17 May 2022 10:19:07 +0800	[thread overview]
Message-ID: <20220517021907.10060-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220517021907.10060-1-liweiwei@iscas.ac.cn>

 - properties for zb* extensions are enabled by default which will make sifive/ibex cpu types implicitly support zb* extensions

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b12f69c584..e205be34e9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -176,6 +176,10 @@ static void rv64_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv64_sifive_e_cpu_init(Object *obj)
@@ -184,6 +188,10 @@ static void rv64_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv128_base_cpu_init(Object *obj)
@@ -211,6 +219,10 @@ static void rv32_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_sifive_e_cpu_init(Object *obj)
@@ -219,6 +231,10 @@ static void rv32_sifive_e_cpu_init(Object *obj)
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_ibex_cpu_init(Object *obj)
@@ -228,6 +244,10 @@ static void rv32_ibex_cpu_init(Object *obj)
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
@@ -237,6 +257,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+    qdev_prop_set_bit(DEVICE(obj), "zba", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbb", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbc", false);
+    qdev_prop_set_bit(DEVICE(obj), "zbs", false);
 }
 #endif
 
-- 
2.17.1



  reply	other threads:[~2022-05-17  2:22 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-17  2:19 [PATCH v2 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
2022-05-17  2:19 ` Weiwei Li [this message]
2022-05-17  4:16   ` [PATCH v2 2/2] target/riscv: disable zb* extensions for sifive/ibex cpu types by default Alistair Francis
2022-05-17  4:49     ` Weiwei Li

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