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charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=129fa4c84=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The RISC-V CPUs have been incorrectly enabling features in the named vend= or CPUs that aren't enabled in hardware. This patchset changes this so that named vendor CPUs are not runtime configurable. I was torn for the best approach here. The other idea I had was to disabl= e features by default and instead enable them in CPUs. I ended up going this approach as I felt it made more sense to not expose configuration options for vendor CPUs, it just seems difficult to support now that we h= ave a large list of CPUs Alistair Francis (2): target/riscv: Don't expose the CPU properties on names CPUs target/riscv: Run extension checks for all CPUs target/riscv/cpu.c | 217 ++++++++++++++++++++++++++------------------- 1 file changed, 125 insertions(+), 92 deletions(-) --=20 2.35.1