From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEFD8C433EF for ; Tue, 17 May 2022 07:27:18 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 58D4783FC8; Tue, 17 May 2022 09:27:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="subPv5K8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4D936841B8; Tue, 17 May 2022 09:27:13 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EAC8483F2A for ; Tue, 17 May 2022 09:27:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CD96C60AC6; Tue, 17 May 2022 07:27:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 19B78C385B8; Tue, 17 May 2022 07:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652772427; bh=m8J9xIT3bbHch70q07ILCulJw5B1i5U9lp57ZQ/tphY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=subPv5K8UurvCYuHOV/lr1QyUaexX02ZTrmD4M8mSWi0D0dDBAtVwPYStZVrc8bGX 5IvwOH9FAjkr/si84EDmT1x2sL0L631R22QT2TFaq6pmouCVaan1/QKqqLnUn5Ufuq TTqIFGMHgD6SpEr5g2VEF6i7Li05Hw/FpJa9PvjPPGmygeHGW2yMxkvO7V5fqZtx47 UrzBVUslTWAhMjy+t/Xzn0Jc0ncHGCgi8oD/GOGjzUGcolD5Q/ebLLQkuJN0N5ABxe KHNniV1VmITNDuEKUNaIw0V9ldIKmgVCCFh0jgkX+P388NFbDmt/KcafUmcPrfFZW5 0PSt+qiHfqrGA== Received: by pali.im (Postfix) id 0DC047DA; Tue, 17 May 2022 09:27:03 +0200 (CEST) Date: Tue, 17 May 2022 09:27:03 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Jaehoon Chung Cc: Peng Fan , Priyanka Jain , Sinan Akman , u-boot@lists.denx.de Subject: Re: [PATCH 2/2] mmc: fsl_esdhc: Add new config option for default fallback mode Message-ID: <20220517072703.jbyd22rra4nqqi2f@pali> References: <20220511182713.26790-1-pali@kernel.org> <20220511182713.26790-2-pali@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tuesday 17 May 2022 08:40:48 Jaehoon Chung wrote: > On 5/12/22 03:27, Pali Rohár wrote: > > Currently default fallback SDHC mode is 1-bit. Add new config option > > CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback > > mode. This is useful e.g. for SPL builds which loads other parts from SD > > card during boot process. > > > > Signed-off-by: Pali Rohár > > --- > > drivers/mmc/Kconfig | 5 +++++ > > drivers/mmc/fsl_esdhc.c | 1 + > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig > > index f04cc44e1973..df15dff6248f 100644 > > --- a/drivers/mmc/Kconfig > > +++ b/drivers/mmc/Kconfig > > @@ -826,6 +826,11 @@ config FSL_ESDHC_VS33_NOT_SUPPORT > > For eSDHC, power supply is through peripheral circuit. 3.3V support is > > common. Select this if 3.3V power supply not supported. > > > > +config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH > > + int > > + depends on FSL_ESDHC > > + default 1 > > Is there any reason not to use dt? This is fallback value for function fsl_esdhc_mmc_init() which is called when DT is not parsed or used (yet). E.g. this applies for P2020 SPL. > Best Regards, > Jaehoon Chung > > > + > > config FSL_ESDHC_IMX > > bool "Freescale/NXP i.MX eSDHC controller support" > > help > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > > index 834f8933b0c6..a4c22942c2be 100644 > > --- a/drivers/mmc/fsl_esdhc.c > > +++ b/drivers/mmc/fsl_esdhc.c > > @@ -988,6 +988,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) > > > > cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); > > cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; > > + cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; > > /* Prefer peripheral clock which provides higher frequency. */ > > if (gd->arch.sdhc_per_clk) > > cfg->sdhc_clk = gd->arch.sdhc_per_clk; >